.. | .. |
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71 | 71 | arm_pm_idle(); |
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72 | 72 | else |
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73 | 73 | cpu_do_idle(); |
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| 74 | + hard_cond_local_irq_enable(); |
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74 | 75 | raw_local_irq_enable(); |
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75 | 76 | } |
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76 | 77 | |
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.. | .. |
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448 | 449 | return ret; |
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449 | 450 | } |
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450 | 451 | #endif |
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| 452 | + |
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| 453 | +#ifdef CONFIG_IRQ_PIPELINE |
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| 454 | + |
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| 455 | +/* |
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| 456 | + * When pipelining interrupts, we have to reconcile the hardware and |
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| 457 | + * the virtual states. Hard irqs are off on entry while the current |
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| 458 | + * stage has to be unstalled: fix this up by stalling the in-band |
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| 459 | + * stage on entry, unstalling on exit. |
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| 460 | + */ |
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| 461 | +asmlinkage void __sched arm_preempt_schedule_irq(void) |
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| 462 | +{ |
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| 463 | + WARN_ON_ONCE(irq_pipeline_debug() && test_inband_stall()); |
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| 464 | + stall_inband_nocheck(); |
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| 465 | + preempt_schedule_irq(); |
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| 466 | + unstall_inband_nocheck(); |
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| 467 | +} |
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| 468 | + |
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| 469 | +#else |
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| 470 | + |
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| 471 | +asmlinkage void __sched arm_preempt_schedule_irq(void) |
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| 472 | +{ |
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| 473 | + preempt_schedule_irq(); |
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| 474 | +} |
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| 475 | + |
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| 476 | +#endif |
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