rk3568 rt init

hc

2023-11-06 e3e12f52b214121840b44c91de5b3e5af5d3eb84

 kernel/sound/soc/rockchip/rockchip_i2s_tdm.h
..
..
@@ -144,12 +144,16 @@
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 #define I2S_DMACR_RDE_SHIFT	24
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 #define I2S_DMACR_RDE_DISABLE	(0 << I2S_DMACR_RDE_SHIFT)
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 #define I2S_DMACR_RDE_ENABLE	(1 << I2S_DMACR_RDE_SHIFT)
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+#define I2S_DMACR_RDE_MASK	(1 << I2S_DMACR_RDE_SHIFT)
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+#define I2S_DMACR_RDE(x)	((x) << I2S_DMACR_RDE_SHIFT)
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 #define I2S_DMACR_RDL_SHIFT	16
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 #define I2S_DMACR_RDL(x)	(((x) - 1) << I2S_DMACR_RDL_SHIFT)
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 #define I2S_DMACR_RDL_MASK	(0x1f << I2S_DMACR_RDL_SHIFT)
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 #define I2S_DMACR_TDE_SHIFT	8
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 #define I2S_DMACR_TDE_DISABLE	(0 << I2S_DMACR_TDE_SHIFT)
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 #define I2S_DMACR_TDE_ENABLE	(1 << I2S_DMACR_TDE_SHIFT)
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+#define I2S_DMACR_TDE_MASK	(1 << I2S_DMACR_TDE_SHIFT)
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+#define I2S_DMACR_TDE(x)	((x) << I2S_DMACR_TDE_SHIFT)
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 #define I2S_DMACR_TDL_SHIFT	0
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 #define I2S_DMACR_TDL(x)	((x) << I2S_DMACR_TDL_SHIFT)
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 #define I2S_DMACR_TDL_MASK	(0x1f << I2S_DMACR_TDL_SHIFT)
..
..
@@ -162,8 +166,8 @@
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 #define I2S_INTCR_RFT(x)	(((x) - 1) << I2S_INTCR_RFT_SHIFT)
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 #define I2S_INTCR_RXOIC		BIT(18)
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 #define I2S_INTCR_RXOIE_SHIFT	17
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-#define I2S_INTCR_RXOIE_DISABLE	(0 << I2S_INTCR_RXOIE_SHIFT)
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-#define I2S_INTCR_RXOIE_ENABLE	(1 << I2S_INTCR_RXOIE_SHIFT)
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+#define I2S_INTCR_RXOIE_MASK	(1 << I2S_INTCR_RXOIE_SHIFT)
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+#define I2S_INTCR_RXOIE(x)	((x) << I2S_INTCR_RXOIE_SHIFT)
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 #define I2S_INTCR_RXFIE_SHIFT	16
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 #define I2S_INTCR_RXFIE_DISABLE	(0 << I2S_INTCR_RXFIE_SHIFT)
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 #define I2S_INTCR_RXFIE_ENABLE	(1 << I2S_INTCR_RXFIE_SHIFT)
..
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@@ -172,8 +176,8 @@
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 #define I2S_INTCR_TFT_MASK	(0x1f << I2S_INTCR_TFT_SHIFT)
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 #define I2S_INTCR_TXUIC		BIT(2)
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 #define I2S_INTCR_TXUIE_SHIFT	1
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-#define I2S_INTCR_TXUIE_DISABLE	(0 << I2S_INTCR_TXUIE_SHIFT)
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-#define I2S_INTCR_TXUIE_ENABLE	(1 << I2S_INTCR_TXUIE_SHIFT)
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+#define I2S_INTCR_TXUIE_MASK	(1 << I2S_INTCR_TXUIE_SHIFT)
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+#define I2S_INTCR_TXUIE(x)	((x) << I2S_INTCR_TXUIE_SHIFT)
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 /*
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  * INTSR
..
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@@ -199,12 +203,37 @@
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  * XFER
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  * Transfer start register
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  */
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+/*
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+ * lp mode2 swap:
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+ * i2s sdi0_l <- i2s sdo0_l
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+ * i2s sdi0_r <- codec sdo_r
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+ *
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+ * lp mode2:
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+ * i2s sdi0_l <- codec sdo_l
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+ * i2s sdi0_r <- i2s sdo0_r
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+ *
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+ * lp mode1:
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+ * i2s sdi0_l <- codec sdo_l
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+ * i2s sdi0_r <- codec sdo_r
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+ * i2s sdi1_l <- i2s sdo0_l
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+ * i2s sdi1_r <- i2s sdo0_r
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+ *
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+ */
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+#define I2S_XFER_LP_MODE_MASK	GENMASK(4, 2)
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+#define I2S_XFER_LP_MODE_2_SWAP	(BIT(4) | BIT(3))
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+#define I2S_XFER_LP_MODE_2	BIT(3)
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+#define I2S_XFER_LP_MODE_1	BIT(2)
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+#define I2S_XFER_LP_MODE_DIS	0
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 #define I2S_XFER_RXS_SHIFT	1
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 #define I2S_XFER_RXS_STOP	(0 << I2S_XFER_RXS_SHIFT)
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 #define I2S_XFER_RXS_START	(1 << I2S_XFER_RXS_SHIFT)
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+#define I2S_XFER_RXS_MASK	(1 << I2S_XFER_RXS_SHIFT)
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+#define I2S_XFER_RXS(x)		((x) << I2S_XFER_RXS_SHIFT)
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 #define I2S_XFER_TXS_SHIFT	0
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 #define I2S_XFER_TXS_STOP	(0 << I2S_XFER_TXS_SHIFT)
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 #define I2S_XFER_TXS_START	(1 << I2S_XFER_TXS_SHIFT)
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+#define I2S_XFER_TXS_MASK	(1 << I2S_XFER_TXS_SHIFT)
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+#define I2S_XFER_TXS(x)		((x) << I2S_XFER_TXS_SHIFT)
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 /*
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  * CLR