rk3568 rt init

hc

2023-11-06 e3e12f52b214121840b44c91de5b3e5af5d3eb84

 kernel/sound/soc/rockchip/rockchip_i2s_tdm.c
..
..
@@ -35,10 +35,15 @@
35
35
 #endif
36
36
 
37
37
 #define DEFAULT_MCLK_FS				256
38
+#define DEFAULT_FS				48000
38
39
 #define CH_GRP_MAX				4  /* The max channel 8 / 2 */
39
40
 #define MULTIPLEX_CH_MAX			10
40
41
 #define CLK_PPM_MIN				(-1000)
41
42
 #define CLK_PPM_MAX				(1000)
43
+#define MAXBURST_PER_FIFO			8
44
+
45
+#define QUIRK_ALWAYS_ON				BIT(0)
46
+#define QUIRK_HDMI_PATH				BIT(1)
42
47
 
43
48
 struct txrx_config {
44
49
 	u32 addr;
..
..
@@ -79,6 +84,7 @@
79
84
 	struct regmap *grf;
80
85
 	struct snd_dmaengine_dai_dma_data capture_dma_data;
81
86
 	struct snd_dmaengine_dai_dma_data playback_dma_data;
87
+	struct snd_pcm_substream *substreams[SNDRV_PCM_STREAM_LAST + 1];
82
88
 	struct reset_control *tx_reset;
83
89
 	struct reset_control *rx_reset;
84
90
 	const struct rk_i2s_soc_data *soc_data;
..
..
@@ -102,9 +108,24 @@
102
108
 	unsigned int clk_trcm;
103
109
 	unsigned int i2s_sdis[CH_GRP_MAX];
104
110
 	unsigned int i2s_sdos[CH_GRP_MAX];
111
+	unsigned int quirks;
105
112
 	int clk_ppm;
106
113
 	atomic_t refcount;
107
114
 	spinlock_t lock; /* xfer lock */
115
+};
116
+
117
+static struct i2s_of_quirks {
118
+	char *quirk;
119
+	int id;
120
+} of_quirks[] = {
121
+	{
122
+		.quirk = "rockchip,always-on",
123
+		.id = QUIRK_ALWAYS_ON,
124
+	},
125
+	{
126
+		.quirk = "rockchip,hdmi-path",
127
+		.id = QUIRK_HDMI_PATH,
128
+	},
108
129
 };
109
130
 
110
131
 static int to_ch_num(unsigned int val)
..
..
@@ -134,10 +155,9 @@
134
155
 	struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
135
156
 
136
157
 	regcache_cache_only(i2s_tdm->regmap, true);
137
-	if (!IS_ERR(i2s_tdm->mclk_tx))
138
-		clk_disable_unprepare(i2s_tdm->mclk_tx);
139
-	if (!IS_ERR(i2s_tdm->mclk_rx))
140
-		clk_disable_unprepare(i2s_tdm->mclk_rx);
158
+
159
+	clk_disable_unprepare(i2s_tdm->mclk_tx);
160
+	clk_disable_unprepare(i2s_tdm->mclk_rx);
141
161
 
142
162
 	return 0;
143
163
 }
..
..
@@ -147,28 +167,45 @@
147
167
 	struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(dev);
148
168
 	int ret;
149
169
 
150
-	if (!IS_ERR(i2s_tdm->mclk_tx))
151
-		clk_prepare_enable(i2s_tdm->mclk_tx);
152
-	if (!IS_ERR(i2s_tdm->mclk_rx))
153
-		clk_prepare_enable(i2s_tdm->mclk_rx);
170
+	ret = clk_prepare_enable(i2s_tdm->mclk_tx);
171
+	if (ret)
172
+		goto err_mclk_tx;
173
+
174
+	ret = clk_prepare_enable(i2s_tdm->mclk_rx);
175
+	if (ret)
176
+		goto err_mclk_rx;
154
177
 
155
178
 	regcache_cache_only(i2s_tdm->regmap, false);
156
179
 	regcache_mark_dirty(i2s_tdm->regmap);
157
-
158
180
 	ret = regcache_sync(i2s_tdm->regmap);
159
-	if (ret) {
160
-		if (!IS_ERR(i2s_tdm->mclk_tx))
161
-			clk_disable_unprepare(i2s_tdm->mclk_tx);
162
-		if (!IS_ERR(i2s_tdm->mclk_rx))
163
-			clk_disable_unprepare(i2s_tdm->mclk_rx);
164
-	}
181
+	if (ret)
182
+		goto err_regmap;
165
183
 
184
+	return 0;
185
+
186
+err_regmap:
187
+	clk_disable_unprepare(i2s_tdm->mclk_rx);
188
+err_mclk_rx:
189
+	clk_disable_unprepare(i2s_tdm->mclk_tx);
190
+err_mclk_tx:
166
191
 	return ret;
167
192
 }
168
193
 
169
194
 static inline struct rk_i2s_tdm_dev *to_info(struct snd_soc_dai *dai)
170
195
 {
171
196
 	return snd_soc_dai_get_drvdata(dai);
197
+}
198
+
199
+static inline bool is_stream_active(struct rk_i2s_tdm_dev *i2s_tdm, int stream)
200
+{
201
+	unsigned int val;
202
+
203
+	regmap_read(i2s_tdm->regmap, I2S_XFER, &val);
204
+
205
+	if (stream == SNDRV_PCM_STREAM_PLAYBACK)
206
+		return (val & I2S_XFER_TXS_START);
207
+	else
208
+		return (val & I2S_XFER_RXS_START);
172
209
 }
173
210
 
174
211
 #ifdef HAVE_SYNC_RESET
..
..
@@ -180,7 +217,7 @@
180
217
 #define writeq(v,c) ({ __iowmb(); __raw_writeq((__force u64) cpu_to_le64(v), c); })
181
218
 #endif
182
219
 
183
-static void rockchip_snd_xfer_reset_assert(struct rk_i2s_tdm_dev *i2s_tdm)
220
+static void rockchip_i2s_tdm_reset_assert(struct rk_i2s_tdm_dev *i2s_tdm)
184
221
 {
185
222
 	int tx_bank, rx_bank, tx_offset, rx_offset, tx_id, rx_id;
186
223
 	void __iomem *cru_reset, *addr;
..
..
@@ -229,7 +266,7 @@
229
266
 			writeq(val, addr);
230
267
 			break;
231
268
 		}
232
-		/* fall through */
269
+		/* fallthrough */
233
270
 	default:
234
271
 		local_irq_save(flags);
235
272
 		writel(BIT(tx_offset) | (BIT(tx_offset) << 16),
..
..
@@ -243,7 +280,7 @@
243
280
 	udelay(10);
244
281
 }
245
282
 
246
-static void rockchip_snd_xfer_reset_deassert(struct rk_i2s_tdm_dev *i2s_tdm)
283
+static void rockchip_i2s_tdm_reset_deassert(struct rk_i2s_tdm_dev *i2s_tdm)
247
284
 {
248
285
 	int tx_bank, rx_bank, tx_offset, rx_offset, tx_id, rx_id;
249
286
 	void __iomem *cru_reset, *addr;
..
..
@@ -291,7 +328,7 @@
291
328
 			writeq(val, addr);
292
329
 			break;
293
330
 		}
294
-		/* fall through */
331
+		/* fallthrough */
295
332
 	default:
296
333
 		local_irq_save(flags);
297
334
 		writel((BIT(tx_offset) << 16),
..
..
@@ -309,94 +346,26 @@
309
346
  * make sure both tx and rx are reset at the same time for sync lrck
310
347
  * when clk_trcm > 0
311
348
  */
312
-static void rockchip_snd_xfer_sync_reset(struct rk_i2s_tdm_dev *i2s_tdm)
349
+static void rockchip_i2s_tdm_sync_reset(struct rk_i2s_tdm_dev *i2s_tdm)
313
350
 {
314
-	rockchip_snd_xfer_reset_assert(i2s_tdm);
315
-	rockchip_snd_xfer_reset_deassert(i2s_tdm);
351
+	rockchip_i2s_tdm_reset_assert(i2s_tdm);
352
+	rockchip_i2s_tdm_reset_deassert(i2s_tdm);
316
353
 }
317
354
 #else
318
-static inline void rockchip_snd_xfer_reset_assert(struct rk_i2s_tdm_dev *i2s_tdm)
355
+static inline void rockchip_i2s_tdm_reset_assert(struct rk_i2s_tdm_dev *i2s_tdm)
319
356
 {
320
357
 }
321
-static inline void rockchip_snd_xfer_reset_deassert(struct rk_i2s_tdm_dev *i2s_tdm)
358
+static inline void rockchip_i2s_tdm_reset_deassert(struct rk_i2s_tdm_dev *i2s_tdm)
322
359
 {
323
360
 }
324
-static inline void rockchip_snd_xfer_sync_reset(struct rk_i2s_tdm_dev *i2s_tdm)
361
+static inline void rockchip_i2s_tdm_sync_reset(struct rk_i2s_tdm_dev *i2s_tdm)
325
362
 {
326
363
 }
327
364
 #endif
328
365
 
329
-/* only used when clk_trcm > 0 */
330
-static void rockchip_snd_txrxctrl(struct snd_pcm_substream *substream,
331
-				  struct snd_soc_dai *dai, int on)
366
+static void rockchip_i2s_tdm_reset(struct reset_control *rc)
332
367
 {
333
-	struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
334
-	unsigned int val = 0;
335
-	unsigned long flags;
336
-	int retry = 10;
337
-
338
-	spin_lock_irqsave(&i2s_tdm->lock, flags);
339
-	if (on) {
340
-		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
341
-			regmap_update_bits(i2s_tdm->regmap, I2S_DMACR,
342
-					   I2S_DMACR_TDE_ENABLE,
343
-					   I2S_DMACR_TDE_ENABLE);
344
-		else
345
-			regmap_update_bits(i2s_tdm->regmap, I2S_DMACR,
346
-					   I2S_DMACR_RDE_ENABLE,
347
-					   I2S_DMACR_RDE_ENABLE);
348
-
349
-		if (atomic_inc_return(&i2s_tdm->refcount) == 1) {
350
-			rockchip_snd_xfer_reset_assert(i2s_tdm);
351
-			regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
352
-					   I2S_XFER_TXS_START |
353
-					   I2S_XFER_RXS_START,
354
-					   I2S_XFER_TXS_START |
355
-					   I2S_XFER_RXS_START);
356
-			rockchip_snd_xfer_reset_deassert(i2s_tdm);
357
-		}
358
-	} else {
359
-		if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
360
-			regmap_update_bits(i2s_tdm->regmap, I2S_DMACR,
361
-					   I2S_DMACR_TDE_ENABLE,
362
-					   I2S_DMACR_TDE_DISABLE);
363
-		else
364
-			regmap_update_bits(i2s_tdm->regmap, I2S_DMACR,
365
-					   I2S_DMACR_RDE_ENABLE,
366
-					   I2S_DMACR_RDE_DISABLE);
367
-
368
-		if (atomic_dec_and_test(&i2s_tdm->refcount)) {
369
-			regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
370
-					   I2S_XFER_TXS_START |
371
-					   I2S_XFER_RXS_START,
372
-					   I2S_XFER_TXS_STOP |
373
-					   I2S_XFER_RXS_STOP);
374
-
375
-			udelay(150);
376
-			regmap_update_bits(i2s_tdm->regmap, I2S_CLR,
377
-					   I2S_CLR_TXC | I2S_CLR_RXC,
378
-					   I2S_CLR_TXC | I2S_CLR_RXC);
379
-
380
-			regmap_read(i2s_tdm->regmap, I2S_CLR, &val);
381
-
382
-			/* Should wait for clear operation to finish */
383
-			while (val) {
384
-				regmap_read(i2s_tdm->regmap, I2S_CLR, &val);
385
-				retry--;
386
-				if (!retry) {
387
-					dev_info(i2s_tdm->dev, "reset txrx\n");
388
-					rockchip_snd_xfer_sync_reset(i2s_tdm);
389
-					break;
390
-				}
391
-			}
392
-		}
393
-	}
394
-	spin_unlock_irqrestore(&i2s_tdm->lock, flags);
395
-}
396
-
397
-static void rockchip_snd_reset(struct reset_control *rc)
398
-{
399
-	if (IS_ERR(rc))
368
+	if (IS_ERR_OR_NULL(rc))
400
369
 		return;
401
370
 
402
371
 	reset_control_assert(rc);
..
..
@@ -407,92 +376,264 @@
407
376
 	udelay(10);
408
377
 }
409
378
 
410
-static void rockchip_snd_txctrl(struct rk_i2s_tdm_dev *i2s_tdm, int on)
379
+static int rockchip_i2s_tdm_clear(struct rk_i2s_tdm_dev *i2s_tdm,
380
+				  unsigned int clr)
411
381
 {
382
+	struct reset_control *rst = NULL;
412
383
 	unsigned int val = 0;
413
-	int retry = 10;
384
+	int ret = 0;
414
385
 
415
-	if (on) {
416
-		regmap_update_bits(i2s_tdm->regmap, I2S_DMACR,
417
-				   I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_ENABLE);
386
+	switch (clr) {
387
+	case I2S_CLR_TXC:
388
+		rst = i2s_tdm->tx_reset;
389
+		break;
390
+	case I2S_CLR_RXC:
391
+		rst = i2s_tdm->rx_reset;
392
+		break;
393
+	case I2S_CLR_TXC | I2S_CLR_RXC:
394
+		break;
395
+	default:
396
+		return -EINVAL;
397
+	}
418
398
 
419
-		regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
420
-				   I2S_XFER_TXS_START,
421
-				   I2S_XFER_TXS_START);
399
+	/*
400
+	 * Workaround for FIFO clear on SLAVE mode:
401
+	 *
402
+	 * A Suggest to do reset hclk domain and then do mclk
403
+	 *   domain, especially for SLAVE mode without CLK in.
404
+	 *   at last, recovery regmap config.
405
+	 *
406
+	 * B Suggest to switch to MASTER, and then do FIFO clr,
407
+	 *   at last, bring back to SLAVE.
408
+	 *
409
+	 * Now we choose plan B here.
410
+	 */
411
+	if (!i2s_tdm->is_master_mode)
412
+		regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
413
+				   I2S_CKR_MSS_MASK, I2S_CKR_MSS_MASTER);
414
+	regmap_update_bits(i2s_tdm->regmap, I2S_CLR, clr, clr);
415
+	ret = regmap_read_poll_timeout_atomic(i2s_tdm->regmap, I2S_CLR, val,
416
+					      !(val & clr), 10, 100);
417
+	if (!i2s_tdm->is_master_mode)
418
+		regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
419
+				   I2S_CKR_MSS_MASK, I2S_CKR_MSS_SLAVE);
420
+
421
+	if (ret < 0) {
422
+		dev_warn(i2s_tdm->dev, "failed to clear %u on %s mode\n",
423
+			 clr, i2s_tdm->is_master_mode ? "master" : "slave");
424
+		goto reset;
425
+	}
426
+
427
+	return 0;
428
+
429
+reset:
430
+	if (i2s_tdm->clk_trcm)
431
+		rockchip_i2s_tdm_sync_reset(i2s_tdm);
432
+	else
433
+		rockchip_i2s_tdm_reset(rst);
434
+
435
+	return 0;
436
+}
437
+
438
+/*
439
+ * HDMI controller ignores the first FRAME_SYNC cycle, Lost one frame is no big deal
440
+ * for LPCM, but it does matter for Bitstream (NLPCM/HBR), So, padding one frame
441
+ * before xfer the real data to fix it.
442
+ */
443
+static void rockchip_i2s_tdm_tx_fifo_padding(struct rk_i2s_tdm_dev *i2s_tdm, bool en)
444
+{
445
+	unsigned int val, w, c, i;
446
+
447
+	if (!en)
448
+		return;
449
+
450
+	regmap_read(i2s_tdm->regmap, I2S_TXCR, &val);
451
+	w = ((val & I2S_TXCR_VDW_MASK) >> I2S_TXCR_VDW_SHIFT) + 1;
452
+	c = to_ch_num(val & I2S_TXCR_CSR_MASK) * w / 32;
453
+
454
+	for (i = 0; i < c; i++)
455
+		regmap_write(i2s_tdm->regmap, I2S_TXDR, 0x0);
456
+}
457
+
458
+static void rockchip_i2s_tdm_fifo_xrun_detect(struct rk_i2s_tdm_dev *i2s_tdm,
459
+					      int stream, bool en)
460
+{
461
+	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
462
+		/* clear irq status which was asserted before TXUIE enabled */
463
+		regmap_update_bits(i2s_tdm->regmap, I2S_INTCR,
464
+				   I2S_INTCR_TXUIC, I2S_INTCR_TXUIC);
465
+		regmap_update_bits(i2s_tdm->regmap, I2S_INTCR,
466
+				   I2S_INTCR_TXUIE_MASK,
467
+				   I2S_INTCR_TXUIE(en));
422
468
 	} else {
423
-		regmap_update_bits(i2s_tdm->regmap, I2S_DMACR,
424
-				   I2S_DMACR_TDE_ENABLE, I2S_DMACR_TDE_DISABLE);
425
-
426
-		regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
427
-				   I2S_XFER_TXS_START,
428
-				   I2S_XFER_TXS_STOP);
429
-
430
-		udelay(150);
431
-		if (i2s_tdm->is_master_mode) {
432
-			regmap_update_bits(i2s_tdm->regmap, I2S_CLR,
433
-					   I2S_CLR_TXC,
434
-					   I2S_CLR_TXC);
435
-
436
-			regmap_read(i2s_tdm->regmap, I2S_CLR, &val);
437
-
438
-			/* Should wait for clear operation to finish */
439
-			while (val) {
440
-				regmap_read(i2s_tdm->regmap, I2S_CLR, &val);
441
-				retry--;
442
-				if (!retry) {
443
-					dev_warn(i2s_tdm->dev, "reset tx\n");
444
-					rockchip_snd_reset(i2s_tdm->tx_reset);
445
-					break;
446
-				}
447
-			}
448
-		} else {
449
-			rockchip_snd_reset(i2s_tdm->tx_reset);
450
-		}
469
+		/* clear irq status which was asserted before RXOIE enabled */
470
+		regmap_update_bits(i2s_tdm->regmap, I2S_INTCR,
471
+				   I2S_INTCR_RXOIC, I2S_INTCR_RXOIC);
472
+		regmap_update_bits(i2s_tdm->regmap, I2S_INTCR,
473
+				   I2S_INTCR_RXOIE_MASK,
474
+				   I2S_INTCR_RXOIE(en));
451
475
 	}
452
476
 }
453
477
 
454
-static void rockchip_snd_rxctrl(struct rk_i2s_tdm_dev *i2s_tdm, int on)
478
+static void rockchip_i2s_tdm_dma_ctrl(struct rk_i2s_tdm_dev *i2s_tdm,
479
+				      int stream, bool en)
455
480
 {
456
-	unsigned int val = 0;
457
-	int retry = 10;
481
+	if (!en)
482
+		rockchip_i2s_tdm_fifo_xrun_detect(i2s_tdm, stream, 0);
458
483
 
459
-	if (on) {
484
+	if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
485
+		if (i2s_tdm->quirks & QUIRK_HDMI_PATH)
486
+			rockchip_i2s_tdm_tx_fifo_padding(i2s_tdm, en);
487
+
460
488
 		regmap_update_bits(i2s_tdm->regmap, I2S_DMACR,
461
-				   I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_ENABLE);
462
-
463
-		regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
464
-				   I2S_XFER_RXS_START,
465
-				   I2S_XFER_RXS_START);
489
+				   I2S_DMACR_TDE_MASK,
490
+				   I2S_DMACR_TDE(en));
491
+		/*
492
+		 * Explicitly delay 1 usec for dma to fill FIFO,
493
+		 * though there was a implied HW delay that around
494
+		 * half LRCK cycle (e.g. 2.6us@192k) from XFER-start
495
+		 * to FIFO-pop.
496
+		 *
497
+		 * 1 usec is enough to fill at lease 4 entry each FIFO
498
+		 * @192k 8ch 32bit situation.
499
+		 */
500
+		udelay(1);
466
501
 	} else {
467
502
 		regmap_update_bits(i2s_tdm->regmap, I2S_DMACR,
468
-				   I2S_DMACR_RDE_ENABLE, I2S_DMACR_RDE_DISABLE);
469
-
470
-		regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
471
-				   I2S_XFER_RXS_START,
472
-				   I2S_XFER_RXS_STOP);
473
-
474
-		udelay(150);
475
-		if (i2s_tdm->is_master_mode) {
476
-			regmap_update_bits(i2s_tdm->regmap, I2S_CLR,
477
-					   I2S_CLR_RXC,
478
-					   I2S_CLR_RXC);
479
-
480
-			regmap_read(i2s_tdm->regmap, I2S_CLR, &val);
481
-
482
-			/* Should wait for clear operation to finish */
483
-			while (val) {
484
-				regmap_read(i2s_tdm->regmap, I2S_CLR, &val);
485
-				retry--;
486
-				if (!retry) {
487
-					dev_warn(i2s_tdm->dev, "reset rx\n");
488
-					rockchip_snd_reset(i2s_tdm->rx_reset);
489
-					break;
490
-				}
491
-			}
492
-		} else {
493
-			rockchip_snd_reset(i2s_tdm->rx_reset);
494
-		}
503
+				   I2S_DMACR_RDE_MASK,
504
+				   I2S_DMACR_RDE(en));
495
505
 	}
506
+
507
+	if (en)
508
+		rockchip_i2s_tdm_fifo_xrun_detect(i2s_tdm, stream, 1);
509
+}
510
+
511
+static void rockchip_i2s_tdm_xfer_start(struct rk_i2s_tdm_dev *i2s_tdm,
512
+					int stream)
513
+{
514
+	if (i2s_tdm->clk_trcm) {
515
+		rockchip_i2s_tdm_reset_assert(i2s_tdm);
516
+		regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
517
+				   I2S_XFER_TXS_MASK |
518
+				   I2S_XFER_RXS_MASK,
519
+				   I2S_XFER_TXS_START |
520
+				   I2S_XFER_RXS_START);
521
+		rockchip_i2s_tdm_reset_deassert(i2s_tdm);
522
+	} else if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
523
+		regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
524
+				   I2S_XFER_TXS_MASK,
525
+				   I2S_XFER_TXS_START);
526
+	} else {
527
+		regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
528
+				   I2S_XFER_RXS_MASK,
529
+				   I2S_XFER_RXS_START);
530
+	}
531
+}
532
+
533
+static void rockchip_i2s_tdm_xfer_stop(struct rk_i2s_tdm_dev *i2s_tdm,
534
+				       int stream, bool force)
535
+{
536
+	unsigned int msk, val, clr;
537
+
538
+	if (i2s_tdm->quirks & QUIRK_ALWAYS_ON && !force)
539
+		return;
540
+
541
+	if (i2s_tdm->clk_trcm) {
542
+		msk = I2S_XFER_TXS_MASK | I2S_XFER_RXS_MASK;
543
+		val = I2S_XFER_TXS_STOP | I2S_XFER_RXS_STOP;
544
+		clr = I2S_CLR_TXC | I2S_CLR_RXC;
545
+	} else if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
546
+		msk = I2S_XFER_TXS_MASK;
547
+		val = I2S_XFER_TXS_STOP;
548
+		clr = I2S_CLR_TXC;
549
+	} else {
550
+		msk = I2S_XFER_RXS_MASK;
551
+		val = I2S_XFER_RXS_STOP;
552
+		clr = I2S_CLR_RXC;
553
+	}
554
+
555
+	regmap_update_bits(i2s_tdm->regmap, I2S_XFER, msk, val);
556
+
557
+	/* delay for LRCK signal integrity */
558
+	udelay(150);
559
+
560
+	rockchip_i2s_tdm_clear(i2s_tdm, clr);
561
+}
562
+
563
+static void rockchip_i2s_tdm_xfer_trcm_start(struct rk_i2s_tdm_dev *i2s_tdm)
564
+{
565
+	unsigned long flags;
566
+
567
+	spin_lock_irqsave(&i2s_tdm->lock, flags);
568
+	if (atomic_inc_return(&i2s_tdm->refcount) == 1)
569
+		rockchip_i2s_tdm_xfer_start(i2s_tdm, 0);
570
+	spin_unlock_irqrestore(&i2s_tdm->lock, flags);
571
+}
572
+
573
+static void rockchip_i2s_tdm_xfer_trcm_stop(struct rk_i2s_tdm_dev *i2s_tdm)
574
+{
575
+	unsigned long flags;
576
+
577
+	spin_lock_irqsave(&i2s_tdm->lock, flags);
578
+	if (atomic_dec_and_test(&i2s_tdm->refcount))
579
+		rockchip_i2s_tdm_xfer_stop(i2s_tdm, 0, false);
580
+	spin_unlock_irqrestore(&i2s_tdm->lock, flags);
581
+}
582
+
583
+static void rockchip_i2s_tdm_trcm_pause(struct snd_pcm_substream *substream,
584
+					struct rk_i2s_tdm_dev *i2s_tdm)
585
+{
586
+	int stream = substream->stream;
587
+	int bstream = SNDRV_PCM_STREAM_LAST - stream;
588
+
589
+	/* disable dma for both tx and rx */
590
+	rockchip_i2s_tdm_dma_ctrl(i2s_tdm, stream, 0);
591
+	rockchip_i2s_tdm_dma_ctrl(i2s_tdm, bstream, 0);
592
+	rockchip_i2s_tdm_xfer_stop(i2s_tdm, bstream, true);
593
+}
594
+
595
+static void rockchip_i2s_tdm_trcm_resume(struct snd_pcm_substream *substream,
596
+					 struct rk_i2s_tdm_dev *i2s_tdm)
597
+{
598
+	int bstream = SNDRV_PCM_STREAM_LAST - substream->stream;
599
+
600
+	/*
601
+	 * just resume bstream, because current stream will be
602
+	 * startup in the trigger-cmd-START
603
+	 */
604
+	rockchip_i2s_tdm_dma_ctrl(i2s_tdm, bstream, 1);
605
+	rockchip_i2s_tdm_xfer_start(i2s_tdm, bstream);
606
+}
607
+
608
+static void rockchip_i2s_tdm_start(struct rk_i2s_tdm_dev *i2s_tdm, int stream)
609
+{
610
+	/*
611
+	 * On HDMI-PATH-ALWAYS-ON situation, we almost keep XFER always on,
612
+	 * so, for new data start, suggested to STOP-CLEAR-START to make sure
613
+	 * data aligned.
614
+	 */
615
+	if ((i2s_tdm->quirks & QUIRK_HDMI_PATH) &&
616
+	    (i2s_tdm->quirks & QUIRK_ALWAYS_ON) &&
617
+	    (stream == SNDRV_PCM_STREAM_PLAYBACK)) {
618
+		rockchip_i2s_tdm_xfer_stop(i2s_tdm, stream, true);
619
+	}
620
+
621
+	rockchip_i2s_tdm_dma_ctrl(i2s_tdm, stream, 1);
622
+
623
+	if (i2s_tdm->clk_trcm)
624
+		rockchip_i2s_tdm_xfer_trcm_start(i2s_tdm);
625
+	else
626
+		rockchip_i2s_tdm_xfer_start(i2s_tdm, stream);
627
+}
628
+
629
+static void rockchip_i2s_tdm_stop(struct rk_i2s_tdm_dev *i2s_tdm, int stream)
630
+{
631
+	rockchip_i2s_tdm_dma_ctrl(i2s_tdm, stream, 0);
632
+
633
+	if (i2s_tdm->clk_trcm)
634
+		rockchip_i2s_tdm_xfer_trcm_stop(i2s_tdm);
635
+	else
636
+		rockchip_i2s_tdm_xfer_stop(i2s_tdm, stream, false);
496
637
 }
497
638
 
498
639
 static int rockchip_i2s_tdm_set_fmt(struct snd_soc_dai *cpu_dai,
..
..
@@ -659,72 +800,6 @@
659
800
 	return ret;
660
801
 }
661
802
 
662
-static void rockchip_i2s_tdm_xfer_pause(struct snd_pcm_substream *substream,
663
-					struct rk_i2s_tdm_dev *i2s_tdm)
664
-{
665
-	int stream;
666
-	unsigned int val = 0;
667
-	int retry = 10;
668
-
669
-	stream = SNDRV_PCM_STREAM_LAST - substream->stream;
670
-	if (stream == SNDRV_PCM_STREAM_PLAYBACK)
671
-		regmap_update_bits(i2s_tdm->regmap, I2S_DMACR,
672
-				   I2S_DMACR_TDE_ENABLE,
673
-				   I2S_DMACR_TDE_DISABLE);
674
-	else
675
-		regmap_update_bits(i2s_tdm->regmap, I2S_DMACR,
676
-				   I2S_DMACR_RDE_ENABLE,
677
-				   I2S_DMACR_RDE_DISABLE);
678
-
679
-	regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
680
-			   I2S_XFER_TXS_START |
681
-			   I2S_XFER_RXS_START,
682
-			   I2S_XFER_TXS_STOP |
683
-			   I2S_XFER_RXS_STOP);
684
-
685
-	udelay(150);
686
-	regmap_update_bits(i2s_tdm->regmap, I2S_CLR,
687
-			   I2S_CLR_TXC | I2S_CLR_RXC,
688
-			   I2S_CLR_TXC | I2S_CLR_RXC);
689
-
690
-	regmap_read(i2s_tdm->regmap, I2S_CLR, &val);
691
-
692
-	/* Should wait for clear operation to finish */
693
-	while (val) {
694
-		regmap_read(i2s_tdm->regmap, I2S_CLR, &val);
695
-		retry--;
696
-		if (!retry) {
697
-			dev_info(i2s_tdm->dev, "reset txrx\n");
698
-			rockchip_snd_xfer_sync_reset(i2s_tdm);
699
-			break;
700
-		}
701
-	}
702
-}
703
-
704
-static void rockchip_i2s_tdm_xfer_resume(struct snd_pcm_substream *substream,
705
-					 struct rk_i2s_tdm_dev *i2s_tdm)
706
-{
707
-	int stream;
708
-
709
-	stream = SNDRV_PCM_STREAM_LAST - substream->stream;
710
-	if (stream == SNDRV_PCM_STREAM_PLAYBACK)
711
-		regmap_update_bits(i2s_tdm->regmap, I2S_DMACR,
712
-				   I2S_DMACR_TDE_ENABLE,
713
-				   I2S_DMACR_TDE_ENABLE);
714
-	else
715
-		regmap_update_bits(i2s_tdm->regmap, I2S_DMACR,
716
-				   I2S_DMACR_RDE_ENABLE,
717
-				   I2S_DMACR_RDE_ENABLE);
718
-
719
-	rockchip_snd_xfer_reset_assert(i2s_tdm);
720
-	regmap_update_bits(i2s_tdm->regmap, I2S_XFER,
721
-			   I2S_XFER_TXS_START |
722
-			   I2S_XFER_RXS_START,
723
-			   I2S_XFER_TXS_START |
724
-			   I2S_XFER_RXS_START);
725
-	rockchip_snd_xfer_reset_deassert(i2s_tdm);
726
-}
727
-
728
803
 static int rockchip_i2s_tdm_clk_set_rate(struct rk_i2s_tdm_dev *i2s_tdm,
729
804
 					 struct clk *clk, unsigned long rate,
730
805
 					 int ppm)
..
..
@@ -840,6 +915,28 @@
840
915
 	return ret;
841
916
 }
842
917
 
918
+static int rockchip_i2s_tdm_mclk_reparent(struct rk_i2s_tdm_dev *i2s_tdm)
919
+{
920
+	struct clk *parent;
921
+	int ret = 0;
922
+
923
+	/* reparent to the same clk on TRCM mode */
924
+	switch (i2s_tdm->clk_trcm) {
925
+	case I2S_CKR_TRCM_TXONLY:
926
+		parent = clk_get_parent(i2s_tdm->mclk_tx);
927
+		if (clk_has_parent(i2s_tdm->mclk_rx, parent))
928
+			ret = clk_set_parent(i2s_tdm->mclk_rx, parent);
929
+		break;
930
+	case I2S_CKR_TRCM_RXONLY:
931
+		parent = clk_get_parent(i2s_tdm->mclk_rx);
932
+		if (clk_has_parent(i2s_tdm->mclk_tx, parent))
933
+			ret = clk_set_parent(i2s_tdm->mclk_tx, parent);
934
+		break;
935
+	}
936
+
937
+	return ret;
938
+}
939
+
843
940
 static int rockchip_i2s_tdm_set_mclk(struct rk_i2s_tdm_dev *i2s_tdm,
844
941
 				     struct snd_pcm_substream *substream,
845
942
 				     struct clk **mclk)
..
..
@@ -862,6 +959,10 @@
862
959
 			goto err;
863
960
 
864
961
 		ret = clk_set_rate(i2s_tdm->mclk_rx, i2s_tdm->mclk_rx_freq);
962
+		if (ret)
963
+			goto err;
964
+
965
+		ret = rockchip_i2s_tdm_mclk_reparent(i2s_tdm);
865
966
 		if (ret)
866
967
 			goto err;
867
968
 
..
..
@@ -895,6 +996,9 @@
895
996
 	unsigned int val = 0;
896
997
 
897
998
 	if (!i2s_tdm->io_multiplex)
999
+		return 0;
1000
+
1001
+	if (IS_ERR(i2s_tdm->grf))
898
1002
 		return 0;
899
1003
 
900
1004
 	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
..
..
@@ -1006,24 +1110,18 @@
1006
1110
 	return false;
1007
1111
 }
1008
1112
 
1009
-static int rockchip_i2s_trcm_mode(struct snd_pcm_substream *substream,
1010
-				  struct snd_soc_dai *dai,
1011
-				  unsigned int div_bclk,
1012
-				  unsigned int div_lrck,
1013
-				  unsigned int fmt)
1113
+static int rockchip_i2s_tdm_params_trcm(struct snd_pcm_substream *substream,
1114
+					struct snd_soc_dai *dai,
1115
+					unsigned int div_bclk,
1116
+					unsigned int div_lrck,
1117
+					unsigned int fmt)
1014
1118
 {
1015
1119
 	struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
1016
1120
 	unsigned long flags;
1017
1121
 
1018
-	if (!i2s_tdm->clk_trcm)
1019
-		return 0;
1020
-
1021
-	if (!is_params_dirty(substream, dai, div_bclk, div_lrck, fmt))
1022
-		return 0;
1023
-
1024
1122
 	spin_lock_irqsave(&i2s_tdm->lock, flags);
1025
1123
 	if (atomic_read(&i2s_tdm->refcount))
1026
-		rockchip_i2s_tdm_xfer_pause(substream, i2s_tdm);
1124
+		rockchip_i2s_tdm_trcm_pause(substream, i2s_tdm);
1027
1125
 
1028
1126
 	regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV,
1029
1127
 			   I2S_CLKDIV_TXM_MASK | I2S_CLKDIV_RXM_MASK,
..
..
@@ -1042,8 +1140,56 @@
1042
1140
 				   fmt);
1043
1141
 
1044
1142
 	if (atomic_read(&i2s_tdm->refcount))
1045
-		rockchip_i2s_tdm_xfer_resume(substream, i2s_tdm);
1143
+		rockchip_i2s_tdm_trcm_resume(substream, i2s_tdm);
1046
1144
 	spin_unlock_irqrestore(&i2s_tdm->lock, flags);
1145
+
1146
+	return 0;
1147
+}
1148
+
1149
+static int rockchip_i2s_tdm_params(struct snd_pcm_substream *substream,
1150
+				   struct snd_soc_dai *dai,
1151
+				   unsigned int div_bclk,
1152
+				   unsigned int div_lrck,
1153
+				   unsigned int fmt)
1154
+{
1155
+	struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
1156
+	int stream = substream->stream;
1157
+
1158
+	if (is_stream_active(i2s_tdm, stream))
1159
+		rockchip_i2s_tdm_xfer_stop(i2s_tdm, stream, true);
1160
+
1161
+	if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1162
+		regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV,
1163
+				   I2S_CLKDIV_TXM_MASK,
1164
+				   I2S_CLKDIV_TXM(div_bclk));
1165
+		regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
1166
+				   I2S_CKR_TSD_MASK,
1167
+				   I2S_CKR_TSD(div_lrck));
1168
+		regmap_update_bits(i2s_tdm->regmap, I2S_TXCR,
1169
+				   I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK,
1170
+				   fmt);
1171
+	} else {
1172
+		regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV,
1173
+				   I2S_CLKDIV_RXM_MASK,
1174
+				   I2S_CLKDIV_RXM(div_bclk));
1175
+		regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
1176
+				   I2S_CKR_RSD_MASK,
1177
+				   I2S_CKR_RSD(div_lrck));
1178
+		regmap_update_bits(i2s_tdm->regmap, I2S_RXCR,
1179
+				   I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK,
1180
+				   fmt);
1181
+	}
1182
+
1183
+	/*
1184
+	 * Bring back CLK ASAP after cfg changed to make SINK devices active
1185
+	 * on HDMI-PATH-ALWAYS-ON situation, this workaround for some TVs no
1186
+	 * sound issue. at the moment, it's 8K@60Hz display situation.
1187
+	 */
1188
+	if ((i2s_tdm->quirks & QUIRK_HDMI_PATH) &&
1189
+	    (i2s_tdm->quirks & QUIRK_ALWAYS_ON) &&
1190
+	    (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)) {
1191
+		rockchip_i2s_tdm_xfer_start(i2s_tdm, SNDRV_PCM_STREAM_PLAYBACK);
1192
+	}
1047
1193
 
1048
1194
 	return 0;
1049
1195
 }
..
..
@@ -1110,29 +1256,31 @@
1110
1256
 				      struct snd_soc_dai *dai)
1111
1257
 {
1112
1258
 	struct rk_i2s_tdm_dev *i2s_tdm = to_info(dai);
1259
+	struct snd_dmaengine_dai_dma_data *dma_data;
1113
1260
 	struct clk *mclk;
1114
1261
 	int ret = 0;
1115
1262
 	unsigned int val = 0;
1116
1263
 	unsigned int mclk_rate, bclk_rate, div_bclk = 4, div_lrck = 64;
1117
1264
 
1118
-	if (i2s_tdm->is_master_mode) {
1119
-		if (i2s_tdm->mclk_calibrate)
1120
-			rockchip_i2s_tdm_calibrate_mclk(i2s_tdm, substream,
1121
-							params_rate(params));
1265
+	dma_data = snd_soc_dai_get_dma_data(dai, substream);
1266
+	dma_data->maxburst = MAXBURST_PER_FIFO * params_channels(params) / 2;
1122
1267
 
1123
-		ret = rockchip_i2s_tdm_set_mclk(i2s_tdm, substream, &mclk);
1124
-		if (ret)
1125
-			goto err;
1268
+	if (i2s_tdm->mclk_calibrate)
1269
+		rockchip_i2s_tdm_calibrate_mclk(i2s_tdm, substream,
1270
+						params_rate(params));
1126
1271
 
1127
-		mclk_rate = clk_get_rate(mclk);
1128
-		bclk_rate = i2s_tdm->bclk_fs * params_rate(params);
1129
-		if (!bclk_rate) {
1130
-			ret = -EINVAL;
1131
-			goto err;
1132
-		}
1133
-		div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate);
1134
-		div_lrck = bclk_rate / params_rate(params);
1272
+	ret = rockchip_i2s_tdm_set_mclk(i2s_tdm, substream, &mclk);
1273
+	if (ret)
1274
+		goto err;
1275
+
1276
+	mclk_rate = clk_get_rate(mclk);
1277
+	bclk_rate = i2s_tdm->bclk_fs * params_rate(params);
1278
+	if (!bclk_rate) {
1279
+		ret = -EINVAL;
1280
+		goto err;
1135
1281
 	}
1282
+	div_bclk = DIV_ROUND_CLOSEST(mclk_rate, bclk_rate);
1283
+	div_lrck = bclk_rate / params_rate(params);
1136
1284
 
1137
1285
 	switch (params_format(params)) {
1138
1286
 	case SNDRV_PCM_FORMAT_S8:
..
..
@@ -1148,6 +1296,7 @@
1148
1296
 		val |= I2S_TXCR_VDW(24);
1149
1297
 		break;
1150
1298
 	case SNDRV_PCM_FORMAT_S32_LE:
1299
+	case SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE:
1151
1300
 		val |= I2S_TXCR_VDW(32);
1152
1301
 		break;
1153
1302
 	default:
..
..
@@ -1160,29 +1309,13 @@
1160
1309
 		goto err;
1161
1310
 
1162
1311
 	val |= ret;
1163
-	if (i2s_tdm->clk_trcm) {
1164
-		rockchip_i2s_trcm_mode(substream, dai, div_bclk, div_lrck, val);
1165
-	} else if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1166
-		regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV,
1167
-				   I2S_CLKDIV_TXM_MASK,
1168
-				   I2S_CLKDIV_TXM(div_bclk));
1169
-		regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
1170
-				   I2S_CKR_TSD_MASK,
1171
-				   I2S_CKR_TSD(div_lrck));
1172
-		regmap_update_bits(i2s_tdm->regmap, I2S_TXCR,
1173
-				   I2S_TXCR_VDW_MASK | I2S_TXCR_CSR_MASK,
1174
-				   val);
1175
-	} else {
1176
-		regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV,
1177
-				   I2S_CLKDIV_RXM_MASK,
1178
-				   I2S_CLKDIV_RXM(div_bclk));
1179
-		regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
1180
-				   I2S_CKR_RSD_MASK,
1181
-				   I2S_CKR_RSD(div_lrck));
1182
-		regmap_update_bits(i2s_tdm->regmap, I2S_RXCR,
1183
-				   I2S_RXCR_VDW_MASK | I2S_RXCR_CSR_MASK,
1184
-				   val);
1185
-	}
1312
+	if (!is_params_dirty(substream, dai, div_bclk, div_lrck, val))
1313
+		return 0;
1314
+
1315
+	if (i2s_tdm->clk_trcm)
1316
+		rockchip_i2s_tdm_params_trcm(substream, dai, div_bclk, div_lrck, val);
1317
+	else
1318
+		rockchip_i2s_tdm_params(substream, dai, div_bclk, div_lrck, val);
1186
1319
 
1187
1320
 	ret = rockchip_i2s_io_multiplex(substream, dai);
1188
1321
 
..
..
@@ -1200,22 +1333,12 @@
1200
1333
 	case SNDRV_PCM_TRIGGER_START:
1201
1334
 	case SNDRV_PCM_TRIGGER_RESUME:
1202
1335
 	case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1203
-		if (i2s_tdm->clk_trcm)
1204
-			rockchip_snd_txrxctrl(substream, dai, 1);
1205
-		else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1206
-			rockchip_snd_rxctrl(i2s_tdm, 1);
1207
-		else
1208
-			rockchip_snd_txctrl(i2s_tdm, 1);
1336
+		rockchip_i2s_tdm_start(i2s_tdm, substream->stream);
1209
1337
 		break;
1210
1338
 	case SNDRV_PCM_TRIGGER_SUSPEND:
1211
1339
 	case SNDRV_PCM_TRIGGER_STOP:
1212
1340
 	case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1213
-		if (i2s_tdm->clk_trcm)
1214
-			rockchip_snd_txrxctrl(substream, dai, 0);
1215
-		else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
1216
-			rockchip_snd_rxctrl(i2s_tdm, 0);
1217
-		else
1218
-			rockchip_snd_txctrl(i2s_tdm, 0);
1341
+		rockchip_i2s_tdm_stop(i2s_tdm, substream->stream);
1219
1342
 		break;
1220
1343
 	default:
1221
1344
 		ret = -EINVAL;
..
..
@@ -1305,6 +1428,93 @@
1305
1428
 	.put = rockchip_i2s_tdm_clk_compensation_put,
1306
1429
 };
1307
1430
 
1431
+/* loopback mode select */
1432
+enum {
1433
+	LOOPBACK_MODE_DIS = 0,
1434
+	LOOPBACK_MODE_1,
1435
+	LOOPBACK_MODE_2,
1436
+	LOOPBACK_MODE_2_SWAP,
1437
+};
1438
+
1439
+static const char *const loopback_text[] = {
1440
+	"Disabled",
1441
+	"Mode1",
1442
+	"Mode2",
1443
+	"Mode2 Swap",
1444
+};
1445
+
1446
+static SOC_ENUM_SINGLE_EXT_DECL(loopback_mode, loopback_text);
1447
+
1448
+static int rockchip_i2s_tdm_loopback_get(struct snd_kcontrol *kcontrol,
1449
+					 struct snd_ctl_elem_value *ucontrol)
1450
+{
1451
+	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1452
+	struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_component_get_drvdata(component);
1453
+	unsigned int reg = 0, mode = 0;
1454
+
1455
+	pm_runtime_get_sync(component->dev);
1456
+	regmap_read(i2s_tdm->regmap, I2S_XFER, &reg);
1457
+	pm_runtime_put(component->dev);
1458
+
1459
+	switch (reg & I2S_XFER_LP_MODE_MASK) {
1460
+	case I2S_XFER_LP_MODE_2_SWAP:
1461
+		mode = LOOPBACK_MODE_2_SWAP;
1462
+		break;
1463
+	case I2S_XFER_LP_MODE_2:
1464
+		mode = LOOPBACK_MODE_2;
1465
+		break;
1466
+	case I2S_XFER_LP_MODE_1:
1467
+		mode = LOOPBACK_MODE_1;
1468
+		break;
1469
+	default:
1470
+		mode = LOOPBACK_MODE_DIS;
1471
+		break;
1472
+	}
1473
+
1474
+	ucontrol->value.enumerated.item[0] = mode;
1475
+
1476
+	return 0;
1477
+}
1478
+
1479
+static int rockchip_i2s_tdm_loopback_put(struct snd_kcontrol *kcontrol,
1480
+					 struct snd_ctl_elem_value *ucontrol)
1481
+{
1482
+	struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
1483
+	struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_component_get_drvdata(component);
1484
+	unsigned int val = 0, mode = ucontrol->value.enumerated.item[0];
1485
+
1486
+	if (mode < LOOPBACK_MODE_DIS ||
1487
+	    mode > LOOPBACK_MODE_2_SWAP)
1488
+		return -EINVAL;
1489
+
1490
+	switch (mode) {
1491
+	case LOOPBACK_MODE_2_SWAP:
1492
+		val = I2S_XFER_LP_MODE_2_SWAP;
1493
+		break;
1494
+	case LOOPBACK_MODE_2:
1495
+		val = I2S_XFER_LP_MODE_2;
1496
+		break;
1497
+	case LOOPBACK_MODE_1:
1498
+		val = I2S_XFER_LP_MODE_1;
1499
+		break;
1500
+	default:
1501
+		val = I2S_XFER_LP_MODE_DIS;
1502
+		break;
1503
+	}
1504
+
1505
+	pm_runtime_get_sync(component->dev);
1506
+	regmap_update_bits(i2s_tdm->regmap, I2S_XFER, I2S_XFER_LP_MODE_MASK, val);
1507
+	pm_runtime_put(component->dev);
1508
+
1509
+	return 0;
1510
+}
1511
+
1512
+static const struct snd_kcontrol_new rockchip_i2s_tdm_snd_controls[] = {
1513
+	SOC_ENUM_EXT("I2STDM Digital Loopback Mode", loopback_mode,
1514
+		     rockchip_i2s_tdm_loopback_get,
1515
+		     rockchip_i2s_tdm_loopback_put),
1516
+};
1517
+
1308
1518
 static int rockchip_i2s_tdm_dai_probe(struct snd_soc_dai *dai)
1309
1519
 {
1310
1520
 	struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
..
..
@@ -1340,7 +1550,30 @@
1340
1550
 	return 0;
1341
1551
 }
1342
1552
 
1553
+static int rockchip_i2s_tdm_startup(struct snd_pcm_substream *substream,
1554
+				    struct snd_soc_dai *dai)
1555
+{
1556
+	struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
1557
+
1558
+	if (i2s_tdm->substreams[substream->stream])
1559
+		return -EBUSY;
1560
+
1561
+	i2s_tdm->substreams[substream->stream] = substream;
1562
+
1563
+	return 0;
1564
+}
1565
+
1566
+static void rockchip_i2s_tdm_shutdown(struct snd_pcm_substream *substream,
1567
+				      struct snd_soc_dai *dai)
1568
+{
1569
+	struct rk_i2s_tdm_dev *i2s_tdm = snd_soc_dai_get_drvdata(dai);
1570
+
1571
+	i2s_tdm->substreams[substream->stream] = NULL;
1572
+}
1573
+
1343
1574
 static const struct snd_soc_dai_ops rockchip_i2s_tdm_dai_ops = {
1575
+	.startup = rockchip_i2s_tdm_startup,
1576
+	.shutdown = rockchip_i2s_tdm_shutdown,
1344
1577
 	.hw_params = rockchip_i2s_tdm_hw_params,
1345
1578
 	.set_sysclk = rockchip_i2s_tdm_set_sysclk,
1346
1579
 	.set_fmt = rockchip_i2s_tdm_set_fmt,
..
..
@@ -1350,6 +1583,8 @@
1350
1583
 
1351
1584
 static const struct snd_soc_component_driver rockchip_i2s_tdm_component = {
1352
1585
 	.name = DRV_NAME,
1586
+	.controls = rockchip_i2s_tdm_snd_controls,
1587
+	.num_controls = ARRAY_SIZE(rockchip_i2s_tdm_snd_controls),
1353
1588
 };
1354
1589
 
1355
1590
 static bool rockchip_i2s_tdm_wr_reg(struct device *dev, unsigned int reg)
..
..
@@ -1400,6 +1635,7 @@
1400
1635
 {
1401
1636
 	switch (reg) {
1402
1637
 	case I2S_TXFIFOLR:
1638
+	case I2S_INTCR:
1403
1639
 	case I2S_INTSR:
1404
1640
 	case I2S_CLR:
1405
1641
 	case I2S_TXDR:
..
..
@@ -1453,9 +1689,11 @@
1453
1689
 	u32 reg = 0, val = 0, trcm = i2s_tdm->clk_trcm;
1454
1690
 	int i;
1455
1691
 
1692
+	if (IS_ERR(i2s_tdm->grf))
1693
+		return 0;
1694
+
1456
1695
 	switch (trcm) {
1457
1696
 	case I2S_CKR_TRCM_TXONLY:
1458
-		/* fall through */
1459
1697
 	case I2S_CKR_TRCM_RXONLY:
1460
1698
 		break;
1461
1699
 	default:
..
..
@@ -1591,7 +1829,8 @@
1591
1829
 				    SNDRV_PCM_FMTBIT_S16_LE |
1592
1830
 				    SNDRV_PCM_FMTBIT_S20_3LE |
1593
1831
 				    SNDRV_PCM_FMTBIT_S24_LE |
1594
-				    SNDRV_PCM_FMTBIT_S32_LE),
1832
+				    SNDRV_PCM_FMTBIT_S32_LE |
1833
+				    SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE),
1595
1834
 		},
1596
1835
 		.capture = {
1597
1836
 			.stream_name = "Capture",
..
..
@@ -1602,7 +1841,8 @@
1602
1841
 				    SNDRV_PCM_FMTBIT_S16_LE |
1603
1842
 				    SNDRV_PCM_FMTBIT_S20_3LE |
1604
1843
 				    SNDRV_PCM_FMTBIT_S24_LE |
1605
-				    SNDRV_PCM_FMTBIT_S32_LE),
1844
+				    SNDRV_PCM_FMTBIT_S32_LE |
1845
+				    SNDRV_PCM_FMTBIT_IEC958_SUBFRAME_LE),
1606
1846
 		},
1607
1847
 		.ops = &rockchip_i2s_tdm_dai_ops,
1608
1848
 	};
..
..
@@ -1758,6 +1998,34 @@
1758
1998
 	return rockchip_i2s_tdm_path_prepare(i2s_tdm, np, 1);
1759
1999
 }
1760
2000
 
2001
+static irqreturn_t rockchip_i2s_tdm_isr(int irq, void *devid)
2002
+{
2003
+	struct rk_i2s_tdm_dev *i2s_tdm = (struct rk_i2s_tdm_dev *)devid;
2004
+	struct snd_pcm_substream *substream;
2005
+	u32 val;
2006
+
2007
+	regmap_read(i2s_tdm->regmap, I2S_INTSR, &val);
2008
+	if (val & I2S_INTSR_TXUI_ACT) {
2009
+		dev_warn_ratelimited(i2s_tdm->dev, "TX FIFO Underrun\n");
2010
+		regmap_update_bits(i2s_tdm->regmap, I2S_INTCR,
2011
+				   I2S_INTCR_TXUIC, I2S_INTCR_TXUIC);
2012
+		substream = i2s_tdm->substreams[SNDRV_PCM_STREAM_PLAYBACK];
2013
+		if (substream)
2014
+			snd_pcm_stop_xrun(substream);
2015
+	}
2016
+
2017
+	if (val & I2S_INTSR_RXOI_ACT) {
2018
+		dev_warn_ratelimited(i2s_tdm->dev, "RX FIFO Overrun\n");
2019
+		regmap_update_bits(i2s_tdm->regmap, I2S_INTCR,
2020
+				   I2S_INTCR_RXOIC, I2S_INTCR_RXOIC);
2021
+		substream = i2s_tdm->substreams[SNDRV_PCM_STREAM_CAPTURE];
2022
+		if (substream)
2023
+			snd_pcm_stop_xrun(substream);
2024
+	}
2025
+
2026
+	return IRQ_HANDLED;
2027
+}
2028
+
1761
2029
 static int rockchip_i2s_tdm_probe(struct platform_device *pdev)
1762
2030
 {
1763
2031
 	struct device_node *node = pdev->dev.of_node;
..
..
@@ -1769,8 +2037,7 @@
1769
2037
 #ifdef HAVE_SYNC_RESET
1770
2038
 	bool sync;
1771
2039
 #endif
1772
-	int ret;
1773
-	int val;
2040
+	int ret, val, i, irq;
1774
2041
 
1775
2042
 	ret = rockchip_i2s_tdm_dai_prepare(pdev, &soc_dai);
1776
2043
 	if (ret)
..
..
@@ -1788,6 +2055,10 @@
1788
2055
 
1789
2056
 	spin_lock_init(&i2s_tdm->lock);
1790
2057
 	i2s_tdm->soc_data = (const struct rk_i2s_soc_data *)of_id->data;
2058
+
2059
+	for (i = 0; i < ARRAY_SIZE(of_quirks); i++)
2060
+		if (of_property_read_bool(node, of_quirks[i].quirk))
2061
+			i2s_tdm->quirks |= of_quirks[i].id;
1791
2062
 
1792
2063
 	i2s_tdm->bclk_fs = 64;
1793
2064
 	if (!of_property_read_u32(node, "rockchip,bclk-fs", &val)) {
..
..
@@ -1813,8 +2084,6 @@
1813
2084
 		soc_dai->playback.channels_min = 0;
1814
2085
 
1815
2086
 	i2s_tdm->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf");
1816
-	if (IS_ERR(i2s_tdm->grf))
1817
-		return PTR_ERR(i2s_tdm->grf);
1818
2087
 
1819
2088
 #ifdef HAVE_SYNC_RESET
1820
2089
 	sync = of_device_is_compatible(node, "rockchip,px30-i2s-tdm") ||
..
..
@@ -1892,23 +2161,32 @@
1892
2161
 		i2s_tdm->mclk_root1_freq = i2s_tdm->mclk_root1_initial_freq;
1893
2162
 	}
1894
2163
 
1895
-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1896
-	regs = devm_ioremap_resource(&pdev->dev, res);
2164
+	regs = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1897
2165
 	if (IS_ERR(regs))
1898
2166
 		return PTR_ERR(regs);
1899
2167
 
1900
2168
 	i2s_tdm->regmap = devm_regmap_init_mmio(&pdev->dev, regs,
1901
-					    &rockchip_i2s_tdm_regmap_config);
2169
+						&rockchip_i2s_tdm_regmap_config);
1902
2170
 	if (IS_ERR(i2s_tdm->regmap))
1903
2171
 		return PTR_ERR(i2s_tdm->regmap);
1904
2172
 
2173
+	irq = platform_get_irq(pdev, 0);
2174
+	if (irq > 0) {
2175
+		ret = devm_request_irq(&pdev->dev, irq, rockchip_i2s_tdm_isr,
2176
+				       IRQF_SHARED, node->name, i2s_tdm);
2177
+		if (ret) {
2178
+			dev_err(&pdev->dev, "failed to request irq %u\n", irq);
2179
+			return ret;
2180
+		}
2181
+	}
2182
+
1905
2183
 	i2s_tdm->playback_dma_data.addr = res->start + I2S_TXDR;
1906
2184
 	i2s_tdm->playback_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1907
-	i2s_tdm->playback_dma_data.maxburst = 8;
2185
+	i2s_tdm->playback_dma_data.maxburst = MAXBURST_PER_FIFO;
1908
2186
 
1909
2187
 	i2s_tdm->capture_dma_data.addr = res->start + I2S_RXDR;
1910
2188
 	i2s_tdm->capture_dma_data.addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1911
-	i2s_tdm->capture_dma_data.maxburst = 8;
2189
+	i2s_tdm->capture_dma_data.maxburst = MAXBURST_PER_FIFO;
1912
2190
 
1913
2191
 	ret = rockchip_i2s_tdm_tx_path_prepare(i2s_tdm, node);
1914
2192
 	if (ret < 0) {
..
..
@@ -1932,6 +2210,36 @@
1932
2210
 			goto err_pm_disable;
1933
2211
 	}
1934
2212
 
2213
+	if (i2s_tdm->quirks & QUIRK_ALWAYS_ON) {
2214
+		unsigned int rate = DEFAULT_FS * DEFAULT_MCLK_FS;
2215
+		unsigned int div_bclk = DEFAULT_FS * DEFAULT_MCLK_FS;
2216
+		unsigned int div_lrck = i2s_tdm->bclk_fs;
2217
+
2218
+		div_bclk = DIV_ROUND_CLOSEST(rate, div_lrck * DEFAULT_FS);
2219
+
2220
+		/* assign generic freq */
2221
+		clk_set_rate(i2s_tdm->mclk_rx, rate);
2222
+		clk_set_rate(i2s_tdm->mclk_tx, rate);
2223
+
2224
+		ret = rockchip_i2s_tdm_mclk_reparent(i2s_tdm);
2225
+		if (ret)
2226
+			goto err_pm_disable;
2227
+
2228
+		regmap_update_bits(i2s_tdm->regmap, I2S_CLKDIV,
2229
+				   I2S_CLKDIV_RXM_MASK | I2S_CLKDIV_TXM_MASK,
2230
+				   I2S_CLKDIV_RXM(div_bclk) | I2S_CLKDIV_TXM(div_bclk));
2231
+		regmap_update_bits(i2s_tdm->regmap, I2S_CKR,
2232
+				   I2S_CKR_RSD_MASK | I2S_CKR_TSD_MASK,
2233
+				   I2S_CKR_RSD(div_lrck) | I2S_CKR_TSD(div_lrck));
2234
+
2235
+		if (i2s_tdm->clk_trcm)
2236
+			rockchip_i2s_tdm_xfer_trcm_start(i2s_tdm);
2237
+		else
2238
+			rockchip_i2s_tdm_xfer_start(i2s_tdm, SNDRV_PCM_STREAM_PLAYBACK);
2239
+
2240
+		pm_runtime_forbid(&pdev->dev);
2241
+	}
2242
+
1935
2243
 	regmap_update_bits(i2s_tdm->regmap, I2S_DMACR, I2S_DMACR_TDL_MASK,
1936
2244
 			   I2S_DMACR_TDL(16));
1937
2245
 	regmap_update_bits(i2s_tdm->regmap, I2S_DMACR, I2S_DMACR_RDL_MASK,
..
..
@@ -1951,8 +2259,11 @@
1951
2259
 		goto err_suspend;
1952
2260
 	}
1953
2261
 
1954
-	if (of_property_read_bool(node, "rockchip,no-dmaengine"))
1955
-		return ret;
2262
+	if (of_property_read_bool(node, "rockchip,no-dmaengine")) {
2263
+		dev_info(&pdev->dev, "Used for Multi-DAI\n");
2264
+		return 0;
2265
+	}
2266
+
1956
2267
 	ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
1957
2268
 	if (ret) {
1958
2269
 		dev_err(&pdev->dev, "Could not register PCM\n");
..
..
@@ -1978,14 +2289,21 @@
1978
2289
 	if (!pm_runtime_status_suspended(&pdev->dev))
1979
2290
 		i2s_tdm_runtime_suspend(&pdev->dev);
1980
2291
 
1981
-	if (!IS_ERR(i2s_tdm->mclk_tx))
1982
-		clk_prepare_enable(i2s_tdm->mclk_tx);
1983
-	if (!IS_ERR(i2s_tdm->mclk_rx))
1984
-		clk_prepare_enable(i2s_tdm->mclk_rx);
1985
-	if (!IS_ERR(i2s_tdm->hclk))
1986
-		clk_disable_unprepare(i2s_tdm->hclk);
2292
+	clk_disable_unprepare(i2s_tdm->mclk_tx);
2293
+	clk_disable_unprepare(i2s_tdm->mclk_rx);
2294
+	clk_disable_unprepare(i2s_tdm->hclk);
1987
2295
 
1988
2296
 	return 0;
2297
+}
2298
+
2299
+static void rockchip_i2s_tdm_platform_shutdown(struct platform_device *pdev)
2300
+{
2301
+	struct rk_i2s_tdm_dev *i2s_tdm = dev_get_drvdata(&pdev->dev);
2302
+
2303
+	pm_runtime_get_sync(i2s_tdm->dev);
2304
+	rockchip_i2s_tdm_stop(i2s_tdm, SNDRV_PCM_STREAM_PLAYBACK);
2305
+	rockchip_i2s_tdm_stop(i2s_tdm, SNDRV_PCM_STREAM_CAPTURE);
2306
+	pm_runtime_put(i2s_tdm->dev);
1989
2307
 }
1990
2308
 
1991
2309
 #ifdef CONFIG_PM_SLEEP
..
..
@@ -2023,6 +2341,7 @@
2023
2341
 static struct platform_driver rockchip_i2s_tdm_driver = {
2024
2342
 	.probe = rockchip_i2s_tdm_probe,
2025
2343
 	.remove = rockchip_i2s_tdm_remove,
2344
+	.shutdown = rockchip_i2s_tdm_platform_shutdown,
2026
2345
 	.driver = {
2027
2346
 		.name = DRV_NAME,
2028
2347
 		.of_match_table = of_match_ptr(rockchip_i2s_tdm_match),