rk3568 rt init

hc

2023-11-06 e3e12f52b214121840b44c91de5b3e5af5d3eb84

 kernel/drivers/video/rockchip/mpp/mpp_vdpu1.c
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@@ -20,6 +20,8 @@
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 #include <linux/uaccess.h>
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 #include <linux/regmap.h>
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 #include <linux/proc_fs.h>
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+#include <linux/mfd/syscon.h>
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+#include <linux/rockchip/cpu.h>
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 #include <soc/rockchip/pm_domains.h>
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26
 
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 #include "mpp_debug.h"
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@@ -57,6 +59,9 @@
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 /* NOTE: Don't enable it or decoding AVC would meet problem at rk3288 */
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 #define VDPU1_REG_DEC_EN		0x008
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 #define	VDPU1_CLOCK_GATE_EN		BIT(10)
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+
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+#define VDPU1_REG_SOFT_RESET		0x194
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+#define VDPU1_REG_SOFT_RESET_INDEX	(101)
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65
 
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 #define VDPU1_REG_SYS_CTRL		0x00c
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 #define VDPU1_REG_SYS_CTRL_INDEX	(3)
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@@ -387,6 +392,7 @@
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 	u32 i;
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 	u32 reg_en;
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 	struct vdpu_task *task = to_vdpu_task(mpp_task);
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+	u32 timing_en = mpp->srv->timing_en;
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396
 
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 	mpp_debug_enter();
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@@ -401,12 +407,21 @@
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 		mpp_write_req(mpp, task->reg, s, e, reg_en);
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 	}
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+
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+	/* flush tlb before starting hardware */
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+	mpp_iommu_flush_tlb(mpp->iommu_info);
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+
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 	/* init current task */
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 	mpp->cur_task = mpp_task;
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+
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+	mpp_task_run_begin(mpp_task, timing_en, MPP_WORK_TIMEOUT_DELAY);
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+
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 	/* Flush the register before the start the device */
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 	wmb();
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 	mpp_write(mpp, VDPU1_REG_DEC_INT_EN,
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 		  task->reg[reg_en] | VDPU1_DEC_START);
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+
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+	mpp_task_run_end(mpp_task, timing_en);
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 	mpp_debug_leave();
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@@ -503,6 +518,10 @@
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 		dec->procfs = NULL;
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 		return -EIO;
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 	}
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+
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+	/* for common mpp_dev options */
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+	mpp_procfs_create_common(dec->procfs, mpp);
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+
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 	mpp_procfs_create_u32("aclk", 0644,
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 			      dec->procfs, &dec->aclk_info.debug_rate_hz);
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 	mpp_procfs_create_u32("session_buffers", 0644,
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@@ -663,21 +682,35 @@
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 	return IRQ_HANDLED;
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 }
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684
 
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+static int vdpu_soft_reset(struct mpp_dev *mpp)
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+{
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+	u32 val;
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+
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+	mpp_write(mpp, VDPU1_REG_SOFT_RESET, 1);
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+	udelay(2);
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+	val = mpp_read(mpp, VDPU1_REG_SOFT_RESET);
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+
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+	return val;
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+}
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+
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 static int vdpu_reset(struct mpp_dev *mpp)
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 {
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 	struct vdpu_dev *dec = to_vdpu_dev(mpp);
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+	u32 ret = 0;
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-	if (dec->rst_a && dec->rst_h) {
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+	/* soft reset first */
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+	ret = vdpu_soft_reset(mpp);
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+	if (ret && dec->rst_a && dec->rst_h) {
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 		mpp_debug(DEBUG_RESET, "reset in\n");
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705
 
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 		/* Don't skip this or iommu won't work after reset */
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-		rockchip_pmu_idle_request(mpp->dev, true);
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+		mpp_pmu_idle_request(mpp, true);
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 		mpp_safe_reset(dec->rst_a);
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 		mpp_safe_reset(dec->rst_h);
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 		udelay(5);
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 		mpp_safe_unreset(dec->rst_a);
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 		mpp_safe_unreset(dec->rst_h);
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-		rockchip_pmu_idle_request(mpp->dev, false);
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+		mpp_pmu_idle_request(mpp, false);
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 		mpp_debug(DEBUG_RESET, "reset out\n");
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 	}
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@@ -774,12 +807,10 @@
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 		.data = &vdpu_3368_data,
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 	},
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 #endif
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-#ifdef CONFIG_CPU_RK3328
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 	{
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 		.compatible = "rockchip,avs-plus-decoder",
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 		.data = &avsd_plus_data,
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 	},
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-#endif
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 	{},
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 };
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@@ -864,12 +895,53 @@
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 		dev_err(dev, "wait total running time out\n");
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 }
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+static int vdpu_runtime_suspend(struct device *dev)
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+{
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+	struct mpp_dev *mpp = dev_get_drvdata(dev);
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+	struct mpp_grf_info *info = mpp->grf_info;
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+	struct mpp_taskqueue *queue = mpp->queue;
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+
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+	if (cpu_is_rk3528() && info && info->mem_offset) {
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+		mutex_lock(&queue->ref_lock);
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+		if (!atomic_dec_if_positive(&queue->runtime_cnt)) {
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+			regmap_write(info->grf, info->mem_offset,
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+				     info->val_mem_off);
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+		}
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+		mutex_unlock(&queue->ref_lock);
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+	}
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+
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+	return 0;
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+}
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+
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+static int vdpu_runtime_resume(struct device *dev)
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+{
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+	struct mpp_dev *mpp = dev_get_drvdata(dev);
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+	struct mpp_grf_info *info = mpp->grf_info;
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+	struct mpp_taskqueue *queue = mpp->queue;
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+
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+	if (cpu_is_rk3528() && info && info->mem_offset) {
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+		mutex_lock(&queue->ref_lock);
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+		regmap_write(info->grf, info->mem_offset,
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+			     info->val_mem_on);
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+		atomic_inc(&queue->runtime_cnt);
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+		mutex_unlock(&queue->ref_lock);
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+	}
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+
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+	return 0;
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+}
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+
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+static const struct dev_pm_ops vdpu_pm_ops = {
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+	.runtime_suspend		= vdpu_runtime_suspend,
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+	.runtime_resume			= vdpu_runtime_resume,
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+};
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+
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 struct platform_driver rockchip_vdpu1_driver = {
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 	.probe = vdpu_probe,
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 	.remove = vdpu_remove,
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 	.shutdown = vdpu_shutdown,
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 	.driver = {
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 		.name = VDPU1_DRIVER_NAME,
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+		.pm = &vdpu_pm_ops,
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 		.of_match_table = of_match_ptr(mpp_vdpu1_dt_match),
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 	},
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 };