rk3568 rt init

hc

2023-11-06 e3e12f52b214121840b44c91de5b3e5af5d3eb84

 kernel/drivers/video/rockchip/mpp/mpp_vdpp.c
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@@ -18,6 +18,8 @@
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 #include <linux/uaccess.h>
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 #include <linux/regmap.h>
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 #include <linux/proc_fs.h>
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+#include <linux/mfd/syscon.h>
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+#include <linux/rockchip/cpu.h>
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 #include <soc/rockchip/pm_domains.h>
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24
 
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 #include "mpp_debug.h"
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@@ -27,6 +29,8 @@
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 #define VDPP_DRIVER_NAME		"mpp_vdpp"
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30
 
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 #define	VDPP_SESSION_MAX_BUFFERS	15
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+#define VDPP_REG_WORK_MODE			0x0008
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+#define VDPP_REG_VDPP_MODE			BIT(1)
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34
 
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 #define to_vdpp_info(info)	\
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 		container_of(info, struct vdpp_hw_info, hw)
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@@ -87,6 +91,7 @@
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 	struct reset_control *rst_s;
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 	/* for zme */
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 	void __iomem *zme_base;
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+	struct regmap *grf;
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 };
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 static struct vdpp_hw_info vdpp_v1_hw_info = {
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@@ -332,6 +337,9 @@
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 		}
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 	}
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339
 
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+	/* flush tlb before starting hardware */
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+	mpp_iommu_flush_tlb(mpp->iommu_info);
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+
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 	/* init current task */
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 	mpp->cur_task = mpp_task;
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 	/* Flush the register before the start the device */
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@@ -474,6 +482,8 @@
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 	int ret;
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 	struct vdpp_dev *vdpp = to_vdpp_dev(mpp);
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484
 
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+	mpp->grf_info = &mpp->srv->grf_infos[MPP_DRIVER_VDPP];
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+
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 	/* Get clock info from dtsi */
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 	ret = mpp_get_clk_info(mpp, &vdpp->aclk_info, "aclk");
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 	if (ret)
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@@ -546,12 +556,18 @@
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 {
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 	struct vdpp_dev *vdpp = to_vdpp_dev(mpp);
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 	struct vdpp_hw_info *hw_info = vdpp->hw_info;
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+	u32 work_mode = mpp_read(mpp, VDPP_REG_WORK_MODE);
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+	if (!(work_mode & VDPP_REG_VDPP_MODE))
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+		return IRQ_NONE;
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 	mpp->irq_status = mpp_read(mpp, hw_info->int_sta_base);
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 	if (!(mpp->irq_status & hw_info->int_mask))
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 		return IRQ_NONE;
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 	mpp_write(mpp, hw_info->int_en_base, 0);
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 	mpp_write(mpp, hw_info->int_clr_base, mpp->irq_status);
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+
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+	/* ensure hardware is being off status */
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+	mpp_write(mpp, hw_info->start_base, 0);
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 	return IRQ_WAKE_THREAD;
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 }
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@@ -590,7 +606,7 @@
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 		mpp_debug(DEBUG_RESET, "reset in\n");
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607
 
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 		/* Don't skip this or iommu won't work after reset */
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-		rockchip_pmu_idle_request(mpp->dev, true);
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+		mpp_pmu_idle_request(mpp, true);
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 		mpp_safe_reset(vdpp->rst_a);
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 		mpp_safe_reset(vdpp->rst_h);
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 		mpp_safe_reset(vdpp->rst_s);
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@@ -598,7 +614,7 @@
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 		mpp_safe_unreset(vdpp->rst_a);
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 		mpp_safe_unreset(vdpp->rst_h);
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 		mpp_safe_unreset(vdpp->rst_s);
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-		rockchip_pmu_idle_request(mpp->dev, false);
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+		mpp_pmu_idle_request(mpp, false);
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 		mpp_debug(DEBUG_RESET, "reset out\n");
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 	}
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@@ -617,14 +633,18 @@
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 	mpp_write(mpp, hw_info->cfg_base, hw_info->bit_rst_en);
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 	ret = readl_relaxed_poll_timeout(mpp->reg_base + hw_info->rst_sta_base,
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 					 rst_status,
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-					 !(rst_status & hw_info->bit_rst_done),
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-					 0, 2);
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+					 rst_status & hw_info->bit_rst_done,
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+					 0, 5);
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 	if (ret) {
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 		mpp_err("soft reset timeout, use cru reset\n");
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 		return _vdpp_reset(mpp, vdpp);
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 	}
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 	mpp_write(mpp, hw_info->rst_sta_base, 0);
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+
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+	/* ensure hardware is being off status */
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+	mpp_write(mpp, hw_info->start_base, 0);
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+
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 	return 0;
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 }
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@@ -710,6 +730,7 @@
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 		dev_err(dev, "register interrupter runtime failed\n");
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 		return -EINVAL;
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 	}
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+
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 	mpp->session_max_buffers = VDPP_SESSION_MAX_BUFFERS;
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 	vdpp->hw_info = to_vdpp_info(mpp->var->hw_info);
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 	vdpp_procfs_init(mpp);
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@@ -751,12 +772,53 @@
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 		dev_err(dev, "wait total running time out\n");
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 }
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+static int vdpp_runtime_suspend(struct device *dev)
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+{
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+	struct mpp_dev *mpp = dev_get_drvdata(dev);
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+	struct mpp_grf_info *info = mpp->grf_info;
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+	struct mpp_taskqueue *queue = mpp->queue;
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+
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+	if (cpu_is_rk3528() && info && info->mem_offset) {
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+		mutex_lock(&queue->ref_lock);
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+		if (!atomic_dec_if_positive(&queue->runtime_cnt)) {
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+			regmap_write(info->grf, info->mem_offset,
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+				     info->val_mem_off);
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+		}
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+		mutex_unlock(&queue->ref_lock);
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+	}
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+
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+	return 0;
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+}
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+
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+static int vdpp_runtime_resume(struct device *dev)
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+{
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+	struct mpp_dev *mpp = dev_get_drvdata(dev);
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+	struct mpp_grf_info *info = mpp->grf_info;
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+	struct mpp_taskqueue *queue = mpp->queue;
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+
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+	if (cpu_is_rk3528() && info && info->mem_offset) {
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+		mutex_lock(&queue->ref_lock);
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+		regmap_write(info->grf, info->mem_offset,
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+			     info->val_mem_on);
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+		atomic_inc(&queue->runtime_cnt);
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+		mutex_unlock(&queue->ref_lock);
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+	}
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+
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+	return 0;
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+}
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+
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+static const struct dev_pm_ops vdpp_pm_ops = {
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+	.runtime_suspend		= vdpp_runtime_suspend,
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+	.runtime_resume			= vdpp_runtime_resume,
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+};
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+
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 struct platform_driver rockchip_vdpp_driver = {
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 	.probe = vdpp_probe,
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 	.remove = vdpp_remove,
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 	.shutdown = vdpp_shutdown,
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 	.driver = {
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 		.name = VDPP_DRIVER_NAME,
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+		.pm = &vdpp_pm_ops,
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 		.of_match_table = of_match_ptr(mpp_vdpp_dt_match),
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 	},
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 };