rk3568 rt init

hc

2023-11-06 e3e12f52b214121840b44c91de5b3e5af5d3eb84

 kernel/drivers/video/rockchip/mpp/mpp_rkvenc2.c
..
..
@@ -28,6 +28,8 @@
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 #include <linux/nospec.h>
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 #include <linux/workqueue.h>
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 #include <linux/dma-iommu.h>
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+#include <linux/mfd/syscon.h>
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+#include <linux/rockchip/cpu.h>
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 #include <soc/rockchip/pm_domains.h>
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 #include <soc/rockchip/rockchip_ipa.h>
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 #include <soc/rockchip/rockchip_opp_select.h>
..
..
@@ -41,6 +43,7 @@
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43
 
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 #define	RKVENC_SESSION_MAX_BUFFERS		40
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 #define RKVENC_MAX_CORE_NUM			4
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+#define RKVENC_SCLR_DONE_STA			BIT(2)
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47
 
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 #define to_rkvenc_info(info)		\
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 		container_of(info, struct rkvenc_hw_info, hw)
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@@ -187,6 +190,7 @@
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 	dma_addr_t sram_iova;
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 	u32 sram_enabled;
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 	struct page *rcb_page;
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+	struct regmap *grf;
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 };
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..
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@@ -699,6 +703,7 @@
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 	struct rkvenc_dev *enc = to_rkvenc_dev(mpp);
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 	struct rkvenc_task *task = to_rkvenc_task(mpp_task);
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 	struct rkvenc_hw_info *hw = enc->hw_info;
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+	u32 timing_en = mpp->srv->timing_en;
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707
 
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 	mpp_debug_enter();
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709
 
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@@ -735,11 +740,20 @@
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 		}
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 	}
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742
 
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+	/* flush tlb before starting hardware */
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+	mpp_iommu_flush_tlb(mpp->iommu_info);
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+
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 	/* init current task */
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 	mpp->cur_task = mpp_task;
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+
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+	mpp_task_run_begin(mpp_task, timing_en, MPP_WORK_TIMEOUT_DELAY);
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+
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 	/* Flush the register before the start the device */
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 	wmb();
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+
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 	mpp_write(mpp, enc->hw_info->enc_start_base, start_val);
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+
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+	mpp_task_run_end(mpp_task, timing_en);
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757
 
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 	mpp_debug_leave();
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..
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@@ -793,6 +807,7 @@
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 		if (mpp_debug_unlikely(DEBUG_DUMP_ERR_REG))
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 			mpp_task_dump_hw_reg(mpp, mpp_task);
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 	}
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+
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 	mpp_task_finish(mpp_task->session, mpp_task);
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812
 
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 	mpp_debug_leave();
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@@ -1031,6 +1046,10 @@
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 		enc->procfs = NULL;
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 		return -EIO;
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 	}
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+
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+	/* for common mpp_dev options */
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+	mpp_procfs_create_common(enc->procfs, mpp);
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+
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 	/* for debug */
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 	mpp_procfs_create_u32("aclk", 0644,
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 			      enc->procfs, &enc->aclk_info.debug_rate_hz);
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@@ -1063,7 +1082,7 @@
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 	struct rkvenc_dev *enc = to_rkvenc_dev(mpp);
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 	int ret = 0;
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-	mpp->grf_info = &mpp->srv->grf_infos[MPP_DRIVER_RKVENC];
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+	mpp->grf_info = &mpp->srv->grf_infos[MPP_DRIVER_RKVENC2];
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 	/* Get clock info from dtsi */
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 	ret = mpp_get_clk_info(mpp, &enc->aclk_info, "aclk_vcodec");
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@@ -1097,23 +1116,41 @@
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 	return 0;
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 }
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1100
-static int rkvenc_reset(struct mpp_dev *mpp)
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+static int rkvenc_soft_reset(struct mpp_dev *mpp)
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 {
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 	struct rkvenc_dev *enc = to_rkvenc_dev(mpp);
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 	struct rkvenc_hw_info *hw = enc->hw_info;
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-
1105
-	mpp_debug_enter();
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+	u32 rst_status = 0;
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+	int ret = 0;
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1125
 
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 	/* safe reset */
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 	mpp_write(mpp, hw->int_mask_base, 0x3FF);
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 	mpp_write(mpp, hw->enc_clr_base, 0x1);
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-	udelay(5);
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+	ret = readl_relaxed_poll_timeout(mpp->reg_base + hw->int_sta_base,
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+					 rst_status,
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+					 rst_status & RKVENC_SCLR_DONE_STA,
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+					 0, 5);
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 	mpp_write(mpp, hw->int_clr_base, 0xffffffff);
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 	mpp_write(mpp, hw->int_sta_base, 0);
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+	return ret;
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+
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+}
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+
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+static int rkvenc_reset(struct mpp_dev *mpp)
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+{
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+	struct rkvenc_dev *enc = to_rkvenc_dev(mpp);
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+	int ret = 0;
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+
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+	mpp_debug_enter();
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+
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+	/* safe reset first*/
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+	ret = rkvenc_soft_reset(mpp);
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+
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 	/* cru reset */
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-	if (enc->rst_a && enc->rst_h && enc->rst_core) {
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-		rockchip_pmu_idle_request(mpp->dev, true);
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+	if (ret && enc->rst_a && enc->rst_h && enc->rst_core) {
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+		mpp_err("soft reset timeout, use cru reset\n");
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+		mpp_pmu_idle_request(mpp, true);
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 		mpp_safe_reset(enc->rst_a);
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 		mpp_safe_reset(enc->rst_h);
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 		mpp_safe_reset(enc->rst_core);
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@@ -1121,7 +1158,7 @@
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 		mpp_safe_unreset(enc->rst_a);
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 		mpp_safe_unreset(enc->rst_h);
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 		mpp_safe_unreset(enc->rst_core);
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-		rockchip_pmu_idle_request(mpp->dev, false);
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+		mpp_pmu_idle_request(mpp, false);
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 	}
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 	mpp_debug_leave();
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@@ -1338,6 +1375,7 @@
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 	}
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 	mpp->session_max_buffers = RKVENC_SESSION_MAX_BUFFERS;
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 	enc->hw_info = to_rkvenc_info(mpp->var->hw_info);
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+
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 	rkvenc_procfs_init(mpp);
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 	mpp_dev_register_srv(mpp, mpp->srv);
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@@ -1416,12 +1454,44 @@
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 	dev_info(dev, "shutdown success\n");
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 }
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+static int rkvenc_runtime_suspend(struct device *dev)
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+{
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+	struct mpp_dev *mpp = dev_get_drvdata(dev);
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+	struct mpp_grf_info *info = mpp->grf_info;
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+
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+	if (cpu_is_rk3528() && info && info->mem_offset)
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+		regmap_write(info->grf,
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+			     info->mem_offset,
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+			     info->val_mem_off);
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+
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+	return 0;
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+}
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+
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+static int rkvenc_runtime_resume(struct device *dev)
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+{
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+	struct mpp_dev *mpp = dev_get_drvdata(dev);
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+	struct mpp_grf_info *info = mpp->grf_info;
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+
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+	if (cpu_is_rk3528() && info && info->mem_offset)
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+		regmap_write(info->grf,
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+			     info->mem_offset,
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+			     info->val_mem_on);
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+
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+	return 0;
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+}
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+
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+static const struct dev_pm_ops rkvenc_pm_ops = {
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+	.runtime_suspend		= rkvenc_runtime_suspend,
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+	.runtime_resume			= rkvenc_runtime_resume,
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+};
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+
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 struct platform_driver rockchip_rkvenc2_driver = {
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 	.probe = rkvenc_probe,
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 	.remove = rkvenc_remove,
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 	.shutdown = rkvenc_shutdown,
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 	.driver = {
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 		.name = RKVENC_DRIVER_NAME,
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+		.pm = &rkvenc_pm_ops,
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 		.of_match_table = of_match_ptr(mpp_rkvenc_dt_match),
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 	},
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 };