rk3568 rt init

hc

2023-11-06 e3e12f52b214121840b44c91de5b3e5af5d3eb84

 kernel/drivers/soc/rockchip/pm_domains.c
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@@ -37,6 +37,7 @@
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 #include <dt-bindings/power/rk3366-power.h>
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 #include <dt-bindings/power/rk3368-power.h>
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 #include <dt-bindings/power/rk3399-power.h>
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+#include <dt-bindings/power/rk3528-power.h>
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 #include <dt-bindings/power/rk3568-power.h>
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 struct rockchip_domain_info {
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@@ -146,6 +147,20 @@
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 	.keepon_startup = keepon,			\
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 }
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+#define DOMAIN_M_A(pwr, status, req, idle, ack, always, wakeup, keepon)	\
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+{							\
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+	.pwr_w_mask = (pwr) << 16,			\
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+	.pwr_mask = (pwr),				\
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+	.status_mask = (status),			\
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+	.req_w_mask = (req) << 16,			\
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+	.req_mask = (req),				\
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+	.idle_mask = (idle),				\
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+	.ack_mask = (ack),				\
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+	.always_on = always,				\
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+	.active_wakeup = wakeup,			\
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+	.keepon_startup = keepon,			\
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+}
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+
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 #define DOMAIN_M_O(pwr, status, p_offset, req, idle, ack, r_offset, wakeup, keepon)	\
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 {							\
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 	.pwr_w_mask = (pwr) << 16,			\
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@@ -205,6 +220,9 @@
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 #define DOMAIN_RK3399_PROTECT(pwr, status, req, wakeup)	\
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 	DOMAIN(pwr, status, req, req, req, wakeup, true)
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+
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+#define DOMAIN_RK3528(pwr, req, always, wakeup) \
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+	DOMAIN_M_A(pwr, pwr, req, req, req, always, wakeup, false)
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 #define DOMAIN_RK3568(pwr, req, wakeup)		\
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 	DOMAIN_M(pwr, pwr, req, req, req, wakeup, false)
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@@ -1357,6 +1375,18 @@
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 	[RK3399_PD_SDIOAUDIO]	= DOMAIN_RK3399(BIT(31), BIT(31), BIT(29), true),
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 };
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+static const struct rockchip_domain_info rk3528_pm_domains[] = {
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+	[RK3528_PD_PMU]		= DOMAIN_RK3528(0, BIT(0), true, false),
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+	[RK3528_PD_BUS]		= DOMAIN_RK3528(0, BIT(1), true, false),
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+	[RK3528_PD_DDR]		= DOMAIN_RK3528(0, BIT(2), true, false),
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+	[RK3528_PD_MSCH]	= DOMAIN_RK3528(0, BIT(3), true, false),
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+	[RK3528_PD_GPU]		= DOMAIN_RK3528(BIT(0), BIT(4), true, false),
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+	[RK3528_PD_RKVDEC]	= DOMAIN_RK3528(0, BIT(5), true, false),
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+	[RK3528_PD_RKVENC]	= DOMAIN_RK3528(0, BIT(6), true, false),
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+	[RK3528_PD_VO]		= DOMAIN_RK3528(0,  BIT(7), true, false),
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+	[RK3528_PD_VPU]		= DOMAIN_RK3528(0, BIT(8), true, false),
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+};
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+
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 static const struct rockchip_domain_info rk3568_pm_domains[] = {
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 	[RK3568_PD_NPU]		= DOMAIN_RK3568(BIT(1), BIT(2), false),
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 	[RK3568_PD_GPU]		= DOMAIN_RK3568(BIT(0), BIT(1), false),
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@@ -1508,6 +1538,17 @@
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 	.domain_info = rk3399_pm_domains,
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 };
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+static const struct rockchip_pmu_info rk3528_pmu = {
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+	.pwr_offset = 0x1210,
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+	.status_offset = 0x1230,
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+	.req_offset = 0x1110,
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+	.idle_offset = 0x1128,
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+	.ack_offset = 0x1120,
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+
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+	.num_domains = ARRAY_SIZE(rk3528_pm_domains),
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+	.domain_info = rk3528_pm_domains,
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+};
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+
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 static const struct rockchip_pmu_info rk3568_pmu = {
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 	.pwr_offset = 0xa0,
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 	.status_offset = 0x98,
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@@ -1586,6 +1627,12 @@
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 		.data = (void *)&rk3399_pmu,
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 	},
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 #endif
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+#ifdef CONFIG_CPU_RK3528
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+	{
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+		.compatible = "rockchip,rk3528-power-controller",
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+		.data = (void *)&rk3528_pmu,
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+	},
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+#endif
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 #ifdef CONFIG_CPU_RK3568
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 	{
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 		.compatible = "rockchip,rk3568-power-controller",