rk3568 rt init

hc

2023-11-06 e3e12f52b214121840b44c91de5b3e5af5d3eb84

 kernel/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
..
..
@@ -23,7 +23,7 @@
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 struct rockchip_combphy_priv;
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24
 
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 struct combphy_reg {
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-	u16 offset;
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+	u32 offset;
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 	u16 bitend;
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 	u16 bitstart;
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 	u16 disable;
..
..
@@ -38,6 +38,7 @@
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 	struct combphy_reg pipe_rxterm_set;
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 	struct combphy_reg pipe_txelec_set;
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 	struct combphy_reg pipe_txcomp_set;
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+	struct combphy_reg pipe_clk_24m;
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 	struct combphy_reg pipe_clk_25m;
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 	struct combphy_reg pipe_clk_100m;
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 	struct combphy_reg pipe_phymode_sel;
..
..
@@ -152,7 +153,18 @@
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153
 
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 static int rockchip_combphy_usb3_init(struct rockchip_combphy_priv *priv)
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 {
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+	const struct rockchip_combphy_cfg *phy_cfg = priv->cfg;
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 	int ret = 0;
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+
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+	if (device_property_present(priv->dev, "rockchip,dis-u3otg0-port")) {
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+		ret = param_write(priv->pipe_grf, &phy_cfg->grfcfg->u3otg0_port_en,
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+				  false);
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+		return ret;
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+	} else if (device_property_present(priv->dev, "rockchip,dis-u3otg1-port")) {
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+		ret = param_write(priv->pipe_grf, &phy_cfg->grfcfg->u3otg1_port_en,
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+				  false);
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+		return ret;
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+	}
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168
 
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 	if (priv->cfg->combphy_cfg) {
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 		ret = priv->cfg->combphy_cfg(priv);
..
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@@ -409,6 +421,175 @@
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 	return PTR_ERR_OR_ZERO(phy_provider);
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422
 }
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423
 
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+static int rk3528_combphy_cfg(struct rockchip_combphy_priv *priv)
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+{
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+	const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
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+	struct clk *refclk = NULL;
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+	unsigned long rate;
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+	int i;
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+	u32 val;
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+
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+	/* Configure PHY reference clock frequency */
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+	for (i = 0; i < priv->num_clks; i++) {
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+		if (!strncmp(priv->clks[i].id, "refclk", 6)) {
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+			refclk = priv->clks[i].clk;
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+			break;
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+		}
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+	}
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+
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+	if (!refclk) {
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+		dev_err(priv->dev, "No refclk found\n");
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+		return -EINVAL;
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+	}
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+
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+	switch (priv->mode) {
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+	case PHY_TYPE_PCIE:
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+		/* Set SSC downward spread spectrum */
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+		val = readl(priv->mmio + 0x18);
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+		val &= ~GENMASK(5, 4);
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+		val |= 0x01 << 4;
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+		writel(val, priv->mmio + 0x18);
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+
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+		param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
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+		param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
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+		param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
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+		param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
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+		break;
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+	case PHY_TYPE_USB3:
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+		/* Set SSC downward spread spectrum */
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+		val = readl(priv->mmio + 0x18);
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+		val &= ~GENMASK(5, 4);
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+		val |= 0x01 << 4;
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+		writel(val, priv->mmio + 0x18);
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+
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+		/* Enable adaptive CTLE for USB3.0 Rx */
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+		val = readl(priv->mmio + 0x200);
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+		val &= ~GENMASK(17, 17);
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+		val |= 0x01 << 17;
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+		writel(val, priv->mmio + 0x200);
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+
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+		/* Set Rx squelch input filler bandwidth */
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+		val = readl(priv->mmio + 0x20c);
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+		val &= ~GENMASK(2, 0);
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+		val |= 0x06;
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+		writel(val, priv->mmio + 0x20c);
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+
477
+		param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
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+		param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
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+		param_write(priv->phy_grf, &cfg->usb_mode_set, true);
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+		break;
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+	default:
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+		dev_err(priv->dev, "incompatible PHY type\n");
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+		return -EINVAL;
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+	}
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+
486
+	rate = clk_get_rate(refclk);
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+
488
+	switch (rate) {
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+	case 24000000:
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+		param_write(priv->phy_grf, &cfg->pipe_clk_24m, true);
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+		if (priv->mode == PHY_TYPE_USB3) {
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+			/* Set ssc_cnt[10:0]=00101111101 & 31.5KHz */
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+			val = readl(priv->mmio + 0x100);
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+			val &= ~GENMASK(10, 0);
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+			val |= 0x17d;
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+			writel(val, priv->mmio + 0x100);
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+		} else if (priv->mode == PHY_TYPE_PCIE) {
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+			/* Set ssc_cnt[10:0]=00101111101 & 31.5KHz */
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+			val = readl(priv->mmio + 0x100);
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+			val &= ~GENMASK(10, 0);
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+			val |= 0x17d;
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+			writel(val, priv->mmio + 0x100);
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+
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+			/* tx_trim[14]=1, Enable the counting clock of the rterm detect */
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+			val = readl(priv->mmio + 0x218);
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+			val |= (1 << 14);
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+			writel(val, priv->mmio + 0x218);
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+
509
+			/* PLL KVCO tuning fine */
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+			val = readl(priv->mmio + 0x18);
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+			val &= ~(0x7 << 10);
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+			val |= 0x2 << 10;
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+			writel(val, priv->mmio + 0x18);
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+
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+			/* su_trim[6:4]=111, [10:7]=1001, [2:0]=000 */
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+			val = readl(priv->mmio + 0x108);
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+			val &= ~(0x7f7);
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+			val |= 0x4f0;
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+			writel(val, priv->mmio + 0x108);
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+		}
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+		break;
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+	case 100000000:
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+		param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
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+		if (priv->mode == PHY_TYPE_PCIE) {
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+			/* Set ssc_cnt[10:0]=11000110011 & 31.5KHz */
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+			val = readl(priv->mmio + 0x100);
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+			val &= ~GENMASK(10, 0);
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+			val |= 0x633;
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+			writel(val, priv->mmio + 0x100);
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+
531
+			/* PLL KVCO tuning fine */
532
+			val = readl(priv->mmio + 0x18);
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+			val &= ~(0x7 << 10);
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+			val |= 0x2 << 10;
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+			writel(val, priv->mmio + 0x18);
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+
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+			/* su_trim[6:4]=111, [10:7]=1001, [2:0]=000, swing 650mv */
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+			val = 0x570804f0;
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+			writel(val, priv->mmio + 0x108);
540
+		}
541
+		break;
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+	default:
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+		dev_err(priv->dev, "Unsupported rate: %lu\n", rate);
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+		return -EINVAL;
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+	}
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+
547
+	if (priv->mode == PHY_TYPE_PCIE) {
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+		if (device_property_read_bool(priv->dev, "rockchip,enable-ssc")) {
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+			val = readl(priv->mmio + 0x100);
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+			val |= BIT(20);
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+			writel(val, priv->mmio + 0x100);
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+		}
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+	}
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+
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+	return 0;
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+}
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+
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+static const struct rockchip_combphy_grfcfg rk3528_combphy_grfcfgs = {
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+	/* pipe-phy-grf */
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+	.pcie_mode_set		= { 0x48000, 5, 0, 0x00, 0x11 },
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+	.usb_mode_set		= { 0x48000, 5, 0, 0x00, 0x04 },
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+	.pipe_rxterm_set	= { 0x48000, 12, 12, 0x00, 0x01 },
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+	.pipe_txelec_set	= { 0x48004, 1, 1, 0x00, 0x01 },
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+	.pipe_txcomp_set	= { 0x48004, 4, 4, 0x00, 0x01 },
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+	.pipe_clk_24m		= { 0x48004, 14, 13, 0x00, 0x00 },
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+	.pipe_clk_100m		= { 0x48004, 14, 13, 0x00, 0x02 },
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+	.pipe_rxterm_sel	= { 0x48008, 8, 8, 0x00, 0x01 },
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+	.pipe_txelec_sel	= { 0x48008, 12, 12, 0x00, 0x01 },
569
+	.pipe_txcomp_sel	= { 0x48008, 15, 15, 0x00, 0x01 },
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+	.pipe_clk_ext		= { 0x4800c, 9, 8, 0x02, 0x01 },
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+	.pipe_phy_status	= { 0x48034, 6, 6, 0x01, 0x00 },
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+	.con0_for_pcie		= { 0x48000, 15, 0, 0x00, 0x110 },
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+	.con1_for_pcie		= { 0x48004, 15, 0, 0x00, 0x00 },
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+	.con2_for_pcie		= { 0x48008, 15, 0, 0x00, 0x101 },
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+	.con3_for_pcie		= { 0x4800c, 15, 0, 0x00, 0x0200 },
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+	/* pipe-grf */
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+	.u3otg0_port_en		= { 0x40044, 15, 0, 0x0181, 0x1100 },
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+};
579
+
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+static const struct clk_bulk_data rk3528_clks[] = {
581
+	{ .id = "refclk" },
582
+	{ .id = "apbclk" },
583
+	{ .id = "pipe_clk" },
584
+};
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+
586
+static const struct rockchip_combphy_cfg rk3528_combphy_cfgs = {
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+	.num_clks	= ARRAY_SIZE(rk3528_clks),
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+	.clks		= rk3528_clks,
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+	.grfcfg		= &rk3528_combphy_grfcfgs,
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+	.combphy_cfg	= rk3528_combphy_cfg,
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+};
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+
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 static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
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594
 {
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595
 	const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
..
..
@@ -476,6 +657,9 @@
476
657
 
477
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 		/* Set PLL KVCO to min and set PLL charge pump current to max */
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 		writel(0xf0, priv->mmio + (0xa << 2));
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+
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+		/* Set Rx squelch input filler bandwidth */
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+		writel(0x0e, priv->mmio + (0x14 << 2));
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663
 
480
664
 		param_write(priv->phy_grf, &cfg->pipe_sel_usb, true);
481
665
 		param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
..
..
@@ -635,6 +819,10 @@
635
819
 
636
820
 static const struct of_device_id rockchip_combphy_of_match[] = {
637
821
 	{
822
+		.compatible = "rockchip,rk3528-naneng-combphy",
823
+		.data = &rk3528_combphy_cfgs,
824
+	},
825
+	{
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826
 		.compatible = "rockchip,rk3568-naneng-combphy",
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827
 		.data = &rk3568_combphy_cfgs,
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828
 	},