.. | .. |
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47 | 47 | #include <pcicfg.h> |
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48 | 48 | #include <dhd_pcie.h> |
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49 | 49 | #include <dhd_linux.h> |
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| 50 | +#if defined(CUSTOMER_HW_ROCKCHIP) && defined(CUSTOMER_HW_ROCKCHIP_RK3588) |
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| 51 | +#include <rk_dhd_pcie_linux.h> |
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| 52 | +#endif /* CUSTOMER_HW_ROCKCHIP && CUSTOMER_HW_ROCKCHIP_RK3588 */ |
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50 | 53 | #ifdef OEM_ANDROID |
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51 | 54 | #ifdef CONFIG_ARCH_MSM |
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52 | 55 | #if defined(CONFIG_PCI_MSM) || defined(CONFIG_ARCH_MSM8996) |
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.. | .. |
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616 | 619 | { |
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617 | 620 | uint32 rc_l1ss_cap; |
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618 | 621 | uint32 ep_l1ss_cap; |
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| 622 | + |
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| 623 | +#if defined(CUSTOMER_HW_ROCKCHIP) && defined(CUSTOMER_HW_ROCKCHIP_RK3588) |
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| 624 | + if (IS_ENABLED(CONFIG_PCIEASPM_ROCKCHIP_WIFI_EXTENSION)) { |
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| 625 | + if (rk_dhd_bus_is_rc_ep_l1ss_capable(bus)) { |
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| 626 | + DHD_ERROR(("%s L1ss is capable\n", __FUNCTION__)); |
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| 627 | + return TRUE; |
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| 628 | + } else { |
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| 629 | + DHD_ERROR(("%s L1ss is not capable\n", __FUNCTION__)); |
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| 630 | + return FALSE; |
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| 631 | + } |
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| 632 | + } |
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| 633 | +#endif /* CUSTOMER_HW_ROCKCHIP && CUSTOMER_HW_ROCKCHIP_RK3588 */ |
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619 | 634 | |
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620 | 635 | /* RC Extendend Capacility */ |
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621 | 636 | rc_l1ss_cap = dhdpcie_access_cap(bus->rc_dev, PCIE_EXTCAP_ID_L1SS, |
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.. | .. |
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1576 | 1591 | goto exit; |
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1577 | 1592 | } |
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1578 | 1593 | |
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1579 | | - printf("PCI_PROBE: bus %X, slot %X,vendor %X, device %X" |
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| 1594 | + printf("PCI_PROBE: bus 0x%X, slot 0x%X,vendor 0x%X, device 0x%X" |
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1580 | 1595 | "(good PCI location)\n", pdev->bus->number, |
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1581 | 1596 | PCI_SLOT(pdev->devfn), pdev->vendor, pdev->device); |
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1582 | 1597 | |
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