| .. | .. |
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| 139 | 139 | pr_debug("stmmac: MMC ctrl register (offset 0x%x): 0x%08x\n", |
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| 140 | 140 | MMC_CNTRL, value); |
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| 141 | 141 | } |
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| 142 | +EXPORT_SYMBOL(dwmac_mmc_ctrl); |
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| 142 | 143 | |
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| 143 | 144 | /* To mask all all interrupts.*/ |
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| 144 | 145 | void dwmac_mmc_intr_all_mask(void __iomem *mmcaddr) |
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| .. | .. |
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| 147 | 148 | writel(MMC_DEFAULT_MASK, mmcaddr + MMC_TX_INTR_MASK); |
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| 148 | 149 | writel(MMC_DEFAULT_MASK, mmcaddr + MMC_RX_IPC_INTR_MASK); |
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| 149 | 150 | } |
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| 151 | +EXPORT_SYMBOL(dwmac_mmc_intr_all_mask); |
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| 150 | 152 | |
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| 151 | 153 | /* This reads the MAC core counters (if actaully supported). |
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| 152 | 154 | * by default the MMC core is programmed to reset each |
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