rk3568 rt init

hc

2023-11-06 e3e12f52b214121840b44c91de5b3e5af5d3eb84

 kernel/drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
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@@ -119,6 +119,23 @@
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 	       ioaddr + DMA_CHAN_INTR_ENA(chan));
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 }
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+static void dwmac410_dma_init_channel(void __iomem *ioaddr,
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+				      struct stmmac_dma_cfg *dma_cfg, u32 chan)
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+{
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+	u32 value;
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+
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+	/* common channel control register config */
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+	value = readl(ioaddr + DMA_CHAN_CONTROL(chan));
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+	if (dma_cfg->pblx8)
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+		value = value | DMA_BUS_MODE_PBL;
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+
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+	writel(value, ioaddr + DMA_CHAN_CONTROL(chan));
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+
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+	/* Mask interrupts by writing to CSR7 */
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+	writel(DMA_CHAN_INTR_DEFAULT_MASK_4_10,
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+	       ioaddr + DMA_CHAN_INTR_ENA(chan));
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+}
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+
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 static void dwmac4_dma_init(void __iomem *ioaddr,
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 			    struct stmmac_dma_cfg *dma_cfg, int atds)
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 {
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@@ -197,7 +214,7 @@
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 				       u32 channel, int fifosz, u8 qmode)
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 {
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 	unsigned int rqs = fifosz / 256 - 1;
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-	u32 mtl_rx_op, mtl_rx_int;
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+	u32 mtl_rx_op;
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 	mtl_rx_op = readl(ioaddr + MTL_CHAN_RX_OP_MODE(channel));
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@@ -268,11 +285,6 @@
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 	}
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 	writel(mtl_rx_op, ioaddr + MTL_CHAN_RX_OP_MODE(channel));
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-
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-	/* Enable MTL RX overflow */
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-	mtl_rx_int = readl(ioaddr + MTL_CHAN_INT_CTRL(channel));
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-	writel(mtl_rx_int | MTL_RX_OVERFLOW_INT_EN,
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-	       ioaddr + MTL_CHAN_INT_CTRL(channel));
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 }
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 static void dwmac4_dma_tx_chan_op_mode(void __iomem *ioaddr, int mode,
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@@ -461,7 +473,7 @@
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 const struct stmmac_dma_ops dwmac410_dma_ops = {
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 	.reset = dwmac4_dma_reset,
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 	.init = dwmac4_dma_init,
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-	.init_chan = dwmac4_dma_init_channel,
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+	.init_chan = dwmac410_dma_init_channel,
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 	.init_rx_chan = dwmac4_dma_init_rx_chan,
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 	.init_tx_chan = dwmac4_dma_init_tx_chan,
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 	.axi = dwmac4_dma_axi,