rk3568 rt init

hc

2023-11-06 e3e12f52b214121840b44c91de5b3e5af5d3eb84

 kernel/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c
..
..
@@ -24,6 +24,7 @@
24
24
 #include <linux/of_net.h>
25
25
 #include <linux/gpio.h>
26
26
 #include <linux/module.h>
27
+#include <linux/nvmem-consumer.h>
27
28
 #include <linux/of_gpio.h>
28
29
 #include <linux/of_device.h>
29
30
 #include <linux/platform_device.h>
..
..
@@ -77,6 +78,7 @@
77
78
 	struct clk *pclk_mac;
78
79
 	struct clk *clk_phy;
79
80
 	struct clk *pclk_xpcs;
81
+	struct clk *clk_xpcs_eee;
80
82
 
81
83
 	struct reset_control *phy_reset;
82
84
 
..
..
@@ -85,6 +87,8 @@
85
87
 
86
88
 	struct regmap *grf;
87
89
 	struct regmap *xpcs;
90
+
91
+	unsigned char otp_data;
88
92
 };
89
93
 
90
94
 /* XPCS */
..
..
@@ -1322,6 +1326,208 @@
1322
1326
 	.set_rmii_speed = rk3399_set_rmii_speed,
1323
1327
 };
1324
1328
 
1329
+#define RK3528_VO_GRF_GMAC_CON		0X60018
1330
+#define RK3528_VPU_GRF_GMAC_CON5	0X40018
1331
+#define RK3528_VPU_GRF_GMAC_CON6	0X4001c
1332
+
1333
+#define RK3528_GMAC_RXCLK_DLY_ENABLE	GRF_BIT(15)
1334
+#define RK3528_GMAC_RXCLK_DLY_DISABLE	GRF_CLR_BIT(15)
1335
+#define RK3528_GMAC_TXCLK_DLY_ENABLE	GRF_BIT(14)
1336
+#define RK3528_GMAC_TXCLK_DLY_DISABLE	GRF_CLR_BIT(14)
1337
+
1338
+#define RK3528_GMAC_CLK_RX_DL_CFG(val)	HIWORD_UPDATE(val, 0xFF, 8)
1339
+#define RK3528_GMAC_CLK_TX_DL_CFG(val)	HIWORD_UPDATE(val, 0xFF, 0)
1340
+
1341
+#define RK3528_GMAC0_PHY_INTF_SEL_RMII	GRF_BIT(1)
1342
+#define RK3528_GMAC1_PHY_INTF_SEL_RGMII	GRF_CLR_BIT(8)
1343
+#define RK3528_GMAC1_PHY_INTF_SEL_RMII	GRF_BIT(8)
1344
+
1345
+#define RK3528_GMAC1_CLK_SELET_CRU	GRF_CLR_BIT(12)
1346
+#define RK3528_GMAC1_CLK_SELET_IO	GRF_BIT(12)
1347
+
1348
+#define RK3528_GMAC0_CLK_RMII_DIV2	GRF_BIT(3)
1349
+#define RK3528_GMAC0_CLK_RMII_DIV20	GRF_CLR_BIT(3)
1350
+#define RK3528_GMAC1_CLK_RMII_DIV2	GRF_BIT(10)
1351
+#define RK3528_GMAC1_CLK_RMII_DIV20	GRF_CLR_BIT(10)
1352
+
1353
+#define RK3528_GMAC1_CLK_RGMII_DIV1		\
1354
+			(GRF_CLR_BIT(11) | GRF_CLR_BIT(10))
1355
+#define RK3528_GMAC1_CLK_RGMII_DIV5		\
1356
+			(GRF_BIT(11) | GRF_BIT(10))
1357
+#define RK3528_GMAC1_CLK_RGMII_DIV50		\
1358
+			(GRF_BIT(11) | GRF_CLR_BIT(10))
1359
+
1360
+#define RK3528_GMAC0_CLK_RMII_GATE	GRF_BIT(2)
1361
+#define RK3528_GMAC0_CLK_RMII_NOGATE	GRF_CLR_BIT(2)
1362
+#define RK3528_GMAC1_CLK_RMII_GATE	GRF_BIT(9)
1363
+#define RK3528_GMAC1_CLK_RMII_NOGATE	GRF_CLR_BIT(9)
1364
+
1365
+#define RK3528_VO_GRF_MACPHY_CON0		0X6001c
1366
+#define RK3528_VO_GRF_MACPHY_CON1		0X60020
1367
+
1368
+#define RK3528_VO_GRF_MACPHY_SHUTDOWN		GRF_BIT(1)
1369
+#define RK3528_VO_GRF_MACPHY_POWERUP		GRF_CLR_BIT(1)
1370
+#define RK3528_VO_GRF_MACPHY_INTERNAL_RMII_SEL	GRF_BIT(6)
1371
+#define RK3528_VO_GRF_MACPHY_24M_CLK_SEL	(GRF_BIT(8) | GRF_BIT(9))
1372
+#define RK3528_VO_GRF_MACPHY_PHY_ID		GRF_BIT(11)
1373
+
1374
+#define RK3528_VO_GRF_MACPHY_BGS		HIWORD_UPDATE(0x0, 0xf, 0)
1375
+
1376
+static void rk3528_set_to_rgmii(struct rk_priv_data *bsp_priv,
1377
+				int tx_delay, int rx_delay)
1378
+{
1379
+	struct device *dev = &bsp_priv->pdev->dev;
1380
+
1381
+	if (IS_ERR(bsp_priv->grf)) {
1382
+		dev_err(dev, "Missing rockchip,grf property\n");
1383
+		return;
1384
+	}
1385
+
1386
+	regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
1387
+		     RK3528_GMAC1_PHY_INTF_SEL_RGMII);
1388
+
1389
+	regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
1390
+		     DELAY_ENABLE(RK3528, tx_delay, rx_delay));
1391
+
1392
+	regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON6,
1393
+		     DELAY_VALUE(RK3528, tx_delay, rx_delay));
1394
+}
1395
+
1396
+static void rk3528_set_to_rmii(struct rk_priv_data *bsp_priv)
1397
+{
1398
+	struct device *dev = &bsp_priv->pdev->dev;
1399
+	unsigned int id = bsp_priv->bus_id;
1400
+
1401
+	if (IS_ERR(bsp_priv->grf)) {
1402
+		dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
1403
+		return;
1404
+	}
1405
+
1406
+	if (id == 1)
1407
+		regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
1408
+			     RK3528_GMAC1_PHY_INTF_SEL_RMII);
1409
+	else
1410
+		regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON,
1411
+			     RK3528_GMAC0_PHY_INTF_SEL_RMII);
1412
+}
1413
+
1414
+static void rk3528_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
1415
+{
1416
+	struct device *dev = &bsp_priv->pdev->dev;
1417
+	unsigned int val = 0;
1418
+
1419
+	switch (speed) {
1420
+	case 10:
1421
+		val = RK3528_GMAC1_CLK_RGMII_DIV50;
1422
+		break;
1423
+	case 100:
1424
+		val = RK3528_GMAC1_CLK_RGMII_DIV5;
1425
+		break;
1426
+	case 1000:
1427
+		val = RK3528_GMAC1_CLK_RGMII_DIV1;
1428
+		break;
1429
+	default:
1430
+		goto err;
1431
+	}
1432
+
1433
+	regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, val);
1434
+	return;
1435
+err:
1436
+	dev_err(dev, "unknown RGMII speed value for GMAC speed=%d", speed);
1437
+}
1438
+
1439
+static void rk3528_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
1440
+{
1441
+	struct device *dev = &bsp_priv->pdev->dev;
1442
+	unsigned int val, offset, id = bsp_priv->bus_id;
1443
+
1444
+	switch (speed) {
1445
+	case 10:
1446
+		val = (id == 1) ? RK3528_GMAC1_CLK_RMII_DIV20 :
1447
+				  RK3528_GMAC0_CLK_RMII_DIV20;
1448
+		break;
1449
+	case 100:
1450
+		val = (id == 1) ? RK3528_GMAC1_CLK_RMII_DIV2 :
1451
+				  RK3528_GMAC0_CLK_RMII_DIV2;
1452
+		break;
1453
+	default:
1454
+		goto err;
1455
+	}
1456
+
1457
+	offset = (id == 1) ? RK3528_VPU_GRF_GMAC_CON5 : RK3528_VO_GRF_GMAC_CON;
1458
+	regmap_write(bsp_priv->grf, offset, val);
1459
+
1460
+	return;
1461
+err:
1462
+	dev_err(dev, "unknown RMII speed value for GMAC speed=%d", speed);
1463
+}
1464
+
1465
+static void rk3528_set_clock_selection(struct rk_priv_data *bsp_priv,
1466
+				       bool input, bool enable)
1467
+{
1468
+	unsigned int value, id = bsp_priv->bus_id;
1469
+
1470
+	if (id == 1) {
1471
+		value = input ? RK3528_GMAC1_CLK_SELET_IO :
1472
+				RK3528_GMAC1_CLK_SELET_CRU;
1473
+		value |= enable ? RK3528_GMAC1_CLK_RMII_NOGATE :
1474
+				  RK3528_GMAC1_CLK_RMII_GATE;
1475
+		regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, value);
1476
+	} else {
1477
+		value = enable ? RK3528_GMAC0_CLK_RMII_NOGATE :
1478
+				 RK3528_GMAC0_CLK_RMII_GATE;
1479
+		regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON, value);
1480
+	}
1481
+}
1482
+
1483
+static void rk3528_integrated_sphy_power(struct rk_priv_data *priv, bool up)
1484
+{
1485
+	struct device *dev = &priv->pdev->dev;
1486
+	unsigned int id = priv->bus_id;
1487
+
1488
+	/* Only GMAC0 support integrated phy */
1489
+	if (id > 0)
1490
+		return;
1491
+
1492
+	if (IS_ERR(priv->grf) || !priv->phy_reset) {
1493
+		dev_err(dev, "%s: Missing rockchip,grf or phy_reset property\n",
1494
+			__func__);
1495
+		return;
1496
+	}
1497
+
1498
+	if (up) {
1499
+		unsigned int bgs = RK3528_VO_GRF_MACPHY_BGS;
1500
+
1501
+		reset_control_assert(priv->phy_reset);
1502
+		udelay(20);
1503
+		regmap_write(priv->grf, RK3528_VO_GRF_MACPHY_CON0,
1504
+			     RK3528_VO_GRF_MACPHY_POWERUP |
1505
+			     RK3528_VO_GRF_MACPHY_INTERNAL_RMII_SEL |
1506
+			     RK3528_VO_GRF_MACPHY_24M_CLK_SEL |
1507
+			     RK3528_VO_GRF_MACPHY_PHY_ID);
1508
+
1509
+		if (priv->otp_data > 0)
1510
+			bgs = HIWORD_UPDATE(priv->otp_data, 0xf, 0);
1511
+
1512
+		regmap_write(priv->grf, RK3528_VO_GRF_MACPHY_CON1, bgs);
1513
+		usleep_range(10 * 1000, 12 * 1000);
1514
+		reset_control_deassert(priv->phy_reset);
1515
+		usleep_range(50 * 1000, 60 * 1000);
1516
+	} else {
1517
+		regmap_write(priv->grf, RK3528_VO_GRF_MACPHY_CON0,
1518
+			     RK3528_VO_GRF_MACPHY_SHUTDOWN);
1519
+	}
1520
+}
1521
+
1522
+static const struct rk_gmac_ops rk3528_ops = {
1523
+	.set_to_rgmii = rk3528_set_to_rgmii,
1524
+	.set_to_rmii = rk3528_set_to_rmii,
1525
+	.set_rgmii_speed = rk3528_set_rgmii_speed,
1526
+	.set_rmii_speed = rk3528_set_rmii_speed,
1527
+	.set_clock_selection = rk3528_set_clock_selection,
1528
+	.integrated_phy_power = rk3528_integrated_sphy_power,
1529
+};
1530
+
1325
1531
 #define RK3568_GRF_GMAC0_CON0		0X0380
1326
1532
 #define RK3568_GRF_GMAC0_CON1		0X0384
1327
1533
 #define RK3568_GRF_GMAC1_CON0		0X0388
..
..
@@ -1708,8 +1914,10 @@
1708
1914
 		   bsp_priv->phy_iface == PHY_INTERFACE_MODE_QSGMII) {
1709
1915
 		bsp_priv->pclk_xpcs = devm_clk_get(dev, "pclk_xpcs");
1710
1916
 		if (IS_ERR(bsp_priv->pclk_xpcs))
1711
-			dev_err(dev, "cannot get clock %s\n",
1712
-				"pclk_xpcs");
1917
+			dev_err(dev, "cannot get clock %s\n", "pclk_xpcs");
1918
+		bsp_priv->clk_xpcs_eee = devm_clk_get(dev, "clk_xpcs_eee");
1919
+		if (IS_ERR(bsp_priv->clk_xpcs_eee))
1920
+			dev_err(dev, "cannot get clock %s\n", "clk_xpcs_eee");
1713
1921
 	}
1714
1922
 
1715
1923
 	bsp_priv->clk_mac_speed = devm_clk_get(dev, "clk_mac_speed");
..
..
@@ -1777,6 +1985,9 @@
1777
1985
 			if (!IS_ERR(bsp_priv->pclk_xpcs))
1778
1986
 				clk_prepare_enable(bsp_priv->pclk_xpcs);
1779
1987
 
1988
+			if (!IS_ERR(bsp_priv->clk_xpcs_eee))
1989
+				clk_prepare_enable(bsp_priv->clk_xpcs_eee);
1990
+
1780
1991
 			if (bsp_priv->ops && bsp_priv->ops->set_clock_selection)
1781
1992
 				bsp_priv->ops->set_clock_selection(bsp_priv, bsp_priv->clock_input,
1782
1993
 								   true);
..
..
@@ -1813,6 +2024,8 @@
1813
2024
 			clk_disable_unprepare(bsp_priv->clk_mac_speed);
1814
2025
 
1815
2026
 			clk_disable_unprepare(bsp_priv->pclk_xpcs);
2027
+
2028
+			clk_disable_unprepare(bsp_priv->clk_xpcs_eee);
1816
2029
 
1817
2030
 			/**
1818
2031
 			 * if (!IS_ERR(bsp_priv->clk_mac))
..
..
@@ -1926,10 +2139,34 @@
1926
2139
 		bsp_priv->integrated_phy = of_property_read_bool(plat->phy_node,
1927
2140
 								 "phy-is-integrated");
1928
2141
 		if (bsp_priv->integrated_phy) {
2142
+			unsigned char *efuse_buf;
2143
+			struct nvmem_cell *cell;
2144
+			size_t len;
2145
+
1929
2146
 			bsp_priv->phy_reset = of_reset_control_get(plat->phy_node, NULL);
1930
2147
 			if (IS_ERR(bsp_priv->phy_reset)) {
1931
2148
 				dev_err(&pdev->dev, "No PHY reset control found.\n");
1932
2149
 				bsp_priv->phy_reset = NULL;
2150
+			}
2151
+
2152
+			/* Read bgs from OTP if it exists */
2153
+			cell = nvmem_cell_get(dev, "bgs");
2154
+			if (IS_ERR(cell)) {
2155
+				if (PTR_ERR(cell) != -EPROBE_DEFER)
2156
+					dev_info(dev, "failed to get bgs cell: %ld, use default\n",
2157
+						 PTR_ERR(cell));
2158
+				else
2159
+					return ERR_CAST(cell);
2160
+			} else {
2161
+				efuse_buf = nvmem_cell_read(cell, &len);
2162
+				nvmem_cell_put(cell);
2163
+				if (!IS_ERR(efuse_buf)) {
2164
+					if (len == 1)
2165
+						bsp_priv->otp_data = efuse_buf[0];
2166
+					kfree(efuse_buf);
2167
+				} else {
2168
+					dev_err(dev, "failed to get efuse buf, use default\n");
2169
+				}
1933
2170
 			}
1934
2171
 		}
1935
2172
 	}
..
..
@@ -2284,6 +2521,9 @@
2284
2521
 #ifdef CONFIG_CPU_RK3399
2285
2522
 	{ .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops },
2286
2523
 #endif
2524
+#ifdef CONFIG_CPU_RK3528
2525
+	{ .compatible = "rockchip,rk3528-gmac", .data = &rk3528_ops },
2526
+#endif
2287
2527
 #ifdef CONFIG_CPU_RK3568
2288
2528
 	{ .compatible = "rockchip,rk3568-gmac", .data = &rk3568_ops },
2289
2529
 #endif