~ljy/RK356X_SDK_RELEASE.git

..	..	@@ -24,6 +24,7 @@
24	24	#include <linux/of_net.h>
25	25	#include <linux/gpio.h>
26	26	#include <linux/module.h>
	27	+#include <linux/nvmem-consumer.h>
27	28	#include <linux/of_gpio.h>
28	29	#include <linux/of_device.h>
29	30	#include <linux/platform_device.h>
..	..	@@ -47,7 +48,10 @@
47	48	void (set_to_qsgmii)(struct rk_priv_data bsp_priv);
48	49	void (set_rgmii_speed)(struct rk_priv_data bsp_priv, int speed);
49	50	void (set_rmii_speed)(struct rk_priv_data bsp_priv, int speed);
50		- void (integrated_phy_powerup)(struct rk_priv_data bsp_priv);
	51	+ void (set_sgmii_speed)(struct rk_priv_data bsp_priv, int speed);
	52	+ void (set_clock_selection)(struct rk_priv_data bsp_priv, bool input,
	53	+ bool enable);
	54	+ void (integrated_phy_power)(struct rk_priv_data bsp_priv, bool up);
51	55	};
52	56
53	57	struct rk_priv_data {
..	..	@@ -61,6 +65,7 @@
61	65	bool clk_enabled;
62	66	bool clock_input;
63	67	bool integrated_phy;
	68	+ struct phy *comphy;
64	69
65	70	struct clk *clk_mac;
66	71	struct clk *gmac_clkin;
..	..	@@ -73,6 +78,7 @@
73	78	struct clk *pclk_mac;
74	79	struct clk *clk_phy;
75	80	struct clk *pclk_xpcs;
	81	+ struct clk *clk_xpcs_eee;
76	82
77	83	struct reset_control *phy_reset;
78	84
..	..	@@ -81,6 +87,8 @@
81	87
82	88	struct regmap *grf;
83	89	struct regmap *xpcs;
	90	+
	91	+ unsigned char otp_data;
84	92	};
85	93
86	94	/* XPCS */
..	..	@@ -165,10 +173,10 @@
165	173	int ret, i, id = bsp_priv->bus_id;
166	174	u32 val;
167	175
168		- if (mode == PHY_INTERFACE_MODE_QSGMII && id > 0)
	176	+ if (mode == PHY_INTERFACE_MODE_QSGMII && !id)
169	177	return 0;
170	178
171		- ret = xpcs_soft_reset(bsp_priv, id);
	179	+ ret = xpcs_soft_reset(bsp_priv, 0);
172	180	if (ret) {
173	181	dev_err(&bsp_priv->pdev->dev, "xpcs_soft_reset fail %d\n", ret);
174	182	return ret;
..	..	@@ -195,10 +203,10 @@
195	203	SR_MII_CTRL_AN_ENABLE);
196	204	}
197	205	} else {
198		- val = xpcs_read(bsp_priv, SR_MII_OFFSET(id) + VR_MII_DIG_CTRL1);
199		- xpcs_write(bsp_priv, SR_MII_OFFSET(id) + VR_MII_DIG_CTRL1,
	206	+ val = xpcs_read(bsp_priv, SR_MII_OFFSET(0) + VR_MII_DIG_CTRL1);
	207	+ xpcs_write(bsp_priv, SR_MII_OFFSET(0) + VR_MII_DIG_CTRL1,
200	208	val \| MII_MAC_AUTO_SW);
201		- xpcs_write(bsp_priv, SR_MII_OFFSET(id) + MII_BMCR,
	209	+ xpcs_write(bsp_priv, SR_MII_OFFSET(0) + MII_BMCR,
202	210	SR_MII_CTRL_AN_ENABLE);
203	211	}
204	212
..	..	@@ -212,8 +220,55 @@
212	220	#define GRF_CLR_BIT(nr) (BIT(nr+16))
213	221
214	222	#define DELAY_ENABLE(soc, tx, rx) \
215		- (((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) \| \
216		- ((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE))
	223	+ ((((tx) >= 0) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) \| \
	224	+ (((rx) >= 0) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE))
	225	+
	226	+#define DELAY_VALUE(soc, tx, rx) \
	227	+ ((((tx) >= 0) ? soc##_GMAC_CLK_TX_DL_CFG(tx) : 0) \| \
	228	+ (((rx) >= 0) ? soc##_GMAC_CLK_RX_DL_CFG(rx) : 0))
	229	+
	230	+/* Integrated EPHY */
	231	+
	232	+#define RK_GRF_MACPHY_CON0 0xb00
	233	+#define RK_GRF_MACPHY_CON1 0xb04
	234	+#define RK_GRF_MACPHY_CON2 0xb08
	235	+#define RK_GRF_MACPHY_CON3 0xb0c
	236	+
	237	+#define RK_MACPHY_ENABLE GRF_BIT(0)
	238	+#define RK_MACPHY_DISABLE GRF_CLR_BIT(0)
	239	+#define RK_MACPHY_CFG_CLK_50M GRF_BIT(14)
	240	+#define RK_GMAC2PHY_RMII_MODE (GRF_BIT(6) \| GRF_CLR_BIT(7))
	241	+#define RK_GRF_CON2_MACPHY_ID HIWORD_UPDATE(0x1234, 0xffff, 0)
	242	+#define RK_GRF_CON3_MACPHY_ID HIWORD_UPDATE(0x35, 0x3f, 0)
	243	+
	244	+static void rk_gmac_integrated_ephy_powerup(struct rk_priv_data *priv)
	245	+{
	246	+ regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M);
	247	+ regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE);
	248	+
	249	+ regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID);
	250	+ regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID);
	251	+
	252	+ if (priv->phy_reset) {
	253	+ /* PHY needs to be disabled before trying to reset it */
	254	+ regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
	255	+ if (priv->phy_reset)
	256	+ reset_control_assert(priv->phy_reset);
	257	+ usleep_range(10, 20);
	258	+ if (priv->phy_reset)
	259	+ reset_control_deassert(priv->phy_reset);
	260	+ usleep_range(10, 20);
	261	+ regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE);
	262	+ msleep(30);
	263	+ }
	264	+}
	265	+
	266	+static void rk_gmac_integrated_ephy_powerdown(struct rk_priv_data *priv)
	267	+{
	268	+ regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
	269	+ if (priv->phy_reset)
	270	+ reset_control_assert(priv->phy_reset);
	271	+}
217	272
218	273	#define PX30_GRF_GMAC_CON1 0x0904
219	274
..	..	@@ -306,12 +361,10 @@
306	361
307	362	regmap_write(bsp_priv->grf, RK1808_GRF_GMAC_CON1,
308	363	RK1808_GMAC_PHY_INTF_SEL_RGMII \|
309		- RK1808_GMAC_RXCLK_DLY_ENABLE \|
310		- RK1808_GMAC_TXCLK_DLY_ENABLE);
	364	+ DELAY_ENABLE(RK1808, tx_delay, rx_delay));
311	365
312	366	regmap_write(bsp_priv->grf, RK1808_GRF_GMAC_CON0,
313		- RK1808_GMAC_CLK_RX_DL_CFG(rx_delay) \|
314		- RK1808_GMAC_CLK_TX_DL_CFG(tx_delay));
	367	+ DELAY_VALUE(RK1808, tx_delay, rx_delay));
315	368	}
316	369
317	370	static void rk1808_set_to_rmii(struct rk_priv_data *bsp_priv)
..	..	@@ -439,8 +492,7 @@
439	492	RK3128_GMAC_RMII_MODE_CLR);
440	493	regmap_write(bsp_priv->grf, RK3128_GRF_MAC_CON0,
441	494	DELAY_ENABLE(RK3128, tx_delay, rx_delay) \|
442		- RK3128_GMAC_CLK_RX_DL_CFG(rx_delay) \|
443		- RK3128_GMAC_CLK_TX_DL_CFG(tx_delay));
	495	+ DELAY_VALUE(RK3128, tx_delay, rx_delay));
444	496	}
445	497
446	498	static void rk3128_set_to_rmii(struct rk_priv_data *bsp_priv)
..	..	@@ -556,8 +608,7 @@
556	608	DELAY_ENABLE(RK3228, tx_delay, rx_delay));
557	609
558	610	regmap_write(bsp_priv->grf, RK3228_GRF_MAC_CON0,
559		- RK3228_GMAC_CLK_RX_DL_CFG(rx_delay) \|
560		- RK3228_GMAC_CLK_TX_DL_CFG(tx_delay));
	611	+ DELAY_VALUE(RK3128, tx_delay, rx_delay));
561	612	}
562	613
563	614	static void rk3228_set_to_rmii(struct rk_priv_data *bsp_priv)
..	..	@@ -620,10 +671,16 @@
620	671	dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
621	672	}
622	673
623		-static void rk3228_integrated_phy_powerup(struct rk_priv_data *priv)
	674	+static void rk3228_integrated_phy_power(struct rk_priv_data *priv, bool up)
624	675	{
625		- regmap_write(priv->grf, RK3228_GRF_CON_MUX,
626		- RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY);
	676	+ if (up) {
	677	+ regmap_write(priv->grf, RK3228_GRF_CON_MUX,
	678	+ RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY);
	679	+
	680	+ rk_gmac_integrated_ephy_powerup(priv);
	681	+ } else {
	682	+ rk_gmac_integrated_ephy_powerdown(priv);
	683	+ }
627	684	}
628	685
629	686	static const struct rk_gmac_ops rk3228_ops = {
..	..	@@ -631,7 +688,7 @@
631	688	.set_to_rmii = rk3228_set_to_rmii,
632	689	.set_rgmii_speed = rk3228_set_rgmii_speed,
633	690	.set_rmii_speed = rk3228_set_rmii_speed,
634		- .integrated_phy_powerup = rk3228_integrated_phy_powerup,
	691	+ .integrated_phy_power = rk3228_integrated_phy_power,
635	692	};
636	693
637	694	#define RK3288_GRF_SOC_CON1 0x0248
..	..	@@ -677,8 +734,7 @@
677	734	RK3288_GMAC_RMII_MODE_CLR);
678	735	regmap_write(bsp_priv->grf, RK3288_GRF_SOC_CON3,
679	736	DELAY_ENABLE(RK3288, tx_delay, rx_delay) \|
680		- RK3288_GMAC_CLK_RX_DL_CFG(rx_delay) \|
681		- RK3288_GMAC_CLK_TX_DL_CFG(tx_delay));
	737	+ DELAY_VALUE(RK3288, tx_delay, rx_delay));
682	738	}
683	739
684	740	static void rk3288_set_to_rmii(struct rk_priv_data *bsp_priv)
..	..	@@ -849,12 +905,10 @@
849	905	regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON1,
850	906	RK3328_GMAC_PHY_INTF_SEL_RGMII \|
851	907	RK3328_GMAC_RMII_MODE_CLR \|
852		- RK3328_GMAC_RXCLK_DLY_ENABLE \|
853		- RK3328_GMAC_TXCLK_DLY_ENABLE);
	908	+ DELAY_ENABLE(RK3328, tx_delay, rx_delay));
854	909
855	910	regmap_write(bsp_priv->grf, RK3328_GRF_MAC_CON0,
856		- RK3328_GMAC_CLK_RX_DL_CFG(rx_delay) \|
857		- RK3328_GMAC_CLK_TX_DL_CFG(tx_delay));
	911	+ DELAY_VALUE(RK3328, tx_delay, rx_delay));
858	912	}
859	913
860	914	static void rk3328_set_to_rmii(struct rk_priv_data *bsp_priv)
..	..	@@ -922,10 +976,16 @@
922	976	dev_err(dev, "unknown speed value for RMII! speed=%d", speed);
923	977	}
924	978
925		-static void rk3328_integrated_phy_powerup(struct rk_priv_data *priv)
	979	+static void rk3328_integrated_phy_power(struct rk_priv_data *priv, bool up)
926	980	{
927		- regmap_write(priv->grf, RK3328_GRF_MACPHY_CON1,
928		- RK3328_MACPHY_RMII_MODE);
	981	+ if (up) {
	982	+ regmap_write(priv->grf, RK3328_GRF_MACPHY_CON1,
	983	+ RK3328_MACPHY_RMII_MODE);
	984	+
	985	+ rk_gmac_integrated_ephy_powerup(priv);
	986	+ } else {
	987	+ rk_gmac_integrated_ephy_powerdown(priv);
	988	+ }
929	989	}
930	990
931	991	static const struct rk_gmac_ops rk3328_ops = {
..	..	@@ -933,7 +993,7 @@
933	993	.set_to_rmii = rk3328_set_to_rmii,
934	994	.set_rgmii_speed = rk3328_set_rgmii_speed,
935	995	.set_rmii_speed = rk3328_set_rmii_speed,
936		- .integrated_phy_powerup = rk3328_integrated_phy_powerup,
	996	+ .integrated_phy_power = rk3328_integrated_phy_power,
937	997	};
938	998
939	999	#define RK3366_GRF_SOC_CON6 0x0418
..	..	@@ -979,8 +1039,7 @@
979	1039	RK3366_GMAC_RMII_MODE_CLR);
980	1040	regmap_write(bsp_priv->grf, RK3366_GRF_SOC_CON7,
981	1041	DELAY_ENABLE(RK3366, tx_delay, rx_delay) \|
982		- RK3366_GMAC_CLK_RX_DL_CFG(rx_delay) \|
983		- RK3366_GMAC_CLK_TX_DL_CFG(tx_delay));
	1042	+ DELAY_VALUE(RK3366, tx_delay, rx_delay));
984	1043	}
985	1044
986	1045	static void rk3366_set_to_rmii(struct rk_priv_data *bsp_priv)
..	..	@@ -1090,8 +1149,7 @@
1090	1149	RK3368_GMAC_RMII_MODE_CLR);
1091	1150	regmap_write(bsp_priv->grf, RK3368_GRF_SOC_CON16,
1092	1151	DELAY_ENABLE(RK3368, tx_delay, rx_delay) \|
1093		- RK3368_GMAC_CLK_RX_DL_CFG(rx_delay) \|
1094		- RK3368_GMAC_CLK_TX_DL_CFG(tx_delay));
	1152	+ DELAY_VALUE(RK3368, tx_delay, rx_delay));
1095	1153	}
1096	1154
1097	1155	static void rk3368_set_to_rmii(struct rk_priv_data *bsp_priv)
..	..	@@ -1201,8 +1259,7 @@
1201	1259	RK3399_GMAC_RMII_MODE_CLR);
1202	1260	regmap_write(bsp_priv->grf, RK3399_GRF_SOC_CON6,
1203	1261	DELAY_ENABLE(RK3399, tx_delay, rx_delay) \|
1204		- RK3399_GMAC_CLK_RX_DL_CFG(rx_delay) \|
1205		- RK3399_GMAC_CLK_TX_DL_CFG(tx_delay));
	1262	+ DELAY_VALUE(RK3399, tx_delay, rx_delay));
1206	1263	}
1207	1264
1208	1265	static void rk3399_set_to_rmii(struct rk_priv_data *bsp_priv)
..	..	@@ -1267,6 +1324,208 @@
1267	1324	.set_to_rmii = rk3399_set_to_rmii,
1268	1325	.set_rgmii_speed = rk3399_set_rgmii_speed,
1269	1326	.set_rmii_speed = rk3399_set_rmii_speed,
	1327	+};
	1328	+
	1329	+#define RK3528_VO_GRF_GMAC_CON 0X60018
	1330	+#define RK3528_VPU_GRF_GMAC_CON5 0X40018
	1331	+#define RK3528_VPU_GRF_GMAC_CON6 0X4001c
	1332	+
	1333	+#define RK3528_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15)
	1334	+#define RK3528_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15)
	1335	+#define RK3528_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14)
	1336	+#define RK3528_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14)
	1337	+
	1338	+#define RK3528_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 8)
	1339	+#define RK3528_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 0)
	1340	+
	1341	+#define RK3528_GMAC0_PHY_INTF_SEL_RMII GRF_BIT(1)
	1342	+#define RK3528_GMAC1_PHY_INTF_SEL_RGMII GRF_CLR_BIT(8)
	1343	+#define RK3528_GMAC1_PHY_INTF_SEL_RMII GRF_BIT(8)
	1344	+
	1345	+#define RK3528_GMAC1_CLK_SELET_CRU GRF_CLR_BIT(12)
	1346	+#define RK3528_GMAC1_CLK_SELET_IO GRF_BIT(12)
	1347	+
	1348	+#define RK3528_GMAC0_CLK_RMII_DIV2 GRF_BIT(3)
	1349	+#define RK3528_GMAC0_CLK_RMII_DIV20 GRF_CLR_BIT(3)
	1350	+#define RK3528_GMAC1_CLK_RMII_DIV2 GRF_BIT(10)
	1351	+#define RK3528_GMAC1_CLK_RMII_DIV20 GRF_CLR_BIT(10)
	1352	+
	1353	+#define RK3528_GMAC1_CLK_RGMII_DIV1 \
	1354	+ (GRF_CLR_BIT(11) \| GRF_CLR_BIT(10))
	1355	+#define RK3528_GMAC1_CLK_RGMII_DIV5 \
	1356	+ (GRF_BIT(11) \| GRF_BIT(10))
	1357	+#define RK3528_GMAC1_CLK_RGMII_DIV50 \
	1358	+ (GRF_BIT(11) \| GRF_CLR_BIT(10))
	1359	+
	1360	+#define RK3528_GMAC0_CLK_RMII_GATE GRF_BIT(2)
	1361	+#define RK3528_GMAC0_CLK_RMII_NOGATE GRF_CLR_BIT(2)
	1362	+#define RK3528_GMAC1_CLK_RMII_GATE GRF_BIT(9)
	1363	+#define RK3528_GMAC1_CLK_RMII_NOGATE GRF_CLR_BIT(9)
	1364	+
	1365	+#define RK3528_VO_GRF_MACPHY_CON0 0X6001c
	1366	+#define RK3528_VO_GRF_MACPHY_CON1 0X60020
	1367	+
	1368	+#define RK3528_VO_GRF_MACPHY_SHUTDOWN GRF_BIT(1)
	1369	+#define RK3528_VO_GRF_MACPHY_POWERUP GRF_CLR_BIT(1)
	1370	+#define RK3528_VO_GRF_MACPHY_INTERNAL_RMII_SEL GRF_BIT(6)
	1371	+#define RK3528_VO_GRF_MACPHY_24M_CLK_SEL (GRF_BIT(8) \| GRF_BIT(9))
	1372	+#define RK3528_VO_GRF_MACPHY_PHY_ID GRF_BIT(11)
	1373	+
	1374	+#define RK3528_VO_GRF_MACPHY_BGS HIWORD_UPDATE(0x0, 0xf, 0)
	1375	+
	1376	+static void rk3528_set_to_rgmii(struct rk_priv_data *bsp_priv,
	1377	+ int tx_delay, int rx_delay)
	1378	+{
	1379	+ struct device *dev = &bsp_priv->pdev->dev;
	1380	+
	1381	+ if (IS_ERR(bsp_priv->grf)) {
	1382	+ dev_err(dev, "Missing rockchip,grf property\n");
	1383	+ return;
	1384	+ }
	1385	+
	1386	+ regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
	1387	+ RK3528_GMAC1_PHY_INTF_SEL_RGMII);
	1388	+
	1389	+ regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
	1390	+ DELAY_ENABLE(RK3528, tx_delay, rx_delay));
	1391	+
	1392	+ regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON6,
	1393	+ DELAY_VALUE(RK3528, tx_delay, rx_delay));
	1394	+}
	1395	+
	1396	+static void rk3528_set_to_rmii(struct rk_priv_data *bsp_priv)
	1397	+{
	1398	+ struct device *dev = &bsp_priv->pdev->dev;
	1399	+ unsigned int id = bsp_priv->bus_id;
	1400	+
	1401	+ if (IS_ERR(bsp_priv->grf)) {
	1402	+ dev_err(dev, "%s: Missing rockchip,grf property\n", __func__);
	1403	+ return;
	1404	+ }
	1405	+
	1406	+ if (id == 1)
	1407	+ regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5,
	1408	+ RK3528_GMAC1_PHY_INTF_SEL_RMII);
	1409	+ else
	1410	+ regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON,
	1411	+ RK3528_GMAC0_PHY_INTF_SEL_RMII);
	1412	+}
	1413	+
	1414	+static void rk3528_set_rgmii_speed(struct rk_priv_data *bsp_priv, int speed)
	1415	+{
	1416	+ struct device *dev = &bsp_priv->pdev->dev;
	1417	+ unsigned int val = 0;
	1418	+
	1419	+ switch (speed) {
	1420	+ case 10:
	1421	+ val = RK3528_GMAC1_CLK_RGMII_DIV50;
	1422	+ break;
	1423	+ case 100:
	1424	+ val = RK3528_GMAC1_CLK_RGMII_DIV5;
	1425	+ break;
	1426	+ case 1000:
	1427	+ val = RK3528_GMAC1_CLK_RGMII_DIV1;
	1428	+ break;
	1429	+ default:
	1430	+ goto err;
	1431	+ }
	1432	+
	1433	+ regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, val);
	1434	+ return;
	1435	+err:
	1436	+ dev_err(dev, "unknown RGMII speed value for GMAC speed=%d", speed);
	1437	+}
	1438	+
	1439	+static void rk3528_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed)
	1440	+{
	1441	+ struct device *dev = &bsp_priv->pdev->dev;
	1442	+ unsigned int val, offset, id = bsp_priv->bus_id;
	1443	+
	1444	+ switch (speed) {
	1445	+ case 10:
	1446	+ val = (id == 1) ? RK3528_GMAC1_CLK_RMII_DIV20 :
	1447	+ RK3528_GMAC0_CLK_RMII_DIV20;
	1448	+ break;
	1449	+ case 100:
	1450	+ val = (id == 1) ? RK3528_GMAC1_CLK_RMII_DIV2 :
	1451	+ RK3528_GMAC0_CLK_RMII_DIV2;
	1452	+ break;
	1453	+ default:
	1454	+ goto err;
	1455	+ }
	1456	+
	1457	+ offset = (id == 1) ? RK3528_VPU_GRF_GMAC_CON5 : RK3528_VO_GRF_GMAC_CON;
	1458	+ regmap_write(bsp_priv->grf, offset, val);
	1459	+
	1460	+ return;
	1461	+err:
	1462	+ dev_err(dev, "unknown RMII speed value for GMAC speed=%d", speed);
	1463	+}
	1464	+
	1465	+static void rk3528_set_clock_selection(struct rk_priv_data *bsp_priv,
	1466	+ bool input, bool enable)
	1467	+{
	1468	+ unsigned int value, id = bsp_priv->bus_id;
	1469	+
	1470	+ if (id == 1) {
	1471	+ value = input ? RK3528_GMAC1_CLK_SELET_IO :
	1472	+ RK3528_GMAC1_CLK_SELET_CRU;
	1473	+ value \|= enable ? RK3528_GMAC1_CLK_RMII_NOGATE :
	1474	+ RK3528_GMAC1_CLK_RMII_GATE;
	1475	+ regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, value);
	1476	+ } else {
	1477	+ value = enable ? RK3528_GMAC0_CLK_RMII_NOGATE :
	1478	+ RK3528_GMAC0_CLK_RMII_GATE;
	1479	+ regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON, value);
	1480	+ }
	1481	+}
	1482	+
	1483	+static void rk3528_integrated_sphy_power(struct rk_priv_data *priv, bool up)
	1484	+{
	1485	+ struct device *dev = &priv->pdev->dev;
	1486	+ unsigned int id = priv->bus_id;
	1487	+
	1488	+ /* Only GMAC0 support integrated phy */
	1489	+ if (id > 0)
	1490	+ return;
	1491	+
	1492	+ if (IS_ERR(priv->grf) \|\| !priv->phy_reset) {
	1493	+ dev_err(dev, "%s: Missing rockchip,grf or phy_reset property\n",
	1494	+ __func__);
	1495	+ return;
	1496	+ }
	1497	+
	1498	+ if (up) {
	1499	+ unsigned int bgs = RK3528_VO_GRF_MACPHY_BGS;
	1500	+
	1501	+ reset_control_assert(priv->phy_reset);
	1502	+ udelay(20);
	1503	+ regmap_write(priv->grf, RK3528_VO_GRF_MACPHY_CON0,
	1504	+ RK3528_VO_GRF_MACPHY_POWERUP \|
	1505	+ RK3528_VO_GRF_MACPHY_INTERNAL_RMII_SEL \|
	1506	+ RK3528_VO_GRF_MACPHY_24M_CLK_SEL \|
	1507	+ RK3528_VO_GRF_MACPHY_PHY_ID);
	1508	+
	1509	+ if (priv->otp_data > 0)
	1510	+ bgs = HIWORD_UPDATE(priv->otp_data, 0xf, 0);
	1511	+
	1512	+ regmap_write(priv->grf, RK3528_VO_GRF_MACPHY_CON1, bgs);
	1513	+ usleep_range(10 * 1000, 12 * 1000);
	1514	+ reset_control_deassert(priv->phy_reset);
	1515	+ usleep_range(50 * 1000, 60 * 1000);
	1516	+ } else {
	1517	+ regmap_write(priv->grf, RK3528_VO_GRF_MACPHY_CON0,
	1518	+ RK3528_VO_GRF_MACPHY_SHUTDOWN);
	1519	+ }
	1520	+}
	1521	+
	1522	+static const struct rk_gmac_ops rk3528_ops = {
	1523	+ .set_to_rgmii = rk3528_set_to_rgmii,
	1524	+ .set_to_rmii = rk3528_set_to_rmii,
	1525	+ .set_rgmii_speed = rk3528_set_rgmii_speed,
	1526	+ .set_rmii_speed = rk3528_set_rmii_speed,
	1527	+ .set_clock_selection = rk3528_set_clock_selection,
	1528	+ .integrated_phy_power = rk3528_integrated_sphy_power,
1270	1529	};
1271	1530
1272	1531	#define RK3568_GRF_GMAC0_CON0 0X0380
..	..	@@ -1349,12 +1608,10 @@
1349	1608
1350	1609	regmap_write(bsp_priv->grf, offset_con1,
1351	1610	RK3568_GMAC_PHY_INTF_SEL_RGMII \|
1352		- RK3568_GMAC_RXCLK_DLY_ENABLE \|
1353		- RK3568_GMAC_TXCLK_DLY_ENABLE);
	1611	+ DELAY_ENABLE(RK3568, tx_delay, rx_delay));
1354	1612
1355	1613	regmap_write(bsp_priv->grf, offset_con0,
1356		- RK3568_GMAC_CLK_RX_DL_CFG(rx_delay) \|
1357		- RK3568_GMAC_CLK_TX_DL_CFG(tx_delay));
	1614	+ DELAY_VALUE(RK3568, tx_delay, rx_delay));
1358	1615	}
1359	1616
1360	1617	static void rk3568_set_to_rmii(struct rk_priv_data *bsp_priv)
..	..	@@ -1400,6 +1657,34 @@
1400	1657	__func__, rate, ret);
1401	1658	}
1402	1659
	1660	+static void rk3568_set_gmac_sgmii_speed(struct rk_priv_data *bsp_priv, int speed)
	1661	+{
	1662	+ struct device *dev = &bsp_priv->pdev->dev;
	1663	+ unsigned int ctrl;
	1664	+
	1665	+ /* Only gmac1 set the speed for port1 */
	1666	+ if (!bsp_priv->bus_id)
	1667	+ return;
	1668	+
	1669	+ switch (speed) {
	1670	+ case 10:
	1671	+ ctrl = BMCR_SPEED10;
	1672	+ break;
	1673	+ case 100:
	1674	+ ctrl = BMCR_SPEED100;
	1675	+ break;
	1676	+ case 1000:
	1677	+ ctrl = BMCR_SPEED1000;
	1678	+ break;
	1679	+ default:
	1680	+ dev_err(dev, "unknown speed value for GMAC speed=%d", speed);
	1681	+ return;
	1682	+ }
	1683	+
	1684	+ xpcs_write(bsp_priv, SR_MII_OFFSET(bsp_priv->bus_id) + MII_BMCR,
	1685	+ ctrl \| BMCR_FULLDPLX);
	1686	+}
	1687	+
1403	1688	static const struct rk_gmac_ops rk3568_ops = {
1404	1689	.set_to_rgmii = rk3568_set_to_rgmii,
1405	1690	.set_to_rmii = rk3568_set_to_rmii,
..	..	@@ -1407,6 +1692,7 @@
1407	1692	.set_to_qsgmii = rk3568_set_to_qsgmii,
1408	1693	.set_rgmii_speed = rk3568_set_gmac_speed,
1409	1694	.set_rmii_speed = rk3568_set_gmac_speed,
	1695	+ .set_sgmii_speed = rk3568_set_gmac_sgmii_speed,
1410	1696	};
1411	1697
1412	1698	#define RV1108_GRF_GMAC_CON0 0X0900
..	..	@@ -1472,21 +1758,18 @@
1472	1758	(GRF_CLR_BIT(4) \| GRF_CLR_BIT(5) \| GRF_BIT(6))
1473	1759	#define RV1126_GMAC_FLOW_CTRL GRF_BIT(7)
1474	1760	#define RV1126_GMAC_FLOW_CTRL_CLR GRF_CLR_BIT(7)
1475		-#define RV1126_GMAC_M0_RXCLK_DLY_ENABLE GRF_BIT(1)
1476		-#define RV1126_GMAC_M0_RXCLK_DLY_DISABLE GRF_CLR_BIT(1)
1477		-#define RV1126_GMAC_M0_TXCLK_DLY_ENABLE GRF_BIT(0)
1478		-#define RV1126_GMAC_M0_TXCLK_DLY_DISABLE GRF_CLR_BIT(0)
1479		-#define RV1126_GMAC_M1_RXCLK_DLY_ENABLE GRF_BIT(3)
1480		-#define RV1126_GMAC_M1_RXCLK_DLY_DISABLE GRF_CLR_BIT(3)
1481		-#define RV1126_GMAC_M1_TXCLK_DLY_ENABLE GRF_BIT(2)
1482		-#define RV1126_GMAC_M1_TXCLK_DLY_DISABLE GRF_CLR_BIT(2)
	1761	+#define RV1126_M0_GMAC_RXCLK_DLY_ENABLE GRF_BIT(1)
	1762	+#define RV1126_M0_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(1)
	1763	+#define RV1126_M0_GMAC_TXCLK_DLY_ENABLE GRF_BIT(0)
	1764	+#define RV1126_M0_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(0)
	1765	+#define RV1126_M1_GMAC_RXCLK_DLY_ENABLE GRF_BIT(3)
	1766	+#define RV1126_M1_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(3)
	1767	+#define RV1126_M1_GMAC_TXCLK_DLY_ENABLE GRF_BIT(2)
	1768	+#define RV1126_M1_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(2)
1483	1769
1484		-/* RV1126_GRF_GMAC_CON1 */
1485		-#define RV1126_GMAC_M0_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
1486		-#define RV1126_GMAC_M0_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
1487		-/* RV1126_GRF_GMAC_CON2 */
1488		-#define RV1126_GMAC_M1_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
1489		-#define RV1126_GMAC_M1_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
	1770	+/* RV1126_GRF_GMAC_CON1 && RV1126_GRF_GMAC_CON2 */
	1771	+#define RV1126_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 8)
	1772	+#define RV1126_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0x7F, 0)
1490	1773
1491	1774	static void rv1126_set_to_rgmii(struct rk_priv_data *bsp_priv,
1492	1775	int tx_delay, int rx_delay)
..	..	@@ -1500,18 +1783,14 @@
1500	1783
1501	1784	regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON0,
1502	1785	RV1126_GMAC_PHY_INTF_SEL_RGMII \|
1503		- RV1126_GMAC_M0_RXCLK_DLY_ENABLE \|
1504		- RV1126_GMAC_M0_TXCLK_DLY_ENABLE \|
1505		- RV1126_GMAC_M1_RXCLK_DLY_ENABLE \|
1506		- RV1126_GMAC_M1_TXCLK_DLY_ENABLE);
	1786	+ DELAY_ENABLE(RV1126_M0, tx_delay, rx_delay) \|
	1787	+ DELAY_ENABLE(RV1126_M1, tx_delay, rx_delay));
1507	1788
1508	1789	regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON1,
1509		- RV1126_GMAC_M0_CLK_RX_DL_CFG(rx_delay) \|
1510		- RV1126_GMAC_M0_CLK_TX_DL_CFG(tx_delay));
	1790	+ DELAY_VALUE(RV1126, tx_delay, rx_delay));
1511	1791
1512	1792	regmap_write(bsp_priv->grf, RV1126_GRF_GMAC_CON2,
1513		- RV1126_GMAC_M1_CLK_RX_DL_CFG(rx_delay) \|
1514		- RV1126_GMAC_M1_CLK_TX_DL_CFG(tx_delay));
	1793	+ DELAY_VALUE(RV1126, tx_delay, rx_delay));
1515	1794	}
1516	1795
1517	1796	static void rv1126_set_to_rmii(struct rk_priv_data *bsp_priv)
..	..	@@ -1585,50 +1864,6 @@
1585	1864	.set_rmii_speed = rv1126_set_rmii_speed,
1586	1865	};
1587	1866
1588		-#define RK_GRF_MACPHY_CON0 0xb00
1589		-#define RK_GRF_MACPHY_CON1 0xb04
1590		-#define RK_GRF_MACPHY_CON2 0xb08
1591		-#define RK_GRF_MACPHY_CON3 0xb0c
1592		-
1593		-#define RK_MACPHY_ENABLE GRF_BIT(0)
1594		-#define RK_MACPHY_DISABLE GRF_CLR_BIT(0)
1595		-#define RK_MACPHY_CFG_CLK_50M GRF_BIT(14)
1596		-#define RK_GMAC2PHY_RMII_MODE (GRF_BIT(6) \| GRF_CLR_BIT(7))
1597		-#define RK_GRF_CON2_MACPHY_ID HIWORD_UPDATE(0x1234, 0xffff, 0)
1598		-#define RK_GRF_CON3_MACPHY_ID HIWORD_UPDATE(0x35, 0x3f, 0)
1599		-
1600		-static void rk_gmac_integrated_phy_powerup(struct rk_priv_data *priv)
1601		-{
1602		- if (priv->ops->integrated_phy_powerup)
1603		- priv->ops->integrated_phy_powerup(priv);
1604		-
1605		- regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M);
1606		- regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE);
1607		-
1608		- regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID);
1609		- regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID);
1610		-
1611		- if (priv->phy_reset) {
1612		- /* PHY needs to be disabled before trying to reset it */
1613		- regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
1614		- if (priv->phy_reset)
1615		- reset_control_assert(priv->phy_reset);
1616		- usleep_range(10, 20);
1617		- if (priv->phy_reset)
1618		- reset_control_deassert(priv->phy_reset);
1619		- usleep_range(10, 20);
1620		- regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE);
1621		- msleep(30);
1622		- }
1623		-}
1624		-
1625		-static void rk_gmac_integrated_phy_powerdown(struct rk_priv_data *priv)
1626		-{
1627		- regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE);
1628		- if (priv->phy_reset)
1629		- reset_control_assert(priv->phy_reset);
1630		-}
1631		-
1632	1867	static int rk_gmac_clk_init(struct plat_stmmacenet_data *plat)
1633	1868	{
1634	1869	struct rk_priv_data *bsp_priv = plat->bsp_priv;
..	..	@@ -1679,8 +1914,10 @@
1679	1914	bsp_priv->phy_iface == PHY_INTERFACE_MODE_QSGMII) {
1680	1915	bsp_priv->pclk_xpcs = devm_clk_get(dev, "pclk_xpcs");
1681	1916	if (IS_ERR(bsp_priv->pclk_xpcs))
1682		- dev_err(dev, "cannot get clock %s\n",
1683		- "pclk_xpcs");
	1917	+ dev_err(dev, "cannot get clock %s\n", "pclk_xpcs");
	1918	+ bsp_priv->clk_xpcs_eee = devm_clk_get(dev, "clk_xpcs_eee");
	1919	+ if (IS_ERR(bsp_priv->clk_xpcs_eee))
	1920	+ dev_err(dev, "cannot get clock %s\n", "clk_xpcs_eee");
1684	1921	}
1685	1922
1686	1923	bsp_priv->clk_mac_speed = devm_clk_get(dev, "clk_mac_speed");
..	..	@@ -1748,15 +1985,26 @@
1748	1985	if (!IS_ERR(bsp_priv->pclk_xpcs))
1749	1986	clk_prepare_enable(bsp_priv->pclk_xpcs);
1750	1987
	1988	+ if (!IS_ERR(bsp_priv->clk_xpcs_eee))
	1989	+ clk_prepare_enable(bsp_priv->clk_xpcs_eee);
	1990	+
	1991	+ if (bsp_priv->ops && bsp_priv->ops->set_clock_selection)
	1992	+ bsp_priv->ops->set_clock_selection(bsp_priv, bsp_priv->clock_input,
	1993	+ true);
	1994	+
1751	1995	/**
1752	1996	* if (!IS_ERR(bsp_priv->clk_mac))
1753	1997	* clk_prepare_enable(bsp_priv->clk_mac);
1754	1998	*/
1755		- mdelay(5);
	1999	+ usleep_range(100, 200);
1756	2000	bsp_priv->clk_enabled = true;
1757	2001	}
1758	2002	} else {
1759	2003	if (bsp_priv->clk_enabled) {
	2004	+ if (bsp_priv->ops && bsp_priv->ops->set_clock_selection)
	2005	+ bsp_priv->ops->set_clock_selection(bsp_priv, bsp_priv->clock_input,
	2006	+ false);
	2007	+
1760	2008	if (phy_iface == PHY_INTERFACE_MODE_RMII) {
1761	2009	clk_disable_unprepare(bsp_priv->mac_clk_rx);
1762	2010
..	..	@@ -1776,6 +2024,8 @@
1776	2024	clk_disable_unprepare(bsp_priv->clk_mac_speed);
1777	2025
1778	2026	clk_disable_unprepare(bsp_priv->pclk_xpcs);
	2027	+
	2028	+ clk_disable_unprepare(bsp_priv->clk_xpcs_eee);
1779	2029
1780	2030	/**
1781	2031	* if (!IS_ERR(bsp_priv->clk_mac))
..	..	@@ -1853,7 +2103,7 @@
1853	2103
1854	2104	ret = of_property_read_u32(dev->of_node, "tx_delay", &value);
1855	2105	if (ret) {
1856		- bsp_priv->tx_delay = 0x30;
	2106	+ bsp_priv->tx_delay = -1;
1857	2107	dev_err(dev, "Can not read property: tx_delay.");
1858	2108	dev_err(dev, "set tx_delay to 0x%x\n",
1859	2109	bsp_priv->tx_delay);
..	..	@@ -1864,7 +2114,7 @@
1864	2114
1865	2115	ret = of_property_read_u32(dev->of_node, "rx_delay", &value);
1866	2116	if (ret) {
1867		- bsp_priv->rx_delay = 0x10;
	2117	+ bsp_priv->rx_delay = -1;
1868	2118	dev_err(dev, "Can not read property: rx_delay.");
1869	2119	dev_err(dev, "set rx_delay to 0x%x\n",
1870	2120	bsp_priv->rx_delay);
..	..	@@ -1878,24 +2128,45 @@
1878	2128	bsp_priv->xpcs = syscon_regmap_lookup_by_phandle(dev->of_node,
1879	2129	"rockchip,xpcs");
1880	2130	if (!IS_ERR(bsp_priv->xpcs)) {
1881		- struct phy *comphy;
1882		-
1883		- comphy = devm_of_phy_get(&pdev->dev, dev->of_node, NULL);
1884		- if (IS_ERR(comphy))
	2131	+ bsp_priv->comphy = devm_of_phy_get(&pdev->dev, dev->of_node, NULL);
	2132	+ if (IS_ERR(bsp_priv->comphy)) {
	2133	+ bsp_priv->comphy = NULL;
1885	2134	dev_err(dev, "devm_of_phy_get error\n");
1886		- ret = phy_init(comphy);
1887		- if (ret)
1888		- dev_err(dev, "phy_init error\n");
	2135	+ }
1889	2136	}
1890	2137
1891	2138	if (plat->phy_node) {
1892	2139	bsp_priv->integrated_phy = of_property_read_bool(plat->phy_node,
1893	2140	"phy-is-integrated");
1894	2141	if (bsp_priv->integrated_phy) {
	2142	+ unsigned char *efuse_buf;
	2143	+ struct nvmem_cell *cell;
	2144	+ size_t len;
	2145	+
1895	2146	bsp_priv->phy_reset = of_reset_control_get(plat->phy_node, NULL);
1896	2147	if (IS_ERR(bsp_priv->phy_reset)) {
1897	2148	dev_err(&pdev->dev, "No PHY reset control found.\n");
1898	2149	bsp_priv->phy_reset = NULL;
	2150	+ }
	2151	+
	2152	+ /* Read bgs from OTP if it exists */
	2153	+ cell = nvmem_cell_get(dev, "bgs");
	2154	+ if (IS_ERR(cell)) {
	2155	+ if (PTR_ERR(cell) != -EPROBE_DEFER)
	2156	+ dev_info(dev, "failed to get bgs cell: %ld, use default\n",
	2157	+ PTR_ERR(cell));
	2158	+ else
	2159	+ return ERR_CAST(cell);
	2160	+ } else {
	2161	+ efuse_buf = nvmem_cell_read(cell, &len);
	2162	+ nvmem_cell_put(cell);
	2163	+ if (!IS_ERR(efuse_buf)) {
	2164	+ if (len == 1)
	2165	+ bsp_priv->otp_data = efuse_buf[0];
	2166	+ kfree(efuse_buf);
	2167	+ } else {
	2168	+ dev_err(dev, "failed to get efuse buf, use default\n");
	2169	+ }
1899	2170	}
1900	2171	}
1901	2172	}
..	..	@@ -1927,17 +2198,17 @@
1927	2198	case PHY_INTERFACE_MODE_RGMII_ID:
1928	2199	dev_info(dev, "init for RGMII_ID\n");
1929	2200	if (bsp_priv->ops && bsp_priv->ops->set_to_rgmii)
1930		- bsp_priv->ops->set_to_rgmii(bsp_priv, 0, 0);
	2201	+ bsp_priv->ops->set_to_rgmii(bsp_priv, -1, -1);
1931	2202	break;
1932	2203	case PHY_INTERFACE_MODE_RGMII_RXID:
1933	2204	dev_info(dev, "init for RGMII_RXID\n");
1934	2205	if (bsp_priv->ops && bsp_priv->ops->set_to_rgmii)
1935		- bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, 0);
	2206	+ bsp_priv->ops->set_to_rgmii(bsp_priv, bsp_priv->tx_delay, -1);
1936	2207	break;
1937	2208	case PHY_INTERFACE_MODE_RGMII_TXID:
1938	2209	dev_info(dev, "init for RGMII_TXID\n");
1939	2210	if (bsp_priv->ops && bsp_priv->ops->set_to_rgmii)
1940		- bsp_priv->ops->set_to_rgmii(bsp_priv, 0, bsp_priv->rx_delay);
	2211	+ bsp_priv->ops->set_to_rgmii(bsp_priv, -1, bsp_priv->rx_delay);
1941	2212	break;
1942	2213	case PHY_INTERFACE_MODE_RMII:
1943	2214	dev_info(dev, "init for RMII\n");
..	..	@@ -1946,11 +2217,23 @@
1946	2217	break;
1947	2218	case PHY_INTERFACE_MODE_SGMII:
1948	2219	dev_info(dev, "init for SGMII\n");
	2220	+ ret = phy_init(bsp_priv->comphy);
	2221	+ if (ret) {
	2222	+ dev_err(dev, "phy_init error: %d\n", ret);
	2223	+ return ret;
	2224	+ }
	2225	+
1949	2226	if (bsp_priv->ops && bsp_priv->ops->set_to_sgmii)
1950	2227	bsp_priv->ops->set_to_sgmii(bsp_priv);
1951	2228	break;
1952	2229	case PHY_INTERFACE_MODE_QSGMII:
1953	2230	dev_info(dev, "init for QSGMII\n");
	2231	+ ret = phy_init(bsp_priv->comphy);
	2232	+ if (ret) {
	2233	+ dev_err(dev, "phy_init error: %d\n", ret);
	2234	+ return ret;
	2235	+ }
	2236	+
1954	2237	if (bsp_priv->ops && bsp_priv->ops->set_to_qsgmii)
1955	2238	bsp_priv->ops->set_to_qsgmii(bsp_priv);
1956	2239	break;
..	..	@@ -1967,9 +2250,6 @@
1967	2250	pm_runtime_enable(dev);
1968	2251	pm_runtime_get_sync(dev);
1969	2252
1970		- if (bsp_priv->integrated_phy)
1971		- rk_gmac_integrated_phy_powerup(bsp_priv);
1972		-
1973	2253	return 0;
1974	2254	}
1975	2255
..	..	@@ -1977,8 +2257,9 @@
1977	2257	{
1978	2258	struct device *dev = &gmac->pdev->dev;
1979	2259
1980		- if (gmac->integrated_phy)
1981		- rk_gmac_integrated_phy_powerdown(gmac);
	2260	+ if (gmac->phy_iface == PHY_INTERFACE_MODE_SGMII \|\|
	2261	+ gmac->phy_iface == PHY_INTERFACE_MODE_QSGMII)
	2262	+ phy_exit(gmac->comphy);
1982	2263
1983	2264	pm_runtime_put_sync(dev);
1984	2265	pm_runtime_disable(dev);
..	..	@@ -2005,11 +2286,26 @@
2005	2286	bsp_priv->ops->set_rmii_speed(bsp_priv, speed);
2006	2287	break;
2007	2288	case PHY_INTERFACE_MODE_SGMII:
	2289	+ if (bsp_priv->ops && bsp_priv->ops->set_sgmii_speed)
	2290	+ bsp_priv->ops->set_sgmii_speed(bsp_priv, speed);
2008	2291	case PHY_INTERFACE_MODE_QSGMII:
2009	2292	break;
2010	2293	default:
2011	2294	dev_err(dev, "unsupported interface %d", bsp_priv->phy_iface);
2012	2295	}
	2296	+}
	2297	+
	2298	+static int rk_integrated_phy_power(void *priv, bool up)
	2299	+{
	2300	+ struct rk_priv_data *bsp_priv = priv;
	2301	+
	2302	+ if (!bsp_priv->integrated_phy \|\| !bsp_priv->ops \|\|
	2303	+ !bsp_priv->ops->integrated_phy_power)
	2304	+ return 0;
	2305	+
	2306	+ bsp_priv->ops->integrated_phy_power(bsp_priv, up);
	2307	+
	2308	+ return 0;
2013	2309	}
2014	2310
2015	2311	void dwmac_rk_set_rgmii_delayline(struct stmmac_priv *priv,
..	..	@@ -2050,24 +2346,17 @@
2050	2346	{
2051	2347	}
2052	2348
2053		-static unsigned char macaddr[6];
2054		-extern ssize_t at24_mac_read(unsigned char* addr);
2055	2349	void rk_get_eth_addr(void priv, unsigned char addr)
2056	2350	{
2057	2351	struct rk_priv_data *bsp_priv = priv;
2058	2352	struct device *dev = &bsp_priv->pdev->dev;
2059		- int i;
2060		- //unsigned char ethaddr[ETH_ALEN * MAX_ETH] = {0};
2061		- //int ret, id = bsp_priv->bus_id;
	2353	+ unsigned char ethaddr[ETH_ALEN * MAX_ETH] = {0};
	2354	+ int ret, id = bsp_priv->bus_id;
2062	2355
2063		- //ben
2064		- printk("nk-debug:enter rk_get_eth_addr.. \n");
2065		-
2066		- #if 0
2067	2356	rk_devinfo_get_eth_mac(addr);
2068	2357	if (is_valid_ether_addr(addr))
2069	2358	goto out;
2070		-
	2359	+
2071	2360	if (id < 0 \|\| id >= MAX_ETH) {
2072	2361	dev_err(dev, "%s: Invalid ethernet bus id %d\n", __func__, id);
2073	2362	return;
..	..	@@ -2094,35 +2383,7 @@
2094	2383	} else {
2095	2384	memcpy(addr, &ethaddr[id * ETH_ALEN], ETH_ALEN);
2096	2385	}
2097		- #endif
2098		-
2099		- #if 0
2100		- macaddr[0] = 0xee;
2101		- macaddr[1] = 0x31;
2102		- macaddr[2] = 0x32;
2103		- macaddr[3] = 0x33;
2104		- macaddr[4] = 0x34;
2105		- macaddr[5] = 0x35;
2106		-
2107		- memcpy(addr, macaddr, 6);
2108		- #endif
2109		-
2110		- #if 1
2111		- if (at24_mac_read(macaddr) > 0) {
2112		- printk("ben %s: at24_mac_read Success!! \n", __func__);
2113		- memcpy(addr, macaddr, 6);
2114	2386
2115		- printk("Read the Ethernet MAC address from :");
2116		- for (i = 0; i < 5; i++)
2117		- printk("%2.2x:", addr[i]);
2118		-
2119		- printk("%2.2x\n", addr[i]);
2120		- } else {
2121		- printk("ben %s: at24_mac_read Failed!! \n", __func__);
2122		- goto out;
2123		- }
2124		- #endif
2125		-
2126	2387	out:
2127	2388	dev_err(dev, "%s: mac address: %pM\n", __func__, addr);
2128	2389	}
..	..	@@ -2134,7 +2395,6 @@
2134	2395	const struct rk_gmac_ops *data;
2135	2396	int ret;
2136	2397
2137		- printk("nk-debug:enter rk_gmac_probe 1.. \n");
2138	2398	data = of_device_get_match_data(&pdev->dev);
2139	2399	if (!data) {
2140	2400	dev_err(&pdev->dev, "no of match data provided\n");
..	..	@@ -2154,6 +2414,7 @@
2154	2414
2155	2415	plat_dat->fix_mac_speed = rk_fix_speed;
2156	2416	plat_dat->get_eth_addr = rk_get_eth_addr;
	2417	+ plat_dat->integrated_phy_power = rk_integrated_phy_power;
2157	2418
2158	2419	plat_dat->bsp_priv = rk_gmac_setup(pdev, plat_dat, data);
2159	2420	if (IS_ERR(plat_dat->bsp_priv)) {
..	..	@@ -2161,7 +2422,6 @@
2161	2422	goto err_remove_config_dt;
2162	2423	}
2163	2424
2164		- printk("nk-debug:enter rk_gmac_probe 2.. \n");
2165	2425	ret = rk_gmac_clk_init(plat_dat);
2166	2426	if (ret)
2167	2427	goto err_remove_config_dt;
..	..	@@ -2231,19 +2491,48 @@
2231	2491	static SIMPLE_DEV_PM_OPS(rk_gmac_pm_ops, rk_gmac_suspend, rk_gmac_resume);
2232	2492
2233	2493	static const struct of_device_id rk_gmac_dwmac_match[] = {
	2494	+#ifdef CONFIG_CPU_PX30
2234	2495	{ .compatible = "rockchip,px30-gmac", .data = &px30_ops },
	2496	+#endif
	2497	+#ifdef CONFIG_CPU_RK1808
2235	2498	{ .compatible = "rockchip,rk1808-gmac", .data = &rk1808_ops },
	2499	+#endif
	2500	+#ifdef CONFIG_CPU_RK312X
2236	2501	{ .compatible = "rockchip,rk3128-gmac", .data = &rk3128_ops },
	2502	+#endif
	2503	+#ifdef CONFIG_CPU_RK322X
2237	2504	{ .compatible = "rockchip,rk3228-gmac", .data = &rk3228_ops },
	2505	+#endif
	2506	+#ifdef CONFIG_CPU_RK3288
2238	2507	{ .compatible = "rockchip,rk3288-gmac", .data = &rk3288_ops },
	2508	+#endif
	2509	+#ifdef CONFIG_CPU_RK3308
2239	2510	{ .compatible = "rockchip,rk3308-mac", .data = &rk3308_ops },
	2511	+#endif
	2512	+#ifdef CONFIG_CPU_RK3328
2240	2513	{ .compatible = "rockchip,rk3328-gmac", .data = &rk3328_ops },
	2514	+#endif
	2515	+#ifdef CONFIG_CPU_RK3366
2241	2516	{ .compatible = "rockchip,rk3366-gmac", .data = &rk3366_ops },
	2517	+#endif
	2518	+#ifdef CONFIG_CPU_RK3368
2242	2519	{ .compatible = "rockchip,rk3368-gmac", .data = &rk3368_ops },
	2520	+#endif
	2521	+#ifdef CONFIG_CPU_RK3399
2243	2522	{ .compatible = "rockchip,rk3399-gmac", .data = &rk3399_ops },
	2523	+#endif
	2524	+#ifdef CONFIG_CPU_RK3528
	2525	+ { .compatible = "rockchip,rk3528-gmac", .data = &rk3528_ops },
	2526	+#endif
	2527	+#ifdef CONFIG_CPU_RK3568
2244	2528	{ .compatible = "rockchip,rk3568-gmac", .data = &rk3568_ops },
	2529	+#endif
	2530	+#ifdef CONFIG_CPU_RV110X
2245	2531	{ .compatible = "rockchip,rv1108-gmac", .data = &rv1108_ops },
	2532	+#endif
	2533	+#ifdef CONFIG_CPU_RV1126
2246	2534	{ .compatible = "rockchip,rv1126-gmac", .data = &rv1126_ops },
	2535	+#endif
2247	2536	{ }
2248	2537	};
2249	2538	MODULE_DEVICE_TABLE(of, rk_gmac_dwmac_match);
..	..	@@ -2257,8 +2546,7 @@
2257	2546	.of_match_table = rk_gmac_dwmac_match,
2258	2547	},
2259	2548	};
2260		-//module_platform_driver(rk_gmac_dwmac_driver);
2261		- module_platform_driver1(rk_gmac_dwmac_driver);
	2549	+module_platform_driver(rk_gmac_dwmac_driver);
2262	2550
2263	2551	MODULE_AUTHOR("Chen-Zhi (Roger Chen) <roger.chen@rock-chips.com>");
2264	2552	MODULE_DESCRIPTION("Rockchip RK3288 DWMAC specific glue layer");