| .. | .. |
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| 1091 | 1091 | #define RK3568_VP0_DSP_CTRL 0xC00 |
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| 1092 | 1092 | #define RK3568_VP0_MIPI_CTRL 0xC04 |
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| 1093 | 1093 | #define RK3568_VP0_COLOR_BAR_CTRL 0xC08 |
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| 1094 | +#define RK3568_VP0_DCLK_SEL 0xC0C |
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| 1094 | 1095 | #define RK3568_VP0_3D_LUT_CTRL 0xC10 |
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| 1095 | 1096 | #define RK3568_VP0_3D_LUT_MST 0xC20 |
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| 1096 | 1097 | #define RK3568_VP0_DSP_BG 0xC2C |
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| .. | .. |
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| 1110 | 1111 | #define RK3568_VP0_BCSH_BCS 0xC64 |
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| 1111 | 1112 | #define RK3568_VP0_BCSH_H 0xC68 |
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| 1112 | 1113 | #define RK3568_VP0_BCSH_COLOR_BAR 0xC6C |
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| 1114 | +#define RK3528_VP0_ACM_CTRL 0xCD0 |
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| 1115 | +#define RK3528_VP0_CSC_COE01_02 0xCD4 |
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| 1116 | +#define RK3528_VP0_CSC_COE10_11 0xCD8 |
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| 1117 | +#define RK3528_VP0_CSC_COE12_20 0xCDC |
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| 1118 | +#define RK3528_VP0_CSC_COE21_22 0xCE0 |
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| 1119 | +#define RK3528_VP0_CSC_OFFSET0 0xCE4 |
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| 1120 | +#define RK3528_VP0_CSC_OFFSET1 0xCE8 |
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| 1121 | +#define RK3528_VP0_CSC_OFFSET2 0xCEC |
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| 1122 | +#define RK3528_VP0_MCU_CTRL 0xCF8 |
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| 1123 | +#define RK3528_VP0_MCU_RW_BYPASS_PORT 0xCFC |
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| 1113 | 1124 | |
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| 1114 | 1125 | #define RK3568_VP1_DSP_CTRL 0xD00 |
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| 1115 | 1126 | #define RK3568_VP1_MIPI_CTRL 0xD04 |
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| .. | .. |
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| 1133 | 1144 | #define RK3568_VP1_BCSH_BCS 0xD64 |
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| 1134 | 1145 | #define RK3568_VP1_BCSH_H 0xD68 |
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| 1135 | 1146 | #define RK3568_VP1_BCSH_COLOR_BAR 0xD6C |
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| 1147 | +#define RK3528_VP1_MCU_CTRL 0xDF8 |
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| 1148 | +#define RK3528_VP1_MCU_RW_BYPASS_PORT 0xDFC |
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| 1136 | 1149 | |
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| 1137 | 1150 | #define RK3568_VP2_DSP_CTRL 0xE00 |
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| 1138 | 1151 | #define RK3568_VP2_MIPI_CTRL 0xE04 |
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| .. | .. |
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| 1157 | 1170 | #define RK3568_VP2_BCSH_H 0xE68 |
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| 1158 | 1171 | #define RK3568_VP2_BCSH_COLOR_BAR 0xE6C |
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| 1159 | 1172 | |
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| 1160 | | -/* Overlay registers definition */ |
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| 1173 | +#define RK3588_VP3_DSP_CTRL 0xF00 |
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| 1174 | +#define RK3588_VP3_DUAL_CHANNEL_CTRL 0xF04 |
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| 1175 | +#define RK3588_VP3_COLOR_BAR_CTRL 0xF08 |
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| 1176 | +#define RK3568_VP3_CLK_CTRL 0xF0C |
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| 1177 | +#define RK3588_VP3_DSP_BG 0xF2C |
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| 1178 | +#define RK3588_VP3_PRE_SCAN_HTIMING 0xF30 |
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| 1179 | +#define RK3588_VP3_POST_DSP_HACT_INFO 0xF34 |
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| 1180 | +#define RK3588_VP3_POST_DSP_VACT_INFO 0xF38 |
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| 1181 | +#define RK3588_VP3_POST_SCL_FACTOR_YRGB 0xF3C |
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| 1182 | +#define RK3588_VP3_POST_SCL_CTRL 0xF40 |
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| 1183 | +#define RK3588_VP3_DSP_HACT_INFO 0xF34 |
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| 1184 | +#define RK3588_VP3_DSP_VACT_INFO 0xF38 |
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| 1185 | +#define RK3588_VP3_POST_DSP_VACT_INFO_F1 0xF44 |
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| 1186 | +#define RK3588_VP3_DSP_HTOTAL_HS_END 0xF48 |
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| 1187 | +#define RK3588_VP3_DSP_HACT_ST_END 0xF4C |
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| 1188 | +#define RK3588_VP3_DSP_VTOTAL_VS_END 0xF50 |
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| 1189 | +#define RK3588_VP3_DSP_VACT_ST_END 0xF54 |
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| 1190 | +#define RK3588_VP3_DSP_VS_ST_END_F1 0xF58 |
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| 1191 | +#define RK3588_VP3_DSP_VACT_ST_END_F1 0xF5C |
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| 1192 | +#define RK3588_VP3_BCSH_CTRL 0xF60 |
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| 1193 | +#define RK3588_VP3_BCSH_BCS 0xF64 |
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| 1194 | +#define RK3588_VP3_BCSH_H 0xF68 |
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| 1195 | +#define RK3588_VP3_BCSH_COLOR_BAR 0xF6C |
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| 1196 | +#define RK3528_OVL_SYS 0x500 |
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| 1197 | +#define RK3528_OVL_SYS_PORT_SEL_IMD 0x504 |
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| 1198 | +#define RK3528_OVL_SYS_GATING_EN_IMD 0x508 |
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| 1199 | +#define RK3528_OVL_SYS_CLUSTER0_CTRL 0x510 |
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| 1200 | +#define RK3528_OVL_SYS_ESMART0_CTRL 0x520 |
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| 1201 | +#define RK3528_OVL_SYS_ESMART1_CTRL 0x524 |
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| 1202 | +#define RK3528_OVL_SYS_ESMART2_CTRL 0x528 |
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| 1203 | +#define RK3528_OVL_SYS_ESMART3_CTRL 0x52C |
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| 1204 | +#define RK3528_CLUSTER0_MIX_SRC_COLOR_CTRL 0x530 |
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| 1205 | +#define RK3528_CLUSTER0_MIX_DST_COLOR_CTRL 0x534 |
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| 1206 | +#define RK3528_CLUSTER0_MIX_SRC_ALPHA_CTRL 0x538 |
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| 1207 | +#define RK3528_CLUSTER0_MIX_DST_ALPHA_CTRL 0x53c |
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| 1208 | +#define RK3528_OVL_PORT0_CTRL 0x600 |
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| 1209 | +#define RK3528_OVL_PORT0_LAYER_SEL 0x604 |
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| 1210 | +#define RK3528_OVL_PORT0_MIX0_SRC_COLOR_CTRL 0x620 |
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| 1211 | +#define RK3528_OVL_PORT0_MIX0_DST_COLOR_CTRL 0x624 |
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| 1212 | +#define RK3528_OVL_PORT0_MIX0_SRC_ALPHA_CTRL 0x628 |
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| 1213 | +#define RK3528_OVL_PORT0_MIX0_DST_ALPHA_CTRL 0x62C |
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| 1214 | +#define RK3528_OVL_PORT0_MIX1_SRC_COLOR_CTRL 0x630 |
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| 1215 | +#define RK3528_OVL_PORT0_MIX1_DST_COLOR_CTRL 0x634 |
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| 1216 | +#define RK3528_OVL_PORT0_MIX1_SRC_ALPHA_CTRL 0x638 |
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| 1217 | +#define RK3528_OVL_PORT0_MIX1_DST_ALPHA_CTRL 0x63C |
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| 1218 | +#define RK3528_OVL_PORT0_MIX2_SRC_COLOR_CTRL 0x640 |
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| 1219 | +#define RK3528_OVL_PORT0_MIX2_DST_COLOR_CTRL 0x644 |
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| 1220 | +#define RK3528_OVL_PORT0_MIX2_SRC_ALPHA_CTRL 0x648 |
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| 1221 | +#define RK3528_OVL_PORT0_MIX2_DST_ALPHA_CTRL 0x64C |
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| 1222 | +#define RK3528_HDR_SRC_COLOR_CTRL 0x660 |
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| 1223 | +#define RK3528_HDR_DST_COLOR_CTRL 0x664 |
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| 1224 | +#define RK3528_HDR_SRC_ALPHA_CTRL 0x668 |
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| 1225 | +#define RK3528_HDR_DST_ALPHA_CTRL 0x66C |
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| 1226 | +#define RK3528_OVL_PORT0_BG_MIX_CTRL 0x670 |
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| 1227 | +#define RK3528_OVL_PORT1_CTRL 0x700 |
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| 1228 | +#define RK3528_OVL_PORT1_LAYER_SEL 0x704 |
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| 1229 | +#define RK3528_OVL_PORT1_MIX0_SRC_COLOR_CTRL 0x720 |
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| 1230 | +#define RK3528_OVL_PORT1_MIX0_DST_COLOR_CTRL 0x724 |
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| 1231 | +#define RK3528_OVL_PORT1_MIX0_SRC_ALPHA_CTRL 0x728 |
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| 1232 | +#define RK3528_OVL_PORT1_MIX0_DST_ALPHA_CTRL 0x72C |
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| 1233 | +#define RK3528_OVL_PORT1_MIX1_SRC_COLOR_CTRL 0x730 |
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| 1234 | +#define RK3528_OVL_PORT1_MIX1_DST_COLOR_CTRL 0x734 |
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| 1235 | +#define RK3528_OVL_PORT1_MIX1_SRC_ALPHA_CTRL 0x738 |
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| 1236 | +#define RK3528_OVL_PORT1_MIX1_DST_ALPHA_CTRL 0x73C |
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| 1237 | +#define RK3528_OVL_PORT1_MIX2_SRC_COLOR_CTRL 0x740 |
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| 1238 | +#define RK3528_OVL_PORT1_MIX2_DST_COLOR_CTRL 0x744 |
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| 1239 | +#define RK3528_OVL_PORT1_MIX2_SRC_ALPHA_CTRL 0x748 |
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| 1240 | +#define RK3528_OVL_PORT1_MIX2_DST_ALPHA_CTRL 0x74C |
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| 1241 | +#define RK3528_OVL_PORT1_BG_MIX_CTRL 0x770 |
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| 1242 | + |
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| 1161 | 1243 | #define RK3568_OVL_CTRL 0x600 |
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| 1162 | 1244 | #define RK3568_OVL_LAYER_SEL 0x604 |
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| 1163 | 1245 | #define RK3568_OVL_PORT_SEL 0x608 |
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| .. | .. |
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| 1186 | 1268 | /* Cluster0 register definition */ |
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| 1187 | 1269 | #define RK3568_CLUSTER0_WIN0_CTRL0 0x1000 |
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| 1188 | 1270 | #define RK3568_CLUSTER0_WIN0_CTRL1 0x1004 |
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| 1271 | +#define RK3528_CLUSTER0_WIN0_CTRL1 0x1004 |
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| 1272 | +#define RK3528_CLUSTER0_WIN0_CTRL2 0x1008 |
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| 1189 | 1273 | #define RK3568_CLUSTER0_WIN0_YRGB_MST 0x1010 |
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| 1190 | 1274 | #define RK3568_CLUSTER0_WIN0_CBR_MST 0x1014 |
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| 1191 | 1275 | #define RK3568_CLUSTER0_WIN0_VIR 0x1018 |
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| .. | .. |
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| 1205 | 1289 | |
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| 1206 | 1290 | #define RK3568_CLUSTER0_WIN1_CTRL0 0x1080 |
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| 1207 | 1291 | #define RK3568_CLUSTER0_WIN1_CTRL1 0x1084 |
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| 1292 | +#define RK3528_CLUSTER0_WIN1_CTRL1 0x1084 |
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| 1293 | +#define RK3528_CLUSTER0_WIN1_CTRL2 0x1088 |
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| 1208 | 1294 | #define RK3568_CLUSTER0_WIN1_YRGB_MST 0x1090 |
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| 1209 | 1295 | #define RK3568_CLUSTER0_WIN1_CBR_MST 0x1094 |
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| 1210 | 1296 | #define RK3568_CLUSTER0_WIN1_VIR 0x1098 |
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| .. | .. |
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| 1265 | 1351 | /* Esmart register definition */ |
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| 1266 | 1352 | #define RK3568_ESMART0_CTRL0 0x1800 |
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| 1267 | 1353 | #define RK3568_ESMART0_CTRL1 0x1804 |
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| 1354 | +#define RK3568_ESMART0_AXI_CTRL 0x1808 |
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| 1268 | 1355 | #define RK3568_ESMART0_REGION0_CTRL 0x1810 |
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| 1269 | 1356 | #define RK3568_ESMART0_REGION0_YRGB_MST 0x1814 |
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| 1270 | 1357 | #define RK3568_ESMART0_REGION0_CBR_MST 0x1818 |
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| .. | .. |
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| 1466 | 1553 | #define RK3568_HDR_EOTF_OETF_Y0 0x20F0 |
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| 1467 | 1554 | #define RK3568_HDR_OETF_DX_POW1 0x2200 |
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| 1468 | 1555 | #define RK3568_HDR_OETF_XN1 0x2300 |
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| 1556 | + |
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| 1557 | +/* RK3528 HDR register definition */ |
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| 1558 | +#define RK3528_HDR_LUT_CTRL 0x2000 |
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| 1559 | +#define RK3528_HDR_LUT_MST 0x2004 |
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| 1560 | +#define RK3528_HDR_LUT_STATUS 0x2008 |
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| 1561 | +#define RK3528_SDR2HDR_CTRL 0x2010 |
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| 1562 | +#define RK3528_SDR_CFG_COE0 0x2014 |
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| 1563 | +#define RK3528_SDR_CFG_COE1 0x2018 |
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| 1564 | +#define RK3528_SDR_CSC_COE00_01 0x201C |
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| 1565 | +#define RK3528_SDR_CSC_COE02_10 0x2020 |
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| 1566 | +#define RK3528_SDR_CSC_COE11_12 0x2024 |
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| 1567 | +#define RK3528_SDR_CSC_COE20_21 0x2028 |
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| 1568 | +#define RK3528_SDR_CSC_COE22 0x202C |
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| 1569 | +#define RK3528_HDRVIVID_CTRL 0x2040 |
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| 1570 | +#define RK3528_HDR_PQ_GAMMA 0x2044 |
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| 1571 | +#define RK3528_HLG_RFIX_SCALEFAC 0x2048 |
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| 1572 | +#define RK3528_HLG_MAXLUMA 0x204C |
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| 1573 | +#define RK3528_HLG_R_TM_LIN2NON 0x2050 |
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| 1574 | +#define RK3528_HDR_CSC_COE00_01 0x2054 |
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| 1575 | +#define RK3528_HDR_CSC_COE02_10 0x2058 |
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| 1576 | +#define RK3528_HDR_CSC_COE11_12 0x205C |
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| 1577 | +#define RK3528_HDR_CSC_COE20_21 0x2060 |
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| 1578 | +#define RK3528_HDR_CSC_COE22 0x2064 |
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| 1579 | +#define RK3528_INK_CFG 0x2080 |
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| 1580 | +#define RK3528_INK_POINT0_CFG 0x2084 |
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| 1581 | +#define RK3528_INK_POINT1_CFG 0x2088 |
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| 1582 | +#define RK3528_INK_POINT0_R0 0x208C |
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| 1583 | +#define RK3528_INK_POINT0_G0 0x2090 |
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| 1584 | +#define RK3528_INK_POINT0_B0 0x2094 |
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| 1585 | +#define RK3528_INK_POINT0_R1 0x2098 |
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| 1586 | +#define RK3528_INK_POINT0_G1 0x209C |
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| 1587 | +#define RK3528_INK_POINT0_B1 0x20A0 |
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| 1588 | +#define RK3528_INK_POINT1_R0 0x20A4 |
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| 1589 | +#define RK3528_INK_POINT1_G0 0x20A8 |
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| 1590 | +#define RK3528_INK_POINT1_B0 0x20AC |
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| 1591 | +#define RK3528_INK_POINT1_R1 0x20B0 |
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| 1592 | +#define RK3528_INK_POINT1_G1 0x20B4 |
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| 1593 | +#define RK3528_INK_POINT1_B1 0x20B8 |
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| 1594 | +#define RK3528_HDR_TONE_SCA 0x213C |
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| 1595 | +#define RK3528_HDRGAMMA_CURVE 0x2540 |
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| 1596 | +#define RK3528_HDRGAMMA_MDFVALUE 0x2690 |
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| 1597 | +#define RK3528_SDRINVGAMMA_CURVE 0x2700 |
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| 1598 | +#define RK3528_SDRINVGAMMA_STARTIDX 0x2820 |
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| 1599 | +#define RK3528_SDRINVGAMMA_CHANGEIDX 0x2840 |
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| 1600 | +#define RK3528_SDR_SMGAIN 0x2900 |
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| 1601 | + |
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| 1602 | +/* RK3588 ACM register definition */ |
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| 1603 | +#define RK3528_ACM_CTRL 0x0000 |
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| 1604 | +#define RK3528_ACM_ENABLE BIT(0) |
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| 1605 | +#define RK3528_ACM_BYPASS BIT(1) |
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| 1606 | +#define RK3528_ACM_DELTA_RANGE 0x0004 |
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| 1607 | +#define RK3528_ACM_FETCH_START 0x0008 |
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| 1608 | +#define RK3528_ACM_DEBUG_POINT0 0x0010 |
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| 1609 | +#define RK3528_ACM_DEBUG_POINT1 0x0014 |
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| 1610 | +#define RK3528_ACM_DEBUG_POINT2 0x0018 |
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| 1611 | +#define RK3528_ACM_DEBUG_POINT3 0x001c |
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| 1612 | +#define RK3528_ACM_FETCH_DONE 0x0020 |
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| 1613 | +#define RK3528_ACM_DEBUG0_DATA0 0x0030 |
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| 1614 | +#define RK3528_ACM_DEBUG0_DATA1 0x0034 |
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| 1615 | +#define RK3528_ACM_DEBUG0_DATA2 0x0038 |
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| 1616 | +#define RK3528_ACM_DEBUG0_DATA3 0x003c |
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| 1617 | +#define RK3528_ACM_DEBUG1_DATA0 0x0040 |
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| 1618 | +#define RK3528_ACM_DEBUG1_DATA1 0x0044 |
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| 1619 | +#define RK3528_ACM_DEBUG1_DATA2 0x0048 |
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| 1620 | +#define RK3528_ACM_DEBUG1_DATA3 0x004c |
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| 1621 | +#define RK3528_ACM_DEBUG2_DATA0 0x0050 |
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| 1622 | +#define RK3528_ACM_DEBUG2_DATA1 0x0054 |
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| 1623 | +#define RK3528_ACM_DEBUG2_DATA2 0x0058 |
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| 1624 | +#define RK3528_ACM_DEBUG2_DATA3 0x005c |
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| 1625 | +#define RK3528_ACM_DEBUG3_DATA0 0x0060 |
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| 1626 | +#define RK3528_ACM_DEBUG3_DATA1 0x0064 |
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| 1627 | +#define RK3528_ACM_DEBUG3_DATA2 0x0068 |
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| 1628 | +#define RK3528_ACM_DEBUG3_DATA3 0x006c |
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| 1629 | +#define RK3528_ACM_YHS_DEL_HY_SEG0 0x0100 |
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| 1630 | +#define RK3528_ACM_YHS_DEL_HY_SEG152 0x0360 |
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| 1631 | +#define RK3528_ACM_YHS_DEL_HS_SEG0 0x0364 |
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| 1632 | +#define RK3528_ACM_YHS_DEL_HS_SEG220 0x06d4 |
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| 1633 | +#define RK3528_ACM_YHS_DEL_HGAIN_SEG0 0x06d8 |
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| 1634 | +#define RK3528_ACM_YHS_DEL_HGAIN_SEG64 0x07d8 |
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| 1469 | 1635 | #endif /* _ROCKCHIP_VOP_REG_H */ |
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