rk3568 rt init

hc

2023-11-06 e3e12f52b214121840b44c91de5b3e5af5d3eb84

 kernel/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
..
..
@@ -63,6 +63,27 @@
63
63
 	DRM_FORMAT_VYUY,
64
64
 };
65
65
 
66
+static const uint32_t formats_for_esmart[] = {
67
+	DRM_FORMAT_XRGB8888,
68
+	DRM_FORMAT_ARGB8888,
69
+	DRM_FORMAT_XBGR8888,
70
+	DRM_FORMAT_ABGR8888,
71
+	DRM_FORMAT_RGB888,
72
+	DRM_FORMAT_BGR888,
73
+	DRM_FORMAT_RGB565,
74
+	DRM_FORMAT_BGR565,
75
+	DRM_FORMAT_NV12,
76
+	DRM_FORMAT_NV16,
77
+	DRM_FORMAT_NV24,
78
+	DRM_FORMAT_NV12_10,
79
+	DRM_FORMAT_NV16_10,
80
+	DRM_FORMAT_NV24_10,
81
+	DRM_FORMAT_YVYU,
82
+	DRM_FORMAT_VYUY,
83
+	DRM_FORMAT_YUYV,
84
+	DRM_FORMAT_UYVY,
85
+};
86
+
66
87
 static const uint32_t formats_for_smart[] = {
67
88
 	DRM_FORMAT_XRGB8888,
68
89
 	DRM_FORMAT_ARGB8888,
..
..
@@ -120,6 +141,49 @@
120
141
 				AFBC_FORMAT_MOD_YTR |
121
142
 				AFBC_FORMAT_MOD_SPARSE |
122
143
 				AFBC_FORMAT_MOD_SPLIT),
144
+	DRM_FORMAT_MOD_INVALID,
145
+};
146
+
147
+static const uint64_t format_modifiers_afbc_tiled[] = {
148
+	DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16),
149
+
150
+	DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
151
+				AFBC_FORMAT_MOD_SPARSE),
152
+
153
+	DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
154
+				AFBC_FORMAT_MOD_YTR),
155
+
156
+	DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
157
+				AFBC_FORMAT_MOD_CBR),
158
+
159
+	DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
160
+				AFBC_FORMAT_MOD_YTR |
161
+				AFBC_FORMAT_MOD_SPARSE),
162
+
163
+	DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
164
+				AFBC_FORMAT_MOD_CBR |
165
+				AFBC_FORMAT_MOD_SPARSE),
166
+
167
+	DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
168
+				AFBC_FORMAT_MOD_YTR |
169
+				AFBC_FORMAT_MOD_CBR),
170
+
171
+	DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
172
+				AFBC_FORMAT_MOD_YTR |
173
+				AFBC_FORMAT_MOD_CBR |
174
+				AFBC_FORMAT_MOD_SPARSE),
175
+
176
+	/* SPLIT mandates SPARSE, RGB modes mandates YTR */
177
+	DRM_FORMAT_MOD_ARM_AFBC(AFBC_FORMAT_MOD_BLOCK_SIZE_16x16 |
178
+				AFBC_FORMAT_MOD_YTR |
179
+				AFBC_FORMAT_MOD_SPARSE |
180
+				AFBC_FORMAT_MOD_SPLIT),
181
+
182
+	DRM_FORMAT_MOD_ROCKCHIP_TILED(ROCKCHIP_TILED_BLOCK_SIZE_8x8),
183
+	DRM_FORMAT_MOD_ROCKCHIP_TILED(ROCKCHIP_TILED_BLOCK_SIZE_4x4_MODE0),
184
+	DRM_FORMAT_MOD_ROCKCHIP_TILED(ROCKCHIP_TILED_BLOCK_SIZE_4x4_MODE1),
185
+
186
+	DRM_FORMAT_MOD_LINEAR,
123
187
 	DRM_FORMAT_MOD_INVALID,
124
188
 };
125
189
 
..
..
@@ -364,6 +428,16 @@
364
428
 
365
429
 };
366
430
 
431
+static const struct vop_intr rk3528_vop_axi_intr[] = {
432
+	{
433
+	  .intrs = rk3568_vop_axi_intrs,
434
+	  .nintrs = ARRAY_SIZE(rk3568_vop_axi_intrs),
435
+	  .status = VOP_REG(RK3568_SYS0_INT_STATUS, 0xfe, 0),
436
+	  .enable = VOP_REG_MASK(RK3568_SYS0_INT_EN, 0xfe, 0),
437
+	  .clear = VOP_REG_MASK(RK3568_SYS0_INT_CLR, 0xfe, 0),
438
+	},
439
+};
440
+
367
441
 static const struct vop_intr rk3568_vop_axi_intr[] = {
368
442
 	{
369
443
 	  .intrs = rk3568_vop_axi_intrs,
..
..
@@ -444,6 +518,191 @@
444
518
 	.max_output = { 1920, 1080 },
445
519
 	.fifo_depth =  1920 * 4 / 16,
446
520
 	.regs = &rk3568_vop_wb_regs,
521
+};
522
+
523
+static const struct vop2_video_port_regs rk3528_vop_vp0_regs = {
524
+	.cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 0),
525
+	.overlay_mode = VOP_REG(RK3528_OVL_PORT0_CTRL, 0x1, 0),
526
+	.dsp_background = VOP_REG(RK3568_VP0_DSP_BG, 0xffffffff, 0),
527
+	.out_mode = VOP_REG(RK3568_VP0_DSP_CTRL, 0xf, 0),
528
+	.core_dclk_div = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 4),
529
+	.dclk_div2 = VOP_REG(RK3568_VP0_MIPI_CTRL, 0x1, 4),
530
+	.dclk_div2_phase_lock = VOP_REG(RK3568_VP0_MIPI_CTRL, 0x1, 5),
531
+	.p2i_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 5),
532
+	.dsp_filed_pol = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 6),
533
+	.dsp_interlace = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 7),
534
+	.dsp_data_swap = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1f, 8),
535
+	.post_dsp_out_r2y = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 15),
536
+	.pre_dither_down_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 16),
537
+	.dither_down_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 17),
538
+	.dither_down_sel = VOP_REG(RK3568_VP0_DSP_CTRL, 0x3, 18),
539
+	.dither_down_mode = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 20),
540
+	.gamma_update_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 22),
541
+	.dsp_lut_en = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 28),
542
+	.standby = VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 31),
543
+	.bg_mix_ctrl = VOP_REG(RK3528_OVL_PORT0_BG_MIX_CTRL, 0xffff, 0),
544
+	.bg_dly = VOP_REG(RK3528_OVL_PORT0_BG_MIX_CTRL, 0xff, 24),
545
+	.pre_scan_htiming = VOP_REG(RK3568_VP0_PRE_SCAN_HTIMING, 0x1fff1fff, 0),
546
+	.hpost_st_end = VOP_REG(RK3568_VP0_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
547
+	.vpost_st_end = VOP_REG(RK3568_VP0_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
548
+	.post_scl_factor = VOP_REG(RK3568_VP0_POST_SCL_FACTOR_YRGB, 0xffffffff, 0),
549
+	.post_scl_ctrl = VOP_REG(RK3568_VP0_POST_SCL_CTRL, 0x3, 0),
550
+	.htotal_pw = VOP_REG(RK3568_VP0_DSP_HTOTAL_HS_END, 0xffffffff, 0),
551
+	.hact_st_end = VOP_REG(RK3568_VP0_DSP_HACT_ST_END, 0xffffffff, 0),
552
+	.vtotal_pw = VOP_REG(RK3568_VP0_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
553
+	.vact_st_end = VOP_REG(RK3568_VP0_DSP_VACT_ST_END, 0x1fff1fff, 0),
554
+	.vact_st_end_f1 = VOP_REG(RK3568_VP0_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
555
+	.vs_st_end_f1 = VOP_REG(RK3568_VP0_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
556
+	.vpost_st_end_f1 = VOP_REG(RK3568_VP0_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0),
557
+	.lut_dma_rid = VOP_REG(RK3568_SYS_AXI_LUT_CTRL, 0xf, 4),
558
+	.layer_sel = VOP_REG(RK3528_OVL_PORT0_LAYER_SEL, 0xffff, 0),
559
+	.hdr_src_color_ctrl = VOP_REG(RK3528_HDR_SRC_COLOR_CTRL, 0xffffffff, 0),
560
+	.hdr_dst_color_ctrl = VOP_REG(RK3528_HDR_DST_COLOR_CTRL, 0xffffffff, 0),
561
+	.hdr_src_alpha_ctrl = VOP_REG(RK3528_HDR_SRC_ALPHA_CTRL, 0xffffffff, 0),
562
+	.hdr_dst_alpha_ctrl = VOP_REG(RK3528_HDR_DST_ALPHA_CTRL, 0xffffffff, 0),
563
+	.hdr_lut_update_en = VOP_REG(RK3568_HDR_LUT_CTRL, 0x1, 0),
564
+	.hdr_lut_mode = VOP_REG(RK3568_HDR_LUT_CTRL, 0x1, 1),
565
+	.hdr_lut_mst = VOP_REG(RK3568_HDR_LUT_MST, 0xffffffff, 0),
566
+	.hdr_lut_fetch_done = VOP_REG(RK3528_HDR_LUT_STATUS, 0x1, 0),
567
+	.hdr10_en = VOP_REG(RK3568_OVL_CTRL, 0x1, 4),
568
+	.sdr2hdr_path_en = VOP_REG(RK3568_OVL_CTRL, 0x1, 5),
569
+	.sdr2hdr_en = VOP_REG(RK3568_SDR2HDR_CTRL, 0x1, 0),
570
+	.sdr2hdr_auto_gating_en = VOP_REG(RK3568_SDR2HDR_CTRL, 0x1, 1),
571
+	.sdr2hdr_bypass_en = VOP_REG(RK3568_SDR2HDR_CTRL, 0x1, 2),
572
+	.sdr2hdr_dstmode = VOP_REG(RK3568_SDR2HDR_CTRL, 0x1, 3),
573
+	.hdr_vivid_en = VOP_REG(RK3528_HDRVIVID_CTRL, 0x1, 0),
574
+	.hdr_vivid_bypass_en = VOP_REG(RK3528_HDRVIVID_CTRL, 0x1, 2),
575
+	.hdr_vivid_path_mode = VOP_REG(RK3528_HDRVIVID_CTRL, 0x7, 3),
576
+	.hdr_vivid_dstgamut = VOP_REG(RK3528_HDRVIVID_CTRL, 0x1, 6),
577
+	.acm_bypass_en = VOP_REG(RK3528_VP0_ACM_CTRL, 0x1, 0),
578
+	.csc_en = VOP_REG(RK3528_VP0_ACM_CTRL, 0x1, 1),
579
+	.acm_r2y_en = VOP_REG(RK3528_VP0_ACM_CTRL, 0x1, 2),
580
+	.csc_mode = VOP_REG(RK3528_VP0_ACM_CTRL, 0x7, 3),
581
+	.acm_r2y_mode = VOP_REG(RK3528_VP0_ACM_CTRL, 0x7, 8),
582
+	.csc_coe00 = VOP_REG(RK3528_VP0_ACM_CTRL, 0xffff, 16),
583
+	.csc_coe01 = VOP_REG(RK3528_VP0_CSC_COE01_02, 0xffff, 0),
584
+	.csc_coe02 = VOP_REG(RK3528_VP0_CSC_COE01_02, 0xffff, 16),
585
+	.csc_coe10 = VOP_REG(RK3528_VP0_CSC_COE10_11, 0xffff, 0),
586
+	.csc_coe11 = VOP_REG(RK3528_VP0_CSC_COE10_11, 0xffff, 16),
587
+	.csc_coe12 = VOP_REG(RK3528_VP0_CSC_COE12_20, 0xffff, 0),
588
+	.csc_coe20 = VOP_REG(RK3528_VP0_CSC_COE12_20, 0xffff, 16),
589
+	.csc_coe21 = VOP_REG(RK3528_VP0_CSC_COE21_22, 0xffff, 0),
590
+	.csc_coe22 = VOP_REG(RK3528_VP0_CSC_COE21_22, 0xffff, 16),
591
+	.csc_offset0 = VOP_REG(RK3528_VP0_CSC_OFFSET0, 0xffffffff, 0),
592
+	.csc_offset1 = VOP_REG(RK3528_VP0_CSC_OFFSET1, 0xffffffff, 0),
593
+	.csc_offset2 = VOP_REG(RK3528_VP0_CSC_OFFSET2, 0xffffffff, 0),
594
+};
595
+
596
+static const struct vop2_video_port_regs rk3528_vop_vp1_regs = {
597
+	.cfg_done = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 1),
598
+	.overlay_mode = VOP_REG(RK3528_OVL_PORT1_CTRL, 0x1, 0),
599
+	.dsp_background = VOP_REG(RK3568_VP1_DSP_BG, 0xffffffff, 0),
600
+	.out_mode = VOP_REG(RK3568_VP1_DSP_CTRL, 0xf, 0),
601
+	.core_dclk_div = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 4),
602
+	.p2i_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 5),
603
+	.dsp_filed_pol = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 6),
604
+	.dsp_interlace = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 7),
605
+	.dsp_data_swap = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1f, 8),
606
+	.post_dsp_out_r2y = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 15),
607
+	.pre_dither_down_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 16),
608
+	.dither_down_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 17),
609
+	.dither_down_sel = VOP_REG(RK3568_VP1_DSP_CTRL, 0x3, 18),
610
+	.dither_down_mode = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 20),
611
+	.gamma_update_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 22),
612
+	.dsp_lut_en = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 28),
613
+	.standby = VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 31),
614
+	.bg_mix_ctrl = VOP_REG(RK3528_OVL_PORT1_BG_MIX_CTRL, 0xffff, 0),
615
+	.bg_dly = VOP_REG(RK3528_OVL_PORT1_BG_MIX_CTRL, 0xff, 24),
616
+	.pre_scan_htiming = VOP_REG(RK3568_VP1_PRE_SCAN_HTIMING, 0x1fff1fff, 0),
617
+	.hpost_st_end = VOP_REG(RK3568_VP1_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
618
+	.vpost_st_end = VOP_REG(RK3568_VP1_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
619
+	.post_scl_factor = VOP_REG(RK3568_VP1_POST_SCL_FACTOR_YRGB, 0xffffffff, 0),
620
+	.post_scl_ctrl = VOP_REG(RK3568_VP1_POST_SCL_CTRL, 0x3, 0),
621
+	.htotal_pw = VOP_REG(RK3568_VP1_DSP_HTOTAL_HS_END, 0xffffffff, 0),
622
+	.hact_st_end = VOP_REG(RK3568_VP1_DSP_HACT_ST_END, 0xffffffff, 0),
623
+	.vtotal_pw = VOP_REG(RK3568_VP1_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
624
+	.vact_st_end = VOP_REG(RK3568_VP1_DSP_VACT_ST_END, 0x1fff1fff, 0),
625
+	.vact_st_end_f1 = VOP_REG(RK3568_VP1_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
626
+	.vs_st_end_f1 = VOP_REG(RK3568_VP1_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
627
+	.vpost_st_end_f1 = VOP_REG(RK3568_VP1_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0),
628
+	.bcsh_brightness = VOP_REG(RK3568_VP1_BCSH_BCS, 0xff, 0),
629
+	.bcsh_contrast = VOP_REG(RK3568_VP1_BCSH_BCS, 0x1ff, 8),
630
+	.bcsh_sat_con = VOP_REG(RK3568_VP1_BCSH_BCS, 0x3ff, 20),
631
+	.bcsh_out_mode = VOP_REG(RK3568_VP1_BCSH_BCS, 0x3, 30),
632
+	.bcsh_sin_hue = VOP_REG(RK3568_VP1_BCSH_H, 0x1ff, 0),
633
+	.bcsh_cos_hue = VOP_REG(RK3568_VP1_BCSH_H, 0x1ff, 16),
634
+	.bcsh_r2y_csc_mode = VOP_REG(RK3568_VP1_BCSH_CTRL, 0x3, 6),
635
+	.bcsh_r2y_en = VOP_REG(RK3568_VP1_BCSH_CTRL, 0x1, 4),
636
+	.bcsh_y2r_csc_mode = VOP_REG(RK3568_VP1_BCSH_CTRL, 0x3, 2),
637
+	.bcsh_y2r_en = VOP_REG(RK3568_VP1_BCSH_CTRL, 0x1, 0),
638
+	.bcsh_en = VOP_REG(RK3568_VP1_BCSH_COLOR_BAR, 0x1, 31),
639
+	.lut_dma_rid = VOP_REG(RK3568_SYS_AXI_LUT_CTRL, 0xf, 4),
640
+	.layer_sel = VOP_REG(RK3528_OVL_PORT1_LAYER_SEL, 0xffff, 0),
641
+};
642
+
643
+static const struct vop3_ovl_mix_regs rk3528_vop_hdr_mix_regs = {
644
+	.src_color_ctrl = VOP_REG(RK3528_HDR_SRC_COLOR_CTRL, 0xffffffff, 0),
645
+	.dst_color_ctrl = VOP_REG(RK3528_HDR_DST_COLOR_CTRL, 0xffffffff, 0),
646
+	.src_alpha_ctrl = VOP_REG(RK3528_HDR_SRC_ALPHA_CTRL, 0xffffffff, 0),
647
+	.dst_alpha_ctrl = VOP_REG(RK3528_HDR_DST_ALPHA_CTRL, 0xffffffff, 0),
648
+};
649
+
650
+static const struct vop3_ovl_mix_regs rk3528_vop_vp0_layer_mix_regs = {
651
+	.src_color_ctrl = VOP_REG(RK3528_OVL_PORT0_MIX0_SRC_COLOR_CTRL, 0xffffffff, 0),
652
+	.dst_color_ctrl = VOP_REG(RK3528_OVL_PORT0_MIX0_DST_COLOR_CTRL, 0xffffffff, 0),
653
+	.src_alpha_ctrl = VOP_REG(RK3528_OVL_PORT0_MIX0_SRC_ALPHA_CTRL, 0xffffffff, 0),
654
+	.dst_alpha_ctrl = VOP_REG(RK3528_OVL_PORT0_MIX0_DST_ALPHA_CTRL, 0xffffffff, 0),
655
+};
656
+
657
+static const struct vop3_ovl_mix_regs rk3528_vop_vp1_layer_mix_regs = {
658
+	.src_color_ctrl = VOP_REG(RK3528_OVL_PORT1_MIX0_SRC_COLOR_CTRL, 0xffffffff, 0),
659
+	.dst_color_ctrl = VOP_REG(RK3528_OVL_PORT1_MIX0_DST_COLOR_CTRL, 0xffffffff, 0),
660
+	.src_alpha_ctrl = VOP_REG(RK3528_OVL_PORT1_MIX0_SRC_ALPHA_CTRL, 0xffffffff, 0),
661
+	.dst_alpha_ctrl = VOP_REG(RK3528_OVL_PORT1_MIX0_DST_ALPHA_CTRL, 0xffffffff, 0),
662
+};
663
+
664
+static const struct vop3_ovl_regs rk3528_vop_vp0_ovl_regs = {
665
+	.layer_mix_regs = &rk3528_vop_vp0_layer_mix_regs,
666
+	.hdr_mix_regs = &rk3528_vop_hdr_mix_regs,
667
+};
668
+
669
+static const struct vop3_ovl_regs rk3528_vop_vp1_ovl_regs = {
670
+	.layer_mix_regs = &rk3528_vop_vp1_layer_mix_regs,
671
+};
672
+
673
+static const struct vop2_video_port_data rk3528_vop_video_ports[] = {
674
+	{
675
+	 .id = 0,
676
+	 .soc_id = { 0x3528, 0x3528 },
677
+	 .lut_dma_rid = 14,
678
+	 .feature = VOP_FEATURE_ALPHA_SCALE | VOP_FEATURE_OVERSCAN | VOP_FEATURE_VIVID_HDR |
679
+		    VOP_FEATURE_POST_ACM | VOP_FEATURE_POST_CSC | VOP_FEATURE_OUTPUT_10BIT,
680
+	 .gamma_lut_len = 1024,
681
+	 .max_output = { 4096, 4096 },
682
+	 .hdrvivid_dly = {17, 29, 32, 44, 15, 38, 1, 29, 0, 0},
683
+	 .sdr2hdr_dly = 21,
684
+	 .layer_mix_dly = 6,
685
+	 .hdr_mix_dly = 2,
686
+	 .win_dly = 8,
687
+	 .intr = &rk3568_vp0_intr,
688
+	 .regs = &rk3528_vop_vp0_regs,
689
+	 .ovl_regs = &rk3528_vop_vp0_ovl_regs,
690
+	},
691
+	{
692
+	 .id = 1,
693
+	 .soc_id = { 0x3528, 0x3528 },
694
+	 .feature = VOP_FEATURE_ALPHA_SCALE | VOP_FEATURE_OVERSCAN,
695
+	 .max_output = { 720, 576 },
696
+	 .pre_scan_max_dly = { 37, 40, 40, 40 },
697
+	 .hdrvivid_dly = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
698
+	 .sdr2hdr_dly = 0,
699
+	 .layer_mix_dly = 2,
700
+	 .hdr_mix_dly = 0,
701
+	 .win_dly = 8,
702
+	 .intr = &rk3568_vp1_intr,
703
+	 .regs = &rk3528_vop_vp1_regs,
704
+	 .ovl_regs = &rk3528_vop_vp1_ovl_regs,
705
+	},
447
706
 };
448
707
 
449
708
 static const struct vop2_video_port_regs rk3568_vop_vp0_regs = {
..
..
@@ -718,6 +977,18 @@
718
977
 	},
719
978
 };
720
979
 
980
+static const struct vop2_cluster_regs rk3528_vop_cluster0 = {
981
+	 .afbc_enable = VOP_REG(RK3568_CLUSTER0_CTRL, 0x1, 1),
982
+	 .enable = VOP_REG(RK3568_CLUSTER0_CTRL, 1, 0),
983
+	 .lb_mode = VOP_REG(RK3568_CLUSTER0_CTRL, 0xf, 4),
984
+	 .scl_lb_mode = VOP_REG(RK3568_CLUSTER0_CTRL, 0x3, 9),
985
+	 .frm_reset_en = VOP_REG(RK3568_CLUSTER0_CTRL, 1, 31),
986
+	 .src_color_ctrl = VOP_REG(RK3528_CLUSTER0_MIX_SRC_COLOR_CTRL, 0xffffffff, 0),
987
+	 .dst_color_ctrl = VOP_REG(RK3528_CLUSTER0_MIX_DST_COLOR_CTRL, 0xffffffff, 0),
988
+	 .src_alpha_ctrl = VOP_REG(RK3528_CLUSTER0_MIX_SRC_ALPHA_CTRL, 0xffffffff, 0),
989
+	 .dst_alpha_ctrl = VOP_REG(RK3528_CLUSTER0_MIX_DST_ALPHA_CTRL, 0xffffffff, 0),
990
+};
991
+
721
992
 static const struct vop2_cluster_regs rk3568_vop_cluster0 = {
722
993
 	.afbc_enable = VOP_REG(RK3568_CLUSTER0_CTRL, 0x1, 1),
723
994
 	.enable = VOP_REG(RK3568_CLUSTER0_CTRL, 1, 0),
..
..
@@ -758,12 +1029,32 @@
758
1029
 	.ymirror = VOP_REG(RK3568_CLUSTER0_WIN0_AFBCD_ROTATE_MODE, 0x1, 3),
759
1030
 };
760
1031
 
1032
+static const struct vop2_scl_regs rk3528_cluster0_win_scl = {
1033
+	.scale_yrgb_x = VOP_REG(RK3568_CLUSTER0_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
1034
+	.scale_yrgb_y = VOP_REG(RK3568_CLUSTER0_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
1035
+	.yrgb_ver_scl_mode = VOP_REG(RK3528_CLUSTER0_WIN0_CTRL1, 0x3, 14),
1036
+	.yrgb_hor_scl_mode = VOP_REG(RK3528_CLUSTER0_WIN0_CTRL1, 0x3, 22),
1037
+
1038
+	.yrgb_vscl_filter_mode = VOP_REG(RK3528_CLUSTER0_WIN0_CTRL1, 0x3, 12),/* supported from vop3 */
1039
+	.yrgb_hscl_filter_mode = VOP_REG(RK3528_CLUSTER0_WIN0_CTRL1, 0x3, 20),/* supported from vop3 */
1040
+
1041
+	.vsd_yrgb_gt2 = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL1, 0x1, 28),
1042
+	.vsd_yrgb_gt4 = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL1, 0x1, 29),
1043
+	.vsd_cbcr_gt2 = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL1, 0x1, 30),
1044
+	.vsd_cbcr_gt4 = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL1, 0x1, 31),
1045
+
1046
+	.vsd_avg2 = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL1, 0x1, 18),/* supported from vop3 */
1047
+	.vsd_avg4 = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL1, 0x1, 19),
1048
+	.xavg_en = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL1, 0x1, 27),
1049
+	.xgt_en = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL1, 0x1, 24),
1050
+	.xgt_mode = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL1, 0x3, 25),
1051
+};
1052
+
761
1053
 static const struct vop2_scl_regs rk3568_cluster0_win_scl = {
762
1054
 	.scale_yrgb_x = VOP_REG(RK3568_CLUSTER0_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
763
1055
 	.scale_yrgb_y = VOP_REG(RK3568_CLUSTER0_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
764
1056
 	.yrgb_ver_scl_mode = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL1, 0x3, 14),
765
1057
 	.yrgb_hor_scl_mode = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL1, 0x3, 12),
766
-	.bic_coe_sel = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL1, 0x3, 2),
767
1058
 	.vsd_yrgb_gt2 = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL1, 0x1, 28),
768
1059
 	.vsd_yrgb_gt4 = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL1, 0x1, 29),
769
1060
 };
..
..
@@ -817,6 +1108,9 @@
817
1108
 	.vsd_yrgb_gt4 = VOP_REG(RK3568_ESMART0_REGION0_CTRL, 0x1, 9),
818
1109
 	.vsd_cbcr_gt2 = VOP_REG(RK3568_ESMART0_REGION0_CTRL, 0x1, 10),
819
1110
 	.vsd_cbcr_gt4 = VOP_REG(RK3568_ESMART0_REGION0_CTRL, 0x1, 11),
1111
+	.xavg_en = VOP_REG(RK3568_ESMART0_REGION0_CTRL, 0x1, 20),/* supported from vop3 */
1112
+	.xgt_en = VOP_REG(RK3568_ESMART0_REGION0_CTRL, 0x1, 21),
1113
+	.xgt_mode = VOP_REG(RK3568_ESMART0_REGION0_CTRL, 0x3, 22),
820
1114
 };
821
1115
 
822
1116
 static const struct vop2_scl_regs rk3568_area1_scl = {
..
..
@@ -837,6 +1131,9 @@
837
1131
 	.vsd_yrgb_gt4 = VOP_REG(RK3568_ESMART0_REGION1_CTRL, 0x1, 9),
838
1132
 	.vsd_cbcr_gt2 = VOP_REG(RK3568_ESMART0_REGION1_CTRL, 0x1, 10),
839
1133
 	.vsd_cbcr_gt4 = VOP_REG(RK3568_ESMART0_REGION1_CTRL, 0x1, 11),
1134
+	.xavg_en = VOP_REG(RK3568_ESMART0_REGION1_CTRL, 0x1, 20),/* supported from vop3 */
1135
+	.xgt_en = VOP_REG(RK3568_ESMART0_REGION1_CTRL, 0x1, 21),
1136
+	.xgt_mode = VOP_REG(RK3568_ESMART0_REGION1_CTRL, 0x3, 22),
840
1137
 };
841
1138
 
842
1139
 static const struct vop2_scl_regs rk3568_area2_scl = {
..
..
@@ -857,6 +1154,9 @@
857
1154
 	.vsd_yrgb_gt4 = VOP_REG(RK3568_ESMART0_REGION2_CTRL, 0x1, 9),
858
1155
 	.vsd_cbcr_gt2 = VOP_REG(RK3568_ESMART0_REGION2_CTRL, 0x1, 10),
859
1156
 	.vsd_cbcr_gt4 = VOP_REG(RK3568_ESMART0_REGION2_CTRL, 0x1, 11),
1157
+	.xavg_en = VOP_REG(RK3568_ESMART0_REGION2_CTRL, 0x1, 20),/* supported from vop3 */
1158
+	.xgt_en = VOP_REG(RK3568_ESMART0_REGION2_CTRL, 0x1, 21),
1159
+	.xgt_mode = VOP_REG(RK3568_ESMART0_REGION2_CTRL, 0x3, 22),
860
1160
 };
861
1161
 
862
1162
 static const struct vop2_scl_regs rk3568_area3_scl = {
..
..
@@ -877,6 +1177,9 @@
877
1177
 	.vsd_yrgb_gt4 = VOP_REG(RK3568_ESMART0_REGION3_CTRL, 0x1, 9),
878
1178
 	.vsd_cbcr_gt2 = VOP_REG(RK3568_ESMART0_REGION3_CTRL, 0x1, 10),
879
1179
 	.vsd_cbcr_gt4 = VOP_REG(RK3568_ESMART0_REGION3_CTRL, 0x1, 11),
1180
+	.xavg_en = VOP_REG(RK3568_ESMART0_REGION3_CTRL, 0x1, 20),/* supported from vop3 */
1181
+	.xgt_en = VOP_REG(RK3568_ESMART0_REGION3_CTRL, 0x1, 21),
1182
+	.xgt_mode = VOP_REG(RK3568_ESMART0_REGION3_CTRL, 0x3, 22),
880
1183
 };
881
1184
 
882
1185
 static const struct vop2_win_regs rk3568_area1_data = {
..
..
@@ -933,6 +1236,31 @@
933
1236
 	&rk3568_area3_data
934
1237
 };
935
1238
 
1239
+static const struct vop2_win_regs rk3528_cluster0_win_data = {
1240
+	.scl = &rk3528_cluster0_win_scl,
1241
+	.afbc = &rk3568_cluster0_afbc,
1242
+	.cluster = &rk3528_vop_cluster0,
1243
+	.enable = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 0),
1244
+	.format = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x3f, 1),
1245
+	.tile_mode = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 7),
1246
+	.rb_swap = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 14),
1247
+	.uv_swap = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 17),
1248
+	.dither_up = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 18),
1249
+	.act_info = VOP_REG(RK3568_CLUSTER0_WIN0_ACT_INFO, 0x1fff1fff, 0),
1250
+	.dsp_info = VOP_REG(RK3568_CLUSTER0_WIN0_DSP_INFO, 0x0fff0fff, 0),
1251
+	.dsp_st = VOP_REG(RK3568_CLUSTER0_WIN0_DSP_ST, 0x1fff1fff, 0),
1252
+	.yrgb_mst = VOP_REG(RK3568_CLUSTER0_WIN0_YRGB_MST, 0xffffffff, 0),
1253
+	.uv_mst = VOP_REG(RK3568_CLUSTER0_WIN0_CBR_MST, 0xffffffff, 0),
1254
+	.yuv_clip = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 19),
1255
+	.yrgb_vir = VOP_REG(RK3568_CLUSTER0_WIN0_VIR, 0xffff, 0),
1256
+	.uv_vir = VOP_REG(RK3568_CLUSTER0_WIN0_VIR, 0xffff, 16),
1257
+	.y2r_en = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 8),
1258
+	.r2y_en = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 9),
1259
+	.csc_mode = VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x7, 10),
1260
+	.axi_yrgb_id = VOP_REG(RK3528_CLUSTER0_WIN0_CTRL2, 0x1f, 0),
1261
+	.axi_uv_id = VOP_REG(RK3528_CLUSTER0_WIN0_CTRL2, 0x1f, 5),
1262
+};
1263
+
936
1264
 static const struct vop2_win_regs rk3568_cluster0_win_data = {
937
1265
 	.scl = &rk3568_cluster0_win_scl,
938
1266
 	.afbc = &rk3568_cluster0_afbc,
..
..
@@ -977,6 +1305,9 @@
977
1305
 
978
1306
 static const struct vop2_win_regs rk3568_esmart_win_data = {
979
1307
 	.scl = &rk3568_esmart_win_scl,
1308
+	.axi_yrgb_id = VOP_REG(RK3568_ESMART0_CTRL1, 0x1f, 4),
1309
+	.axi_uv_id = VOP_REG(RK3568_ESMART0_CTRL1, 0x1f, 12),
1310
+	.axi_id = VOP_REG(RK3568_ESMART0_AXI_CTRL, 0x1, 1),
980
1311
 	.enable = VOP_REG(RK3568_ESMART0_REGION0_CTRL, 0x1, 0),
981
1312
 	.format = VOP_REG(RK3568_ESMART0_REGION0_CTRL, 0x1f, 1),
982
1313
 	.dither_up = VOP_REG(RK3568_ESMART0_REGION0_CTRL, 0x1, 12),
..
..
@@ -993,9 +1324,204 @@
993
1324
 	.y2r_en = VOP_REG(RK3568_ESMART0_CTRL0, 0x1, 0),
994
1325
 	.r2y_en = VOP_REG(RK3568_ESMART0_CTRL0, 0x1, 1),
995
1326
 	.csc_mode = VOP_REG(RK3568_ESMART0_CTRL0, 0x3, 2),
1327
+	.csc_13bit_en = VOP_REG(RK3568_ESMART0_CTRL0, 0x1, 16),
996
1328
 	.ymirror = VOP_REG(RK3568_ESMART0_CTRL1, 0x1, 31),
997
1329
 	.color_key = VOP_REG(RK3568_ESMART0_COLOR_KEY_CTRL, 0x3fffffff, 0),
998
1330
 	.color_key_en = VOP_REG(RK3568_ESMART0_COLOR_KEY_CTRL, 0x1, 31),
1331
+	.scale_engine_num = VOP_REG(RK3568_ESMART0_CTRL0, 0x3, 12),/* supported from vop3 */
1332
+};
1333
+
1334
+/*
1335
+ * RK3528 VOP with 1 Cluster win and 4 Esmart win.
1336
+ * Every Esmart win support 4 multi-region.
1337
+ * VP0 can use Cluster win and Esmart0/1/2
1338
+ * VP1 can use Esmart 2/3
1339
+ *
1340
+ * Scale filter mode:
1341
+ *
1342
+ * * Cluster:
1343
+ * * Support prescale down:
1344
+ * * H/V: gt2/avg2 or gt4/avg4
1345
+ * * After prescale down:
1346
+ *    * nearest-neighbor/bilinear/bicubic for scale up
1347
+ *    * nearest-neighbor/bilinear for scale down
1348
+ *
1349
+ * * Esmart:
1350
+ * * Support prescale down:
1351
+ * * H: gt2/avg2 or gt4/avg4
1352
+ * * V: gt2 or gt4
1353
+ * * After prescale down:
1354
+ *    * nearest-neighbor/bilinear/bicubic for scale up
1355
+ *    * nearest-neighbor/bilinear/average for scale down
1356
+ */
1357
+static const struct vop2_win_data rk3528_vop_win_data[] = {
1358
+	{
1359
+	  .name = "Esmart0-win0",
1360
+	  .phys_id = ROCKCHIP_VOP2_ESMART0,
1361
+	  .formats = formats_for_esmart,
1362
+	  .nformats = ARRAY_SIZE(formats_for_esmart),
1363
+	  .format_modifiers = format_modifiers,
1364
+	  .base = 0x0,
1365
+	  .layer_sel_id = { 1, 0xff, 0xff, 0xff },
1366
+	  .supported_rotations = DRM_MODE_REFLECT_Y,
1367
+	  .hsu_filter_mode = VOP2_SCALE_UP_BIC,
1368
+	  .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
1369
+	  .vsu_filter_mode = VOP2_SCALE_UP_BIL,
1370
+	  .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
1371
+	  .hsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_AVG,/* gt or avg */
1372
+	  .vsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_GT,/* gt only */
1373
+	  .regs = &rk3568_esmart_win_data,
1374
+	  .area = rk3568_area_data,
1375
+	  .area_size = ARRAY_SIZE(rk3568_area_data),
1376
+	  .type = DRM_PLANE_TYPE_PRIMARY,
1377
+	  .axi_id = 0,
1378
+	  .axi_yrgb_id = 0x06,
1379
+	  .axi_uv_id = 0x07,
1380
+	  .possible_crtcs = 0x1,/* vp0 only */
1381
+	  .max_upscale_factor = 8,
1382
+	  .max_downscale_factor = 8,
1383
+	  .dly = { 27, 45, 48 },
1384
+	  .feature = WIN_FEATURE_MULTI_AREA | WIN_FEATURE_Y2R_13BIT_DEPTH,
1385
+	},
1386
+
1387
+	{
1388
+	  .name = "Esmart1-win0",
1389
+	  .phys_id = ROCKCHIP_VOP2_ESMART1,
1390
+	  .formats = formats_for_esmart,
1391
+	  .nformats = ARRAY_SIZE(formats_for_esmart),
1392
+	  .format_modifiers = format_modifiers,
1393
+	  .base = 0x200,
1394
+	  .layer_sel_id = { 2, 0xff, 0xff, 0xff },
1395
+	  .supported_rotations = DRM_MODE_REFLECT_Y,
1396
+	  .hsu_filter_mode = VOP2_SCALE_UP_BIC,
1397
+	  .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
1398
+	  .vsu_filter_mode = VOP2_SCALE_UP_BIL,
1399
+	  .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
1400
+	  .hsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_AVG,/* gt or avg */
1401
+	  .vsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_GT,/* gt only */
1402
+	  .regs = &rk3568_esmart_win_data,
1403
+	  .area = rk3568_area_data,
1404
+	  .area_size = ARRAY_SIZE(rk3568_area_data),
1405
+	  .type = DRM_PLANE_TYPE_OVERLAY,
1406
+	  .axi_id = 0,
1407
+	  .axi_yrgb_id = 0x08,
1408
+	  .axi_uv_id = 0x09,
1409
+	  .possible_crtcs = 0x1,/* vp0 only */
1410
+	  .max_upscale_factor = 8,
1411
+	  .max_downscale_factor = 8,
1412
+	  .dly = { 27, 45, 48 },
1413
+	  .feature = WIN_FEATURE_MULTI_AREA,
1414
+	},
1415
+
1416
+	{
1417
+	  .name = "Esmart2-win0",
1418
+	  .phys_id = ROCKCHIP_VOP2_ESMART2,
1419
+	  .base = 0x400,
1420
+	  .formats = formats_for_esmart,
1421
+	  .nformats = ARRAY_SIZE(formats_for_esmart),
1422
+	  .format_modifiers = format_modifiers,
1423
+	  .layer_sel_id = { 3, 0, 0xff, 0xff },
1424
+	  .supported_rotations = DRM_MODE_REFLECT_Y,
1425
+	  .hsu_filter_mode = VOP2_SCALE_UP_BIC,
1426
+	  .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
1427
+	  .vsu_filter_mode = VOP2_SCALE_UP_BIL,
1428
+	  .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
1429
+	  .hsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_AVG,/* gt or avg */
1430
+	  .vsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_GT,/* gt only */
1431
+	  .regs = &rk3568_esmart_win_data,
1432
+	  .area = rk3568_area_data,
1433
+	  .area_size = ARRAY_SIZE(rk3568_area_data),
1434
+	  .type = DRM_PLANE_TYPE_CURSOR,
1435
+	  .axi_id = 0,
1436
+	  .axi_yrgb_id = 0x0a,
1437
+	  .axi_uv_id = 0x0b,
1438
+	  .possible_crtcs = 0x3,/* vp0 or vp1 */
1439
+	  .max_upscale_factor = 8,
1440
+	  .max_downscale_factor = 8,
1441
+	  .dly = { 27, 45, 48 },
1442
+	  .feature = WIN_FEATURE_MULTI_AREA,
1443
+	},
1444
+
1445
+	{
1446
+	  .name = "Esmart3-win0",
1447
+	  .phys_id = ROCKCHIP_VOP2_ESMART3,
1448
+	  .formats = formats_for_esmart,
1449
+	  .nformats = ARRAY_SIZE(formats_for_esmart),
1450
+	  .format_modifiers = format_modifiers,
1451
+	  .base = 0x600,
1452
+	  .layer_sel_id = { 0xff, 1, 0xff, 0xff },
1453
+	  .supported_rotations = DRM_MODE_REFLECT_Y,
1454
+	  .hsu_filter_mode = VOP2_SCALE_UP_BIC,
1455
+	  .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
1456
+	  .vsu_filter_mode = VOP2_SCALE_UP_BIL,
1457
+	  .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
1458
+	  .hsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_AVG,/* gt or avg */
1459
+	  .vsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_GT,/* gt only */
1460
+	  .regs = &rk3568_esmart_win_data,
1461
+	  .area = rk3568_area_data,
1462
+	  .area_size = ARRAY_SIZE(rk3568_area_data),
1463
+	  .type = DRM_PLANE_TYPE_PRIMARY,
1464
+	  .axi_id = 0,
1465
+	  .axi_yrgb_id = 0x0c,
1466
+	  .axi_uv_id = 0x0d,
1467
+	  .possible_crtcs = 0x2,/* vp1 only */
1468
+	  .max_upscale_factor = 8,
1469
+	  .max_downscale_factor = 8,
1470
+	  .dly = { 27, 45, 48 },
1471
+	  .feature = WIN_FEATURE_MULTI_AREA,
1472
+	},
1473
+
1474
+	{
1475
+	  .name = "Cluster0-win0",
1476
+	  .phys_id = ROCKCHIP_VOP2_CLUSTER0,
1477
+	  .base = 0x00,
1478
+	  .formats = formats_for_cluster,
1479
+	  .nformats = ARRAY_SIZE(formats_for_cluster),
1480
+	  .format_modifiers = format_modifiers_afbc_tiled,
1481
+	  .layer_sel_id = { 0, 0xff, 0xff, 0xff },
1482
+	  .supported_rotations = DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270 |
1483
+			   DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y,
1484
+	  .hsu_filter_mode = VOP2_SCALE_UP_BIC,
1485
+	  .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
1486
+	  .vsu_filter_mode = VOP2_SCALE_UP_BIL,
1487
+	  .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
1488
+	  .hsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_AVG,/* gt or avg */
1489
+	  .vsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_AVG,/* gt or avg */
1490
+	  .regs = &rk3528_cluster0_win_data,
1491
+	  .axi_yrgb_id = 0x02,
1492
+	  .axi_uv_id = 0x03,
1493
+	  .possible_crtcs = 0x1,/* vp0 only */
1494
+	  .max_upscale_factor = 8,
1495
+	  .max_downscale_factor = 8,
1496
+	  .dly = { 27, 27, 21 },
1497
+	  .type = DRM_PLANE_TYPE_OVERLAY,
1498
+	  .feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER_MAIN | WIN_FEATURE_Y2R_13BIT_DEPTH,
1499
+	},
1500
+
1501
+	{
1502
+	  .name = "Cluster0-win1",
1503
+	  .phys_id = ROCKCHIP_VOP2_CLUSTER0,
1504
+	  .base = 0x80,
1505
+	  .layer_sel_id = { 0, 0xff, 0xff, 0xff },
1506
+	  .formats = formats_for_cluster,
1507
+	  .nformats = ARRAY_SIZE(formats_for_cluster),
1508
+	  .format_modifiers = format_modifiers_afbc_tiled,
1509
+	  .supported_rotations = DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y,
1510
+	  .hsu_filter_mode = VOP2_SCALE_UP_BIC,
1511
+	  .hsd_filter_mode = VOP2_SCALE_DOWN_BIL,
1512
+	  .vsu_filter_mode = VOP2_SCALE_UP_BIL,
1513
+	  .vsd_filter_mode = VOP2_SCALE_DOWN_BIL,
1514
+	  .hsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_AVG,/* gt or avg */
1515
+	  .vsd_pre_filter_mode = VOP3_PRE_SCALE_DOWN_AVG,/* gt or avg */
1516
+	  .regs = &rk3528_cluster0_win_data,
1517
+	  .axi_yrgb_id = 0x04,
1518
+	  .axi_uv_id = 0x05,
1519
+	  .possible_crtcs = 0x1,/* vp0 only */
1520
+	  .max_upscale_factor = 8,
1521
+	  .max_downscale_factor = 8,
1522
+	  .type = DRM_PLANE_TYPE_OVERLAY,
1523
+	  .feature = WIN_FEATURE_AFBDC | WIN_FEATURE_CLUSTER_SUB,
1524
+	},
999
1525
 };
1000
1526
 
1001
1527
 /*
..
..
@@ -1193,6 +1719,37 @@
1193
1719
 	},
1194
1720
 };
1195
1721
 
1722
+static const struct vop2_ctrl rk3528_vop_ctrl = {
1723
+	.cfg_done_en = VOP_REG(RK3568_REG_CFG_DONE, 0x1, 15),
1724
+	.wb_cfg_done = VOP_REG_MASK(RK3568_REG_CFG_DONE, 0x1, 14),
1725
+	.auto_gating_en = VOP_REG(RK3568_SYS_AUTO_GATING_CTRL, 0x1, 31),
1726
+	.aclk_pre_auto_gating_en = VOP_REG(RK3568_SYS_AUTO_GATING_CTRL, 0x1, 7),
1727
+	.if_ctrl_cfg_done_imd = VOP_REG(RK3568_DSP_IF_POL, 0x1, 28),
1728
+	.version = VOP_REG(RK3568_VERSION_INFO, 0xffff, 16),
1729
+	.lut_dma_en = VOP_REG(RK3568_SYS_AXI_LUT_CTRL, 0x1, 0),
1730
+	.dsp_vs_t_sel = VOP_REG(RK3568_SYS_AXI_LUT_CTRL, 0x1, 16),
1731
+	.rgb_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 0),
1732
+	.hdmi0_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 1),
1733
+	.bt656_en = VOP_REG(RK3568_DSP_IF_EN, 0x1, 7),
1734
+	.rgb_mux = VOP_REG(RK3568_DSP_IF_EN, 0x3, 8),
1735
+	.hdmi0_mux = VOP_REG(RK3568_DSP_IF_EN, 0x3, 10),
1736
+	.bt656_yc_swap = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 5),
1737
+	.bt656_dclk_pol = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 6),
1738
+	.hdmi_pin_pol = VOP_REG(RK3568_DSP_IF_POL, 0x7, 4),
1739
+	.hdmi_dclk_pol = VOP_REG(RK3568_DSP_IF_POL, 0x1, 7),
1740
+	.esmart_lb_mode = VOP_REG(RK3568_LUT_PORT_SEL, 0x3, 26),
1741
+	.win_vp_id[ROCKCHIP_VOP2_CLUSTER0] = VOP_REG(RK3528_OVL_SYS_PORT_SEL_IMD, 0x3, 0),
1742
+	.win_vp_id[ROCKCHIP_VOP2_ESMART0] = VOP_REG(RK3528_OVL_SYS_PORT_SEL_IMD, 0x3, 16),
1743
+	.win_vp_id[ROCKCHIP_VOP2_ESMART1] = VOP_REG(RK3528_OVL_SYS_PORT_SEL_IMD, 0x3, 20),
1744
+	.win_vp_id[ROCKCHIP_VOP2_ESMART2] = VOP_REG(RK3528_OVL_SYS_PORT_SEL_IMD, 0x3, 24),
1745
+	.win_vp_id[ROCKCHIP_VOP2_ESMART3] = VOP_REG(RK3528_OVL_SYS_PORT_SEL_IMD, 0x3, 28),
1746
+	.win_dly[ROCKCHIP_VOP2_CLUSTER0] = VOP_REG(RK3528_OVL_SYS_CLUSTER0_CTRL, 0xffff, 0),
1747
+	.win_dly[ROCKCHIP_VOP2_ESMART0] = VOP_REG(RK3528_OVL_SYS_ESMART0_CTRL, 0xff, 0),
1748
+	.win_dly[ROCKCHIP_VOP2_ESMART1] = VOP_REG(RK3528_OVL_SYS_ESMART1_CTRL, 0xff, 0),
1749
+	.win_dly[ROCKCHIP_VOP2_ESMART2] = VOP_REG(RK3528_OVL_SYS_ESMART2_CTRL, 0xff, 0),
1750
+	.win_dly[ROCKCHIP_VOP2_ESMART3] = VOP_REG(RK3528_OVL_SYS_ESMART3_CTRL, 0xff, 0),
1751
+};
1752
+
1196
1753
 static const struct vop_grf_ctrl rk3568_grf_ctrl = {
1197
1754
 	.grf_bt656_clk_inv = VOP_REG(RK3568_GRF_VO_CON1, 0x1, 1),
1198
1755
 	.grf_bt1120_clk_inv = VOP_REG(RK3568_GRF_VO_CON1, 0x1, 2),
..
..
@@ -1235,6 +1792,7 @@
1235
1792
 	.bt656_yc_swap = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 5),
1236
1793
 	.bt1120_yc_swap = VOP_REG(RK3568_DSP_IF_CTRL, 0x1, 9),
1237
1794
 	.gamma_port_sel = VOP_REG(RK3568_LUT_PORT_SEL, 0x3, 0),
1795
+	.rgb_pin_pol = VOP_REG(RK3568_DSP_IF_POL, 0x7, 0),
1238
1796
 	.lvds_pin_pol = VOP_REG(RK3568_DSP_IF_POL, 0x7, 0),
1239
1797
 	.lvds_dclk_pol = VOP_REG(RK3568_DSP_IF_POL, 0x1, 3),
1240
1798
 	.hdmi_pin_pol = VOP_REG(RK3568_DSP_IF_POL, 0x7, 4),
..
..
@@ -1258,6 +1816,20 @@
1258
1816
 	.otp_en = VOP_REG(RK3568_OTP_WIN_EN, 0x1, 0),
1259
1817
 };
1260
1818
 
1819
+static const struct vop_dump_regs rk3528_dump_regs[] = {
1820
+	{ RK3568_REG_CFG_DONE, "SYS", {0}, 0 },
1821
+	{ RK3528_OVL_SYS, "OVL_SYS", {0}, 0 },
1822
+	{ RK3528_OVL_PORT0_CTRL, "OVL_VP0", VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 31), 0 },
1823
+	{ RK3528_OVL_PORT1_CTRL, "OVL_VP1", VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 31), 0 },
1824
+	{ RK3568_VP0_DSP_CTRL, "VP0", VOP_REG(RK3568_VP0_DSP_CTRL, 0x1, 31), 0 },
1825
+	{ RK3568_VP1_DSP_CTRL, "VP1", VOP_REG(RK3568_VP1_DSP_CTRL, 0x1, 31), 0 },
1826
+	{ RK3568_CLUSTER0_WIN0_CTRL0, "Cluster0", VOP_REG(RK3568_CLUSTER0_WIN0_CTRL0, 0x1, 0), 1 },
1827
+	{ RK3568_ESMART0_CTRL0, "Esmart0", VOP_REG(RK3568_ESMART0_REGION0_CTRL, 0x1, 0), 1 },
1828
+	{ RK3568_ESMART1_CTRL0, "Esmart1", VOP_REG(RK3568_ESMART1_REGION0_CTRL, 0x1, 0), 1 },
1829
+	{ RK3568_SMART0_CTRL0, "Esmart2", VOP_REG(RK3568_SMART0_CTRL0, 0x1, 0), 1 },
1830
+	{ RK3568_SMART1_CTRL0, "Esmart3", VOP_REG(RK3568_SMART1_CTRL0, 0x1, 0), 1 },
1831
+};
1832
+
1261
1833
 static const struct vop_dump_regs rk3568_dump_regs[] = {
1262
1834
 	{ RK3568_REG_CFG_DONE, "SYS", {0}, 0 },
1263
1835
 	{ RK3568_OVL_CTRL, "OVL", {0}, 0 },
..
..
@@ -1271,6 +1843,26 @@
1271
1843
 	{ RK3568_SMART0_CTRL0, "Smart0", VOP_REG(RK3568_SMART0_REGION0_CTRL, 0x1, 0), 1 },
1272
1844
 	{ RK3568_SMART1_CTRL0, "Smart1", VOP_REG(RK3568_SMART1_REGION0_CTRL, 0x1, 0), 1 },
1273
1845
 	{ RK3568_HDR_LUT_CTRL, "HDR", VOP_REG(RK3568_OVL_CTRL, 0x1, 4), 1 },
1846
+};
1847
+
1848
+static const struct vop2_data rk3528_vop = {
1849
+	.version = VOP_VERSION_RK3528,
1850
+	.nr_vps = 2,
1851
+	.nr_mixers = 3,
1852
+	.nr_layers = 4,
1853
+	.nr_gammas = 2,
1854
+	.esmart_lb_mode = VOP3_ESMART_4K_2K_2K_MODE,
1855
+	.max_input = { 4096, 4096 },
1856
+	.max_output = { 4096, 4096 },
1857
+	.ctrl = &rk3528_vop_ctrl,
1858
+	.axi_intr = rk3528_vop_axi_intr,
1859
+	.nr_axi_intr = ARRAY_SIZE(rk3528_vop_axi_intr),
1860
+	.vp = rk3528_vop_video_ports,
1861
+	.wb = &rk3568_vop_wb_data,
1862
+	.win = rk3528_vop_win_data,
1863
+	.win_size = ARRAY_SIZE(rk3528_vop_win_data),
1864
+	.dump_regs = rk3528_dump_regs,
1865
+	.dump_regs_size = ARRAY_SIZE(rk3528_dump_regs),
1274
1866
 };
1275
1867
 
1276
1868
 static const struct vop2_data rk3568_vop = {
..
..
@@ -1295,6 +1887,8 @@
1295
1887
 };
1296
1888
 
1297
1889
 static const struct of_device_id vop2_dt_match[] = {
1890
+	{ .compatible = "rockchip,rk3528-vop",
1891
+	  .data = &rk3528_vop },
1298
1892
 	{ .compatible = "rockchip,rk3568-vop",
1299
1893
 	  .data = &rk3568_vop },
1300
1894
 	{},