rk3568 rt init

hc

2023-11-06 e3e12f52b214121840b44c91de5b3e5af5d3eb84

 kernel/drivers/gpu/drm/rockchip/rockchip_drm_vop.h
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@@ -24,6 +24,7 @@
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 #define VOP_MAJOR(version)		((version) >> 8)
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 #define VOP_MINOR(version)		((version) & 0xff)
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26
 
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+#define VOP_VERSION_RK3528	VOP_VERSION(0x50, 0x17)
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 #define VOP_VERSION_RK3568	VOP_VERSION(0x40, 0x15)
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 #define VOP_VERSION_RK3588	VOP_VERSION(0x40, 0x17)
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@@ -42,6 +43,9 @@
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 /* a feature to splice two windows and two vps to support resolution > 4096 */
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 #define VOP_FEATURE_SPLICE		BIT(5)
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 #define VOP_FEATURE_OVERSCAN		BIT(6)
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+#define VOP_FEATURE_VIVID_HDR		BIT(7)
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+#define VOP_FEATURE_POST_ACM		BIT(8)
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+#define VOP_FEATURE_POST_CSC		BIT(9)
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49
 
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 #define WIN_FEATURE_HDR2SDR		BIT(0)
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 #define WIN_FEATURE_SDR2HDR		BIT(1)
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@@ -92,10 +96,10 @@
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 };
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 enum vop3_esmart_lb_mode {
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-	VOP3_ESMART_ONE_8K_MODE,
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-	VOP3_ESMART_TWO_4K_MODE,
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-	VOP3_ESMART_ONE_4K_AND_TWO_2K_MODE,
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-	VOP3_ESMART_FOUR_2K_MODE,
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+	VOP3_ESMART_8K_MODE,
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+	VOP3_ESMART_4K_4K_MODE,
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+	VOP3_ESMART_4K_2K_2K_MODE,
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+	VOP3_ESMART_2K_2K_2K_2K_MODE,
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 };
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 #define DSP_BG_SWAP		0x1
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@@ -439,6 +443,104 @@
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 	const uint32_t *sdr2hdr_st2084oetf_xn;
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 };
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445
 
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+#define RK_HDRVIVID_TONE_SCA_TAB_LENGTH		257
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+#define RK_HDRVIVID_GAMMA_CURVE_LENGTH		81
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+#define RK_HDRVIVID_GAMMA_MDFVALUE_LENGTH	9
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+#define RK_SDR2HDR_INVGAMMA_CURVE_LENGTH	69
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+#define RK_SDR2HDR_INVGAMMA_S_IDX_LENGTH	6
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+#define RK_SDR2HDR_INVGAMMA_C_IDX_LENGTH	6
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+#define RK_SDR2HDR_SMGAIN_LENGTH		64
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+#define RK_HDRVIVID_TONE_SCA_AXI_TAB_LENGTH	264
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+
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+struct hdrvivid_regs {
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+	uint32_t sdr2hdr_ctrl;
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+	uint32_t sdr2hdr_coe0;
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+	uint32_t sdr2hdr_coe1;
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+	uint32_t sdr2hdr_csc_coe00_01;
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+	uint32_t sdr2hdr_csc_coe02_10;
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+	uint32_t sdr2hdr_csc_coe11_12;
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+	uint32_t sdr2hdr_csc_coe20_21;
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+	uint32_t sdr2hdr_csc_coe22;
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+	uint32_t hdrvivid_ctrl;
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+	uint32_t hdr_pq_gamma;
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+	uint32_t hlg_rfix_scalefac;
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+	uint32_t hlg_maxluma;
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+	uint32_t hlg_r_tm_lin2non;
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+	uint32_t hdr_csc_coe00_01;
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+	uint32_t hdr_csc_coe02_10;
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+	uint32_t hdr_csc_coe11_12;
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+	uint32_t hdr_csc_coe20_21;
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+	uint32_t hdr_csc_coe22;
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+	uint32_t hdr_tone_sca[RK_HDRVIVID_TONE_SCA_TAB_LENGTH];
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+	uint32_t hdrgamma_curve[RK_HDRVIVID_GAMMA_CURVE_LENGTH];
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+	uint32_t hdrgamma_mdfvalue[RK_HDRVIVID_GAMMA_MDFVALUE_LENGTH];
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+	uint32_t sdrinvgamma_curve[RK_SDR2HDR_INVGAMMA_CURVE_LENGTH];
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+	uint32_t sdrinvgamma_startidx[RK_SDR2HDR_INVGAMMA_S_IDX_LENGTH];
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+	uint32_t sdrinvgamma_changeidx[RK_SDR2HDR_INVGAMMA_C_IDX_LENGTH];
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+	uint32_t sdr_smgain[RK_SDR2HDR_SMGAIN_LENGTH];
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+	uint32_t hdr_mode;
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+	uint32_t tone_sca_axi_tab[RK_HDRVIVID_TONE_SCA_AXI_TAB_LENGTH];
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+};
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+
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+struct hdr_extend {
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+	uint32_t hdr_type;
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+	uint32_t length;
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+	union {
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+		struct hdrvivid_regs hdrvivid_data;
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+	};
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+};
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+
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+enum _vop_hdrvivid_mode {
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+	PQHDR2HDR_WITH_DYNAMIC = 0,
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+	PQHDR2SDR_WITH_DYNAMIC,
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+	HLG2PQHDR_WITH_DYNAMIC,
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+	HLG2SDR_WITH_DYNAMIC,
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+	HLG2PQHDR_WITHOUT_DYNAMIC,
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+	HLG2SDR_WITHOUT_DYNAMIC,
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+	HDR_BYPASS,
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+	HDR102SDR,
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+	SDR2HDR10,
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+	SDR2HLG,
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+	SDR2HDR10_USERSPACE = 100,
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+	SDR2HLG_USERSPACE = 101,
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+};
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+
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+enum vop_hdr_format {
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+	HDR_NONE = 0,
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+	HDR_HDR10 = 1,
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+	HDR_HLGSTATIC = 2,
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+	RESERVED3 = 3,		/* reserved for more future static hdr format */
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+	RESERVED4 = 4,		/* reserved for more future static hdr format */
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+	HDR_HDRVIVID = 5,
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+	RESERVED6 = 6,		/* reserved for hdr vivid */
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+	RESERVED7 = 7,		/* reserved for hdr vivid */
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+	HDR_HDR10PLUS = 8,
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+	RESERVED9 = 9,		/* reserved for hdr hdr10+ */
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+	RESERVED10 = 10,	/* reserved for hdr hdr10+ */
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+	HDR_NEXT = 11,
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+	RESERVED12 = 12,	/* reserved for other dynamic hdr format */
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+	RESERVED13 = 13,	/* reserved for other dynamic hdr format */
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+	HDR_FORMAT_MAX,
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+};
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+
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+struct post_csc_coef {
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+	s32 csc_coef00;
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+	s32 csc_coef01;
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+	s32 csc_coef02;
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+	s32 csc_coef10;
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+	s32 csc_coef11;
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+	s32 csc_coef12;
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+	s32 csc_coef20;
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+	s32 csc_coef21;
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+	s32 csc_coef22;
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+
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+	s32 csc_dc0;
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+	s32 csc_dc1;
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+	s32 csc_dc2;
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+
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+	u32 range_type;
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+};
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+
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 enum {
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 	VOP_CSC_Y2R_BT601,
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 	VOP_CSC_Y2R_BT709,
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@@ -509,6 +611,8 @@
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 	struct vop_reg enable;
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 	struct vop_reg afbc_enable;
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 	struct vop_reg lb_mode;
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+	struct vop_reg scl_lb_mode;
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+	struct vop_reg frm_reset_en;
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 	struct vop_reg src_color_ctrl;
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 	struct vop_reg dst_color_ctrl;
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@@ -626,6 +730,13 @@
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 	struct vop_reg hdr_lut_update_en;
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 	struct vop_reg hdr_lut_mode;
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 	struct vop_reg hdr_lut_mst;
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+	struct vop_reg hdr_lut_fetch_done;
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+	struct vop_reg hdr_vivid_en;
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+	struct vop_reg hdr_vivid_bypass_en;
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+	struct vop_reg hdr_vivid_path_mode;
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+	struct vop_reg hdr_vivid_dstgamut;
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+	struct vop_reg sdr2hdr_en;
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+	struct vop_reg sdr2hdr_dstmode;
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 	struct vop_reg sdr2hdr_eotf_en;
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 	struct vop_reg sdr2hdr_r2r_en;
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 	struct vop_reg sdr2hdr_r2r_mode;
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@@ -677,6 +788,25 @@
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 	struct vop_reg edpi_wms_fs;
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 	struct vop_reg gamma_update_en;
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 	struct vop_reg lut_dma_rid;
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+
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+	/* CSC */
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+	struct vop_reg acm_bypass_en;
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+	struct vop_reg csc_en;
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+	struct vop_reg acm_r2y_en;
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+	struct vop_reg csc_mode;
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+	struct vop_reg acm_r2y_mode;
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+	struct vop_reg csc_coe00;
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+	struct vop_reg csc_coe01;
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+	struct vop_reg csc_coe02;
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+	struct vop_reg csc_coe10;
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+	struct vop_reg csc_coe11;
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+	struct vop_reg csc_coe12;
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+	struct vop_reg csc_coe20;
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+	struct vop_reg csc_coe21;
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+	struct vop_reg csc_coe22;
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+	struct vop_reg csc_offset0;
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+	struct vop_reg csc_offset1;
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+	struct vop_reg csc_offset2;
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 };
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811
 
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 struct vop2_wb_regs {
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@@ -711,7 +841,6 @@
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 	uint8_t axi_id;
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 	uint8_t axi_yrgb_id;
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 	uint8_t axi_uv_id;
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-	uint8_t scale_engine_num;
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 	uint8_t possible_crtcs;
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 	uint32_t base;
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@@ -775,6 +904,11 @@
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 	uint16_t cubic_lut_len;
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 	struct vop_rect max_output;
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 	const u8 pre_scan_max_dly[4];
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+	const u8 hdrvivid_dly[10];
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+	const u8 sdr2hdr_dly;
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+	const u8 layer_mix_dly;
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+	const u8 hdr_mix_dly;
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+	const u8 win_dly;
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 	const struct vop_intr *intr;
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 	const struct vop_hdr_table *hdr_table;
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 	const struct vop2_video_port_regs *regs;
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@@ -849,6 +983,7 @@
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 	struct vop_reg version;
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 	struct vop_reg standby;
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 	struct vop_reg dma_stop;
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+	struct vop_reg dsp_vs_t_sel;
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 	struct vop_reg lut_dma_en;
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 	struct vop_reg axi_outstanding_max_num;
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 	struct vop_reg axi_max_outstanding_en;