rk3568 rt init

hc

2023-11-06 e3e12f52b214121840b44c91de5b3e5af5d3eb84

 kernel/drivers/gpu/drm/rockchip/rockchip_drm_tve.h
..
..
@@ -17,6 +17,13 @@
17
17
 
18
18
 #define RK3036_GRF_SOC_CON3	0x0154
19
19
 #define RK312X_GRF_TVE_CON	0x0170
20
+	#define m_EXTREF_EN		BIT(0)
21
+	#define m_VBG_EN		BIT(1)
22
+	#define m_DAC_EN		BIT(2)
23
+	#define m_SENSE_EN		BIT(3)
24
+	#define m_BIAS_EN		(7 << 4)
25
+	#define m_DAC_GAIN		(0x3f << 7)
26
+	#define v_DAC_GAIN(x)		(((x) & 0x3f) << 7)
20
27
 
21
28
 #define TV_CTRL			(0x00)
22
29
 	#define m_CVBS_MODE			BIT(24)
..
..
@@ -87,40 +94,123 @@
87
94
 
88
95
 #define TV_BRIGHTNESS_CONTRAST	(0x90)
89
96
 
90
-#define m_EXTREF_EN		BIT(0)
91
-#define m_VBG_EN		BIT(1)
92
-#define m_DAC_EN		BIT(2)
93
-#define m_SENSE_EN		BIT(3)
94
-#define m_BIAS_EN		(7 << 4)
95
-#define m_DAC_GAIN		(0x3f << 7)
96
-#define v_DAC_GAIN(x)		(((x) & 0x3f) << 7)
97
+#define VDAC_VDAC0		(0x00)
98
+	#define m_RST_ANA		BIT(7)
99
+	#define m_RST_DIG		BIT(6)
97
100
 
98
-#define VDAC_VDAC0             (0x00)
99
-       #define m_RST_ANA               BIT(7)
100
-       #define m_RST_DIG               BIT(6)
101
+	#define v_RST_ANA(x)		(((x) & 1) << 7)
102
+	#define v_RST_DIG(x)		(((x) & 1) << 6)
103
+#define VDAC_VDAC1		(0x280)
104
+	#define m_CUR_REG		(0xf << 4)
105
+	#define m_DR_PWR_DOWN		BIT(1)
106
+	#define m_BG_PWR_DOWN		BIT(0)
101
107
 
102
-       #define v_RST_ANA(x)            (((x) & 1) << 7)
103
-       #define v_RST_DIG(x)            (((x) & 1) << 6)
104
-#define VDAC_VDAC1             (0x280)
105
-       #define m_CUR_REG               (0xf << 4)
106
-       #define m_DR_PWR_DOWN           BIT(1)
107
-       #define m_BG_PWR_DOWN           BIT(0)
108
+	#define v_CUR_REG(x)		(((x) & 0xf) << 4)
109
+	#define v_DR_PWR_DOWN(x)	(((x) & 1) << 1)
110
+	#define v_BG_PWR_DOWN(x)	(((x) & 1) << 0)
111
+#define VDAC_VDAC2	(0x284)
112
+	#define m_CUR_CTR		(0X3f)
108
113
 
109
-       #define v_CUR_REG(x)            (((x) & 0xf) << 4)
110
-       #define v_DR_PWR_DOWN(x)        (((x) & 1) << 1)
111
-       #define v_BG_PWR_DOWN(x)        (((x) & 1) << 0)
112
-#define VDAC_VDAC2             (0x284)
113
-       #define m_CUR_CTR               (0X3f)
114
+	#define v_CUR_CTR(x)		(((x) & 0x3f))
115
+#define VDAC_VDAC3		(0x288)
116
+	#define m_CAB_EN		BIT(5)
117
+	#define m_CAB_REF		BIT(4)
118
+	#define m_CAB_FLAG		BIT(0)
114
119
 
115
-       #define v_CUR_CTR(x)            (((x) & 0x3f))
116
-#define VDAC_VDAC3             (0x288)
117
-       #define m_CAB_EN                BIT(5)
118
-       #define m_CAB_REF               BIT(4)
119
-       #define m_CAB_FLAG              BIT(0)
120
+	#define v_CAB_EN(x)		(((x) & 1) << 5)
121
+	#define v_CAB_REF(x)		(((x) & 1) << 4)
122
+	#define v_CAB_FLAG(x)		(((x) & 1) << 0)
120
123
 
121
-       #define v_CAB_EN(x)             (((x) & 1) << 5)
122
-       #define v_CAB_REF(x)            (((x) & 1) << 4)
123
-       #define v_CAB_FLAG(x)           (((x) & 1) << 0)
124
+// RK3528 CVBS GRF
125
+#define RK3528_VO_GRF_CVBS_CON	0x60010
126
+	#define m_TVE_DCLK_POL		BIT(5)
127
+	#define m_TVE_DCLK_EN		BIT(4)
128
+	#define m_DCLK_UPSAMPLE_2X4X	BIT(3)
129
+	#define m_DCLK_UPSAMPLE_EN	BIT(2)
130
+	#define m_TVE_MODE		BIT(1)
131
+	#define m_TVE_EN		BIT(0)
132
+
133
+	#define v_TVE_DCLK_POL(x)	(((x) & 1) << 5)
134
+	#define v_TVE_DCLK_EN(x)	(((x) & 1) << 4)
135
+	#define v_DCLK_UPSAMPLE_2X4X(x)	(((x) & 1) << 3)
136
+	#define v_DCLK_UPSAMPLE_EN(x)	(((x) & 1) << 2)
137
+	#define v_TVE_MODE(x)		(((x) & 1) << 1)
138
+	#define v_TVE_EN(x)		(((x) & 1) << 0)
139
+
140
+// RK3528 CVBS BT656
141
+#define BT656_DECODER_CTRL		(0x3D00)
142
+#define BT656_DECODER_CROP		(0x3D04)
143
+#define BT656_DECODER_SIZE		(0x3D08)
144
+#define BT656_DECODER_HTOTAL_HS_END	(0x3D0C)
145
+#define BT656_DECODER_VACT_ST_HACT_ST	(0x3D10)
146
+#define BT656_DECODER_VTOTAL_VS_END	(0x3D14)
147
+#define BT656_DECODER_VS_ST_END_F1	(0x3D18)
148
+#define BT656_DECODER_DBG_REG		(0x3D1C)
149
+
150
+// RK3528 CVBS TVE
151
+#define TVE_MODE_CTRL			(0x3E00)
152
+#define TVE_HOR_TIMING1			(0x3E04)
153
+#define TVE_HOR_TIMING2			(0x3E08)
154
+#define TVE_HOR_TIMING3			(0x3E0C)
155
+#define TVE_SUB_CAR_FRQ			(0x3E10)
156
+#define TVE_LUMA_FILTER1		(0x3E14)
157
+#define TVE_LUMA_FILTER2		(0x3E18)
158
+#define TVE_LUMA_FILTER3		(0x3E1C)
159
+#define TVE_LUMA_FILTER4		(0x3E20)
160
+#define TVE_LUMA_FILTER5		(0x3E24)
161
+#define TVE_LUMA_FILTER6		(0x3E28)
162
+#define TVE_LUMA_FILTER7		(0x3E2C)
163
+#define TVE_LUMA_FILTER8		(0x3E30)
164
+#define TVE_IMAGE_POSITION		(0x3E34)
165
+#define TVE_ROUTING			(0x3E38)
166
+#define TVE_SYNC_ADJUST			(0x3E50)
167
+#define TVE_STATUS			(0x3E54)
168
+#define TVE_CTRL			(0x3E68)
169
+#define TVE_INTR_STATUS			(0x3E6C)
170
+#define TVE_INTR_EN			(0x3E70)
171
+#define TVE_INTR_CLR			(0x3E74)
172
+#define TVE_COLOR_BUSRT_SAT		(0x3E78)
173
+#define TVE_CHROMA_BANDWIDTH		(0x3E8C)
174
+#define TVE_BRIGHTNESS_CONTRAST		(0x3E90)
175
+#define TVE_ID				(0x3E98)
176
+#define TVE_REVISION			(0x3E9C)
177
+#define TVE_CLAMP			(0x3EA0)
178
+
179
+// RK3528 CVBS VDAC
180
+#define VDAC_CLK_RST			(0x0000)
181
+	#define m_ANALOG_RST		BIT(7)
182
+	#define m_DIGITAL_RST		BIT(6)
183
+	#define m_INPUT_CLK_INV		BIT(0)
184
+
185
+	#define v_ANALOG_RST(x)		(((x) & 1) << 7)
186
+	#define v_DIGITAL_RST(x)	(((x) & 1) << 6)
187
+	#define v_INPUT_CLK_INV(x)	(((x) & 1) << 0)
188
+#define VDAC_SINE_CTRL			(0x0004)
189
+#define VDAC_SQUARE_CTRL		(0x0008)
190
+#define VDAC_LEVEL_CTRL0		(0x0018)
191
+#define VDAC_LEVEL_CTRL1		(0x001C)
192
+#define VDAC_PWM_REF_CTRL		(0x0280)
193
+	#define m_REF_VOLTAGE		(0xf << 4)
194
+	#define m_REF_RESISTOR		BIT(3)
195
+	#define m_SMP_CLK_INV		BIT(2)
196
+	#define m_DAC_PWN		BIT(1)
197
+	#define m_BIAS_PWN		BIT(0)
198
+
199
+	#define v_REF_VOLTAGE(x)	(((x) & 0xf) << 4)
200
+	#define v_SMP_CLK_INV(x)	(((x) & 1) << 2)
201
+	#define v_REF_RESISTOR(x)	(((x) & 1) << 3)
202
+	#define v_DAC_PWN(x)		(((x) & 1) << 1)
203
+	#define v_BIAS_PWN(x)		(((x) & 1) << 0)
204
+#define VDAC_CURRENT_CTRL		(0x0284)
205
+	#define m_OUT_CURRENT		(0xff << 0)
206
+
207
+	#define v_OUT_CURRENT(x)	(((x) & 0xff) << 0)
208
+#define VDAC_CABLE_CTRL			(0x0288)
209
+#define VDAC_VOLTAGE_CTRL		(0x028C)
210
+#define VDAC_BIAS_CLK_CTRL0		(0x0290)
211
+#define VDAC_BIAS_CLK_CTRL1		(0x0294)
212
+#define VDAC_AUTO_CLK_CTRL0		(0x0298)
213
+#define VDAC_AUTO_CLK_CTRL1		(0x029C)
124
214
 
125
215
 enum {
126
216
 	TVOUT_CVBS_NTSC = 0,
..
..
@@ -136,7 +226,14 @@
136
226
 	SOC_RK3036 = 0,
137
227
 	SOC_RK312X,
138
228
 	SOC_RK322X,
139
-	SOC_RK3328
229
+	SOC_RK3328,
230
+	SOC_RK3528
231
+};
232
+
233
+enum {
234
+	DCLK_UPSAMPLEx1 = 0,
235
+	DCLK_UPSAMPLEx2,
236
+	DCLK_UPSAMPLEx4
140
237
 };
141
238
 
142
239
 #define grf_writel(offset, v)	do { \
..
..
@@ -154,12 +251,16 @@
154
251
 	void __iomem			*regbase;
155
252
 	void __iomem			*vdacbase;
156
253
 	struct clk			*aclk;
157
-	struct clk			*dac_clk;
254
+	struct clk			*hclk;
255
+	struct clk			*pclk_vdac;
256
+	struct clk			*dclk;
257
+	struct clk			*dclk_4x;
158
258
 	struct regmap			*dac_grf;
159
259
 	u32				reg_phy_base;
160
260
 	u32				len;
161
261
 	int				input_format;
162
262
 	int				soc_type;
263
+	int				upsample_mode;
163
264
 	bool				enable;
164
265
 	u32 test_mode;
165
266
 	u32 saturation;
..
..
@@ -168,9 +269,15 @@
168
269
 	u32 lumafilter0;
169
270
 	u32 lumafilter1;
170
271
 	u32 lumafilter2;
272
+	u32 lumafilter3;
273
+	u32 lumafilter4;
274
+	u32 lumafilter5;
275
+	u32 lumafilter6;
276
+	u32 lumafilter7;
171
277
 	u32 daclevel;
172
278
 	u32 dac1level;
173
279
 	u32 preferred_mode;
280
+	u8 vdac_out_current;
174
281
 	struct mutex suspend_lock;	/* mutex for tve resume operation*/
175
282
 	struct rockchip_drm_sub_dev sub_dev;
176
283
 };