rk3568 rt init

hc

2023-11-06 e3e12f52b214121840b44c91de5b3e5af5d3eb84

 kernel/drivers/devfreq/rockchip_dmc.c
..
..
@@ -156,6 +156,7 @@
156
156
 	unsigned long video_1080p_rate;
157
157
 	unsigned long video_4k_rate;
158
158
 	unsigned long video_4k_10b_rate;
159
+	unsigned long video_4k_60p_rate;
159
160
 	unsigned long performance_rate;
160
161
 	unsigned long hdmi_rate;
161
162
 	unsigned long idle_rate;
..
..
@@ -1765,6 +1766,79 @@
1765
1766
 	return 0;
1766
1767
 }
1767
1768
 
1769
+static __maybe_unused int rk3528_dmc_init(struct platform_device *pdev,
1770
+					  struct rockchip_dmcfreq *dmcfreq)
1771
+{
1772
+	struct arm_smccc_res res;
1773
+	int ret;
1774
+	int complt_irq;
1775
+	u32 complt_hwirq;
1776
+	struct irq_data *complt_irq_data;
1777
+
1778
+	res = sip_smc_dram(0, 0, ROCKCHIP_SIP_CONFIG_DRAM_GET_VERSION);
1779
+	dev_notice(&pdev->dev, "current ATF version 0x%lx\n", res.a1);
1780
+	if (res.a0 || res.a1 < 0x100) {
1781
+		dev_err(&pdev->dev, "trusted firmware need update to V1.00 and above.\n");
1782
+		return -ENXIO;
1783
+	}
1784
+
1785
+	/*
1786
+	 * first 4KB is used for interface parameters
1787
+	 * after 4KB is dts parameters
1788
+	 * request share memory size 4KB * 2
1789
+	 */
1790
+	res = sip_smc_request_share_mem(2, SHARE_PAGE_TYPE_DDR);
1791
+	if (res.a0 != 0) {
1792
+		dev_err(&pdev->dev, "no ATF memory for init\n");
1793
+		return -ENOMEM;
1794
+	}
1795
+	ddr_psci_param = (struct share_params *)res.a1;
1796
+	/* Clear ddr_psci_param, size is 4KB * 2 */
1797
+	memset_io(ddr_psci_param, 0x0, 4096 * 2);
1798
+
1799
+	wait_ctrl.dcf_en = 0;
1800
+
1801
+	init_waitqueue_head(&wait_ctrl.wait_wq);
1802
+	wait_ctrl.wait_en = 1;
1803
+	wait_ctrl.wait_time_out_ms = 17 * 5;
1804
+
1805
+	complt_irq = platform_get_irq_byname(pdev, "complete");
1806
+	if (complt_irq < 0) {
1807
+		dev_err(&pdev->dev, "no IRQ for complt_irq: %d\n", complt_irq);
1808
+		return complt_irq;
1809
+	}
1810
+	wait_ctrl.complt_irq = complt_irq;
1811
+
1812
+	ret = devm_request_irq(&pdev->dev, complt_irq, wait_dcf_complete_irq,
1813
+			       0, dev_name(&pdev->dev), &wait_ctrl);
1814
+	if (ret < 0) {
1815
+		dev_err(&pdev->dev, "cannot request complt_irq\n");
1816
+		return ret;
1817
+	}
1818
+	disable_irq(complt_irq);
1819
+
1820
+	complt_irq_data = irq_get_irq_data(complt_irq);
1821
+	complt_hwirq = irqd_to_hwirq(complt_irq_data);
1822
+	ddr_psci_param->complt_hwirq = complt_hwirq;
1823
+
1824
+	res = sip_smc_dram(SHARE_PAGE_TYPE_DDR, 0, ROCKCHIP_SIP_CONFIG_DRAM_INIT);
1825
+	if (res.a0) {
1826
+		dev_err(&pdev->dev, "rockchip_sip_config_dram_init error:%lx\n", res.a0);
1827
+		return -ENOMEM;
1828
+	}
1829
+
1830
+	ret = rockchip_get_freq_info(dmcfreq);
1831
+	if (ret < 0) {
1832
+		dev_err(&pdev->dev, "cannot get frequency info\n");
1833
+		return ret;
1834
+	}
1835
+	dmcfreq->is_set_rate_direct = true;
1836
+
1837
+	dmcfreq->set_auto_self_refresh = rockchip_ddr_set_auto_self_refresh;
1838
+
1839
+	return 0;
1840
+}
1841
+
1768
1842
 static __maybe_unused int rk3568_dmc_init(struct platform_device *pdev,
1769
1843
 					  struct rockchip_dmcfreq *dmcfreq)
1770
1844
 {
..
..
@@ -1945,6 +2019,9 @@
1945
2019
 #endif
1946
2020
 #ifdef CONFIG_CPU_RK3399
1947
2021
 	{ .compatible = "rockchip,rk3399-dmc", .data = rk3399_dmc_init },
2022
+#endif
2023
+#ifdef CONFIG_CPU_RK3528
2024
+	{ .compatible = "rockchip,rk3528-dmc", .data = rk3528_dmc_init },
1948
2025
 #endif
1949
2026
 #ifdef CONFIG_CPU_RK3568
1950
2027
 	{ .compatible = "rockchip,rk3568-dmc", .data = rk3568_dmc_init },
..
..
@@ -2222,6 +2299,11 @@
2222
2299
 			dev_info(dmcfreq->dev, "video_4k_10b_rate = %ld\n",
2223
2300
 				 dmcfreq->video_4k_10b_rate);
2224
2301
 			break;
2302
+		case SYS_STATUS_VIDEO_4K_60P:
2303
+			dmcfreq->video_4k_60p_rate = rockchip_freq_level_2_rate(dmcfreq, level);
2304
+			dev_info(dmcfreq->dev, "video_4k_60p_rate = %ld\n",
2305
+				 dmcfreq->video_4k_60p_rate);
2306
+			break;
2225
2307
 		case SYS_STATUS_PERFORMANCE:
2226
2308
 			dmcfreq->performance_rate = rockchip_freq_level_2_rate(dmcfreq, level);
2227
2309
 			dev_info(dmcfreq->dev, "performance_rate = %ld\n",
..
..
@@ -2337,6 +2419,11 @@
2337
2419
 	if (dmcfreq->video_4k_10b_rate && (status & SYS_STATUS_VIDEO_4K_10B)) {
2338
2420
 		if (dmcfreq->video_4k_10b_rate > target_rate)
2339
2421
 			target_rate = dmcfreq->video_4k_10b_rate;
2422
+	}
2423
+
2424
+	if (dmcfreq->video_4k_60p_rate && (status & SYS_STATUS_VIDEO_4K_60P)) {
2425
+		if (dmcfreq->video_4k_60p_rate > target_rate)
2426
+			target_rate = dmcfreq->video_4k_60p_rate;
2340
2427
 	}
2341
2428
 
2342
2429
 	if (dmcfreq->video_1080p_rate && (status & SYS_STATUS_VIDEO_1080P)) {
..
..
@@ -2978,8 +3065,16 @@
2978
3065
 	return 0;
2979
3066
 }
2980
3067
 
3068
+static int rockchip_dmcfreq_low_temp_adjust_volt(struct monitor_dev_info *mdev_info)
3069
+{
3070
+	struct rockchip_dmcfreq *dmcfreq = dev_get_drvdata(mdev_info->dev);
3071
+
3072
+	return rockchip_dmcfreq_set_volt_only(dmcfreq);
3073
+}
3074
+
2981
3075
 static struct monitor_dev_profile dmc_mdevp = {
2982
3076
 	.type = MONITOR_TPYE_DEV,
3077
+	.low_temp_adjust_volt = rockchip_dmcfreq_low_temp_adjust_volt,
2983
3078
 	.low_temp_adjust = rockchip_monitor_dev_low_temp_adjust,
2984
3079
 	.high_temp_adjust = rockchip_monitor_dev_high_temp_adjust,
2985
3080
 };
..
..
@@ -2988,14 +3083,15 @@
2988
3083
 {
2989
3084
 	int ret;
2990
3085
 
2991
-	if (vop_register_dmc())
2992
-		dev_err(dmcfreq->dev, "fail to register notify to vop.\n");
3086
+	if (dmcfreq->system_status_en || dmcfreq->auto_freq_en) {
3087
+		if (vop_register_dmc())
3088
+			dev_err(dmcfreq->dev, "fail to register notify to vop.\n");
2993
3089
 
2994
-	dmcfreq->status_nb.notifier_call =
2995
-		rockchip_dmcfreq_system_status_notifier;
2996
-	ret = rockchip_register_system_status_notifier(&dmcfreq->status_nb);
2997
-	if (ret)
2998
-		dev_err(dmcfreq->dev, "failed to register system_status nb\n");
3090
+		dmcfreq->status_nb.notifier_call = rockchip_dmcfreq_system_status_notifier;
3091
+		ret = rockchip_register_system_status_notifier(&dmcfreq->status_nb);
3092
+		if (ret)
3093
+			dev_err(dmcfreq->dev, "failed to register system_status nb\n");
3094
+	}
2999
3095
 
3000
3096
 	dmc_mdevp.data = dmcfreq->devfreq;
3001
3097
 	dmcfreq->mdev_info = rockchip_system_monitor_register(dmcfreq->dev,
..
..
@@ -3279,14 +3375,15 @@
3279
3375
 		return ret;
3280
3376
 
3281
3377
 	rockchip_dmcfreq_parse_dt(data);
3378
+	platform_set_drvdata(pdev, data);
3282
3379
 	if (!data->system_status_en && !data->auto_freq_en) {
3283
3380
 		dev_info(dev, "don't add devfreq feature\n");
3381
+		rockchip_dmcfreq_register_notifier(data);
3284
3382
 		return rockchip_dmcfreq_set_volt_only(data);
3285
3383
 	}
3286
3384
 
3287
3385
 	pm_qos_add_request(&pm_qos, PM_QOS_CPU_DMA_LATENCY,
3288
3386
 			   PM_QOS_DEFAULT_VALUE);
3289
-	platform_set_drvdata(pdev, data);
3290
3387
 
3291
3388
 	ret = devfreq_add_governor(&devfreq_dmc_ondemand);
3292
3389
 	if (ret)
..
..
@@ -3323,10 +3420,12 @@
3323
3420
 	if (ret)
3324
3421
 		return ret;
3325
3422
 
3326
-	ret = devfreq_suspend_device(dmcfreq->devfreq);
3327
-	if (ret < 0) {
3328
-		dev_err(dev, "failed to suspend the devfreq devices\n");
3329
-		return ret;
3423
+	if (dmcfreq->devfreq) {
3424
+		ret = devfreq_suspend_device(dmcfreq->devfreq);
3425
+		if (ret < 0) {
3426
+			dev_err(dev, "failed to suspend the devfreq devices\n");
3427
+			return ret;
3428
+		}
3330
3429
 	}
3331
3430
 
3332
3431
 	return 0;
..
..
@@ -3344,11 +3443,14 @@
3344
3443
 	if (ret)
3345
3444
 		return ret;
3346
3445
 
3347
-	ret = devfreq_resume_device(dmcfreq->devfreq);
3348
-	if (ret < 0) {
3349
-		dev_err(dev, "failed to resume the devfreq devices\n");
3350
-		return ret;
3446
+	if (dmcfreq->devfreq) {
3447
+		ret = devfreq_resume_device(dmcfreq->devfreq);
3448
+		if (ret < 0) {
3449
+			dev_err(dev, "failed to resume the devfreq devices\n");
3450
+			return ret;
3451
+		}
3351
3452
 	}
3453
+
3352
3454
 	return ret;
3353
3455
 }
3354
3456