rk3568 rt init

hc

2023-11-06 e3e12f52b214121840b44c91de5b3e5af5d3eb84

 kernel/drivers/devfreq/event/rockchip-dfi.c
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@@ -56,6 +56,10 @@
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 #define RK3368_DFI_EN			(0x30003 << 5)
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 #define RK3368_DFI_DIS			(0x30000 << 5)
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58
 
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+#define RK3528_PMUGRF_OFFSET		0x70000
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+#define RK3528_PMUGRF_OS_REG18		0x248
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+#define RK3528_PMUGRF_OS_REG19		0x24c
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+
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 #define MAX_DMC_NUM_CH			2
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 #define READ_DRAMTYPE_INFO(n)		(((n) >> 13) & 0x7)
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 #define READ_CH_INFO(n)			(((n) >> 28) & 0x3)
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@@ -111,6 +115,7 @@
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 	struct regmap *regmap_pmugrf;
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 	struct clk *clk;
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 	u32 dram_type;
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+	u32 count_rate;
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 	/*
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 	 * available mask, 1: available, 0: not available
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 	 * each bit represent a channel
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@@ -377,8 +382,12 @@
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 	u32 tmp, max = 0;
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 	u32 i, busier_ch = 0;
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 	void __iomem *dfi_regs = info->regs;
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+	u32 count_rate = 1;
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386
 
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 	rockchip_dfi_stop_hardware_counter(edev);
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+
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+	if (info->count_rate)
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+		count_rate = info->count_rate;
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 	/* Find out which channel is busier */
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 	for (i = 0; i < MAX_DMC_NUM_CH; i++) {
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@@ -386,7 +395,7 @@
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 			continue;
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 		info->ch_usage[i].total = readl_relaxed(dfi_regs +
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-				DDRMON_CH0_COUNT_NUM + i * 20);
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+				DDRMON_CH0_COUNT_NUM + i * 20) * count_rate;
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 		/* LPDDR4 and LPDDR4X BL = 16,other DDR type BL = 8 */
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 		tmp = readl_relaxed(dfi_regs +
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@@ -639,6 +648,41 @@
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 	return 0;
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 }
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+static __maybe_unused __init int rk3528_dfi_init(struct platform_device *pdev,
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+						 struct rockchip_dfi *data,
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+						 struct devfreq_event_desc *desc)
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+{
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+	struct device_node *np = pdev->dev.of_node, *node;
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+	struct resource *res;
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+	u32 val_18, val_19;
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+
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+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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+	data->regs = devm_ioremap_resource(&pdev->dev, res);
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+	if (IS_ERR(data->regs))
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+		return PTR_ERR(data->regs);
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+
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+	node = of_parse_phandle(np, "rockchip,grf", 0);
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+	if (node) {
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+		data->regmap_grf = syscon_node_to_regmap(node);
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+		if (IS_ERR(data->regmap_grf))
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+			return PTR_ERR(data->regmap_grf);
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+	}
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+
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+	regmap_read(data->regmap_grf, RK3528_PMUGRF_OFFSET + RK3528_PMUGRF_OS_REG18, &val_18);
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+	regmap_read(data->regmap_grf, RK3528_PMUGRF_OFFSET + RK3528_PMUGRF_OS_REG19, &val_19);
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+	if (READ_SYSREG_VERSION(val_19) >= 0x3)
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+		data->dram_type = READ_DRAMTYPE_INFO_V3(val_18, val_19);
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+	else
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+		data->dram_type = READ_DRAMTYPE_INFO(val_18);
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+	data->count_rate = 2;
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+	data->ch_msk = 1;
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+	data->clk = NULL;
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+
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+	desc->ops = &rockchip_dfi_ops;
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+
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+	return 0;
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+}
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+
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 static const struct of_device_id rockchip_dfi_id_match[] = {
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 #ifdef CONFIG_CPU_PX30
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 	{ .compatible = "rockchip,px30-dfi", .data = px30_dfi_init },
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@@ -661,6 +705,9 @@
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 #ifdef CONFIG_CPU_RK3399
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 	{ .compatible = "rockchip,rk3399-dfi", .data = rockchip_dfi_init },
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 #endif
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+#ifdef CONFIG_CPU_RK3528
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+	{ .compatible = "rockchip,rk3528-dfi", .data = rk3528_dfi_init },
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+#endif
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 #ifdef CONFIG_CPU_RK3568
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 	{ .compatible = "rockchip,rk3568-dfi", .data = px30_dfi_init },
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 #endif