rk3568 rt init

hc

2023-11-06 e3e12f52b214121840b44c91de5b3e5af5d3eb84

 kernel/drivers/clocksource/tcb_clksrc.c
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@@ -25,8 +25,7 @@
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  *     this 32 bit free-running counter. the second channel is not used.
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  *
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  *   - The third channel may be used to provide a 16-bit clockevent
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- *     source, used in either periodic or oneshot mode.  This runs
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- *     at 32 KiHZ, and can handle delays of up to two seconds.
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+ *     source, used in either periodic or oneshot mode.
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  *
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  * A boot clocksource and clockevent source are also currently needed,
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  * unless the relevant platforms (ARM/AT91, AVR32/AT32) are changed so
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@@ -126,6 +125,8 @@
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 struct tc_clkevt_device {
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 	struct clock_event_device	clkevt;
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 	struct clk			*clk;
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+	bool				clk_enabled;
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+	u32				freq;
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 	void __iomem			*regs;
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 };
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@@ -134,14 +135,25 @@
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 	return container_of(clkevt, struct tc_clkevt_device, clkevt);
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 }
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-/* For now, we always use the 32K clock ... this optimizes for NO_HZ,
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- * because using one of the divided clocks would usually mean the
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- * tick rate can never be less than several dozen Hz (vs 0.5 Hz).
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- *
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- * A divided clock could be good for high resolution timers, since
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- * 30.5 usec resolution can seem "low".
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- */
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 static u32 timer_clock;
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+
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+static void tc_clk_disable(struct clock_event_device *d)
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+{
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+	struct tc_clkevt_device *tcd = to_tc_clkevt(d);
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+
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+	clk_disable(tcd->clk);
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+	tcd->clk_enabled = false;
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+}
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+
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+static void tc_clk_enable(struct clock_event_device *d)
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+{
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+	struct tc_clkevt_device *tcd = to_tc_clkevt(d);
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+
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+	if (tcd->clk_enabled)
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+		return;
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+	clk_enable(tcd->clk);
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+	tcd->clk_enabled = true;
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+}
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157
 
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 static int tc_shutdown(struct clock_event_device *d)
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 {
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@@ -150,8 +162,14 @@
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162
 
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 	writel(0xff, regs + ATMEL_TC_REG(2, IDR));
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 	writel(ATMEL_TC_CLKDIS, regs + ATMEL_TC_REG(2, CCR));
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+	return 0;
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+}
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+
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+static int tc_shutdown_clk_off(struct clock_event_device *d)
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+{
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+	tc_shutdown(d);
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 	if (!clockevent_state_detached(d))
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-		clk_disable(tcd->clk);
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+		tc_clk_disable(d);
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173
 
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 	return 0;
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 }
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@@ -164,9 +182,9 @@
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 	if (clockevent_state_oneshot(d) || clockevent_state_periodic(d))
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 		tc_shutdown(d);
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184
 
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-	clk_enable(tcd->clk);
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+	tc_clk_enable(d);
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186
 
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-	/* slow clock, count up to RC, then irq and stop */
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+	/* count up to RC, then irq and stop */
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 	writel(timer_clock | ATMEL_TC_CPCSTOP | ATMEL_TC_WAVE |
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 		     ATMEL_TC_WAVESEL_UP_AUTO, regs + ATMEL_TC_REG(2, CMR));
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 	writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
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@@ -186,12 +204,12 @@
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 	/* By not making the gentime core emulate periodic mode on top
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 	 * of oneshot, we get lower overhead and improved accuracy.
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 	 */
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-	clk_enable(tcd->clk);
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+	tc_clk_enable(d);
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208
 
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-	/* slow clock, count up to RC, then irq and restart */
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+	/* count up to RC, then irq and restart */
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 	writel(timer_clock | ATMEL_TC_WAVE | ATMEL_TC_WAVESEL_UP_AUTO,
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 		     regs + ATMEL_TC_REG(2, CMR));
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-	writel((32768 + HZ / 2) / HZ, tcaddr + ATMEL_TC_REG(2, RC));
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+	writel((tcd->freq + HZ / 2) / HZ, tcaddr + ATMEL_TC_REG(2, RC));
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213
 
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 	/* Enable clock and interrupts on RC compare */
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 	writel(ATMEL_TC_CPCS, regs + ATMEL_TC_REG(2, IER));
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@@ -218,9 +236,13 @@
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 		.features		= CLOCK_EVT_FEAT_PERIODIC |
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 					  CLOCK_EVT_FEAT_ONESHOT,
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 		/* Should be lower than at91rm9200's system timer */
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+#ifdef CONFIG_ATMEL_TCB_CLKSRC_USE_SLOW_CLOCK
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 		.rating			= 125,
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+#else
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+		.rating			= 200,
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+#endif
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 		.set_next_event		= tc_next_event,
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-		.set_state_shutdown	= tc_shutdown,
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+		.set_state_shutdown	= tc_shutdown_clk_off,
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 		.set_state_periodic	= tc_set_periodic,
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 		.set_state_oneshot	= tc_set_oneshot,
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 	},
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@@ -240,8 +262,9 @@
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 	return IRQ_NONE;
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 }
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264
 
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-static int __init setup_clkevents(struct atmel_tc *tc, int clk32k_divisor_idx)
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+static int __init setup_clkevents(struct atmel_tc *tc, int divisor_idx)
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 {
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+	unsigned divisor = atmel_tc_divisors[divisor_idx];
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 	int ret;
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 	struct clk *t2_clk = tc->clk[2];
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 	int irq = tc->irq[2];
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@@ -262,7 +285,11 @@
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 	clkevt.regs = tc->regs;
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 	clkevt.clk = t2_clk;
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-	timer_clock = clk32k_divisor_idx;
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+	timer_clock = divisor_idx;
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+	if (!divisor)
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+		clkevt.freq = 32768;
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+	else
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+		clkevt.freq = clk_get_rate(t2_clk) / divisor;
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 	clkevt.clkevt.cpumask = cpumask_of(0);
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@@ -273,7 +300,7 @@
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 		return ret;
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 	}
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-	clockevents_config_and_register(&clkevt.clkevt, 32768, 1, 0xffff);
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+	clockevents_config_and_register(&clkevt.clkevt, clkevt.freq, 1, 0xffff);
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 	return ret;
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 }
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@@ -410,7 +437,11 @@
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 		goto err_disable_t1;
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 	/* channel 2:  periodic and oneshot timer support */
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+#ifdef CONFIG_ATMEL_TCB_CLKSRC_USE_SLOW_CLOCK
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 	ret = setup_clkevents(tc, clk32k_divisor_idx);
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+#else
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+	ret = setup_clkevents(tc, best_divisor_idx);
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+#endif
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 	if (ret)
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 		goto err_unregister_clksrc;
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