rk3568 rt init

hc

2023-11-06 e3e12f52b214121840b44c91de5b3e5af5d3eb84

 kernel/drivers/clk/rockchip/clk.h
..
..
@@ -255,6 +255,34 @@
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 #define RK3399_PMU_CLKGATE_CON(x)	((x) * 0x4 + 0x100)
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 #define RK3399_PMU_SOFTRST_CON(x)	((x) * 0x4 + 0x110)
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+#define RK3528_PMU_CRU_BASE		0x10000
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+#define RK3528_PCIE_CRU_BASE		0x20000
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+#define RK3528_DDRPHY_CRU_BASE		0x28000
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+#define RK3528_VPU_GRF_BASE		0x40000
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+#define RK3528_VO_GRF_BASE		0x60000
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+#define RK3528_SDMMC_CON0		(RK3528_VO_GRF_BASE + 0x24)
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+#define RK3528_SDMMC_CON1		(RK3528_VO_GRF_BASE + 0x28)
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+#define RK3528_SDIO0_CON0		(RK3528_VPU_GRF_BASE + 0x4)
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+#define RK3528_SDIO0_CON1		(RK3528_VPU_GRF_BASE + 0x8)
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+#define RK3528_SDIO1_CON0		(RK3528_VPU_GRF_BASE + 0xc)
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+#define RK3528_SDIO1_CON1		(RK3528_VPU_GRF_BASE + 0x10)
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+#define RK3528_PLL_CON(x)		RK2928_PLL_CON(x)
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+#define RK3528_PCIE_PLL_CON(x)		((x) * 0x4 + RK3528_PCIE_CRU_BASE)
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+#define RK3528_DDRPHY_PLL_CON(x)	((x) * 0x4 + RK3528_DDRPHY_CRU_BASE)
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+#define RK3528_MODE_CON			0x280
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+#define RK3528_CLKSEL_CON(x)		((x) * 0x4 + 0x300)
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+#define RK3528_CLKGATE_CON(x)		((x) * 0x4 + 0x800)
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+#define RK3528_SOFTRST_CON(x)		((x) * 0x4 + 0xa00)
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+#define RK3528_PMU_CLKSEL_CON(x)	((x) * 0x4 + 0x300 + RK3528_PMU_CRU_BASE)
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+#define RK3528_PMU_CLKGATE_CON(x)	((x) * 0x4 + 0x800 + RK3528_PMU_CRU_BASE)
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+#define RK3528_PCIE_CLKSEL_CON(x)	((x) * 0x4 + 0x300 + RK3528_PCIE_CRU_BASE)
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+#define RK3528_PCIE_CLKGATE_CON(x)	((x) * 0x4 + 0x800 + RK3528_PCIE_CRU_BASE)
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+#define RK3528_DDRPHY_CLKGATE_CON(x)	((x) * 0x4 + 0x800 + RK3528_DDRPHY_CRU_BASE)
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+#define RK3528_DDRPHY_MODE_CON		(0x280 + RK3528_DDRPHY_CRU_BASE)
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+#define RK3528_GLB_CNT_TH		0xc00
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+#define RK3528_GLB_SRST_FST		0xc08
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+#define RK3528_GLB_SRST_SND		0xc0c
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+
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 #define RK3568_PLL_CON(x)		RK2928_PLL_CON(x)
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 #define RK3568_MODE_CON0		0xc0
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 #define RK3568_MISC_CON0		0xc4