| .. | .. |
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| 1421 | 1421 | RK3568_CLKSEL_CON(72), 6, 1, MFLAGS, RK3568_CLKGATE_CON(31), 1, GFLAGS), |
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| 1422 | 1422 | GATE(PCLK_PWM1, "pclk_pwm1", "pclk_bus", 0, RK3568_CLKGATE_CON(31), 10, GFLAGS), |
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| 1423 | 1423 | COMPOSITE_NODIV(CLK_PWM1, "clk_pwm1", gpll100_xin24m_cpll100_p, 0, |
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| 1424 | | - RK3568_CLKSEL_CON(72), 8, 1, MFLAGS, |
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| 1424 | + RK3568_CLKSEL_CON(72), 8, 2, MFLAGS, |
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| 1425 | 1425 | RK3568_CLKGATE_CON(31), 11, GFLAGS), |
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| 1426 | 1426 | GATE(CLK_PWM1_CAPTURE, "clk_pwm1_capture", "xin24m", 0, |
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| 1427 | 1427 | RK3568_CLKGATE_CON(31), 12, GFLAGS), |
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| 1428 | 1428 | GATE(PCLK_PWM2, "pclk_pwm2", "pclk_bus", 0, |
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| 1429 | 1429 | RK3568_CLKGATE_CON(31), 13, GFLAGS), |
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| 1430 | 1430 | COMPOSITE_NODIV(CLK_PWM2, "clk_pwm2", gpll100_xin24m_cpll100_p, 0, |
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| 1431 | | - RK3568_CLKSEL_CON(72), 10, 1, MFLAGS, |
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| 1431 | + RK3568_CLKSEL_CON(72), 10, 2, MFLAGS, |
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| 1432 | 1432 | RK3568_CLKGATE_CON(31), 14, GFLAGS), |
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| 1433 | 1433 | GATE(CLK_PWM2_CAPTURE, "clk_pwm2_capture", "xin24m", 0, |
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| 1434 | 1434 | RK3568_CLKGATE_CON(31), 15, GFLAGS), |
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| 1435 | 1435 | GATE(PCLK_PWM3, "pclk_pwm3", "pclk_bus", 0, |
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| 1436 | 1436 | RK3568_CLKGATE_CON(32), 0, GFLAGS), |
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| 1437 | 1437 | COMPOSITE_NODIV(CLK_PWM3, "clk_pwm3", gpll100_xin24m_cpll100_p, 0, |
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| 1438 | | - RK3568_CLKSEL_CON(72), 12, 1, MFLAGS, |
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| 1438 | + RK3568_CLKSEL_CON(72), 12, 2, MFLAGS, |
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| 1439 | 1439 | RK3568_CLKGATE_CON(32), 1, GFLAGS), |
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| 1440 | 1440 | GATE(CLK_PWM3_CAPTURE, "clk_pwm3_capture", "xin24m", 0, |
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| 1441 | 1441 | RK3568_CLKGATE_CON(32), 2, GFLAGS), |
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