rk3568 rt init

hc

2023-11-06 e3e12f52b214121840b44c91de5b3e5af5d3eb84

 kernel/arch/arm64/boot/dts/rockchip/rk3568.dtsi
old mode 100755new mode 100644
..
..
@@ -126,12 +126,14 @@
126
126
 		opp-shared;
127
127
 
128
128
 		mbist-vmin = <825000 900000 950000>;
129
-		nvmem-cells = <&cpu_leakage>, <&core_pvtm>, <&mbist_vmin>;
130
-		nvmem-cell-names = "leakage", "pvtm", "mbist-vmin";
129
+		nvmem-cells = <&cpu_leakage>, <&core_pvtm>, <&mbist_vmin>, <&cpu_opp_info>;
130
+		nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info";
131
+		rockchip,max-volt = <1150000>;
131
132
 		rockchip,pvtm-voltage-sel = <
132
133
 			0        84000   0
133
-			84001    91000   1
134
-			91001    100000  2
134
+			84001    87000   1
135
+			87001    91000   2
136
+			91001    100000  3
135
137
 		>;
136
138
 		rockchip,pvtm-freq = <408000>;
137
139
 		rockchip,pvtm-volt = <900000>;
..
..
@@ -146,31 +148,22 @@
146
148
 		rockchip,low-temp = <0>;
147
149
 		rockchip,low-temp-adjust-volt = <
148
150
 			/* MHz    MHz    uV */
149
-			   0      1608   75000
151
+			   0      1992   75000
150
152
 		>;
151
153
 
152
154
 		opp-408000000 {
153
155
 			opp-hz = /bits/ 64 <408000000>;
154
156
 			opp-microvolt = <850000 850000 1150000>;
155
-			opp-microvolt-L0 = <850000 850000 1150000>;
156
-			opp-microvolt-L1 = <825000 825000 1150000>;
157
-			opp-microvolt-L2 = <825000 825000 1150000>;
158
157
 			clock-latency-ns = <40000>;
159
158
 		};
160
159
 		opp-600000000 {
161
160
 			opp-hz = /bits/ 64 <600000000>;
162
-			opp-microvolt = <850000 825000 1150000>;
163
-			opp-microvolt-L0 = <850000 850000 1150000>;
164
-			opp-microvolt-L1 = <825000 825000 1150000>;
165
-			opp-microvolt-L2 = <825000 825000 1150000>;
161
+			opp-microvolt = <850000 850000 1150000>;
166
162
 			clock-latency-ns = <40000>;
167
163
 		};
168
164
 		opp-816000000 {
169
165
 			opp-hz = /bits/ 64 <816000000>;
170
166
 			opp-microvolt = <850000 850000 1150000>;
171
-			opp-microvolt-L0 = <850000 850000 1150000>;
172
-			opp-microvolt-L1 = <825000 825000 1150000>;
173
-			opp-microvolt-L2 = <825000 825000 1150000>;
174
167
 			clock-latency-ns = <40000>;
175
168
 			opp-suspend;
176
169
 		};
..
..
@@ -178,40 +171,45 @@
178
171
 			opp-hz = /bits/ 64 <1104000000>;
179
172
 			opp-microvolt = <900000 900000 1150000>;
180
173
 			opp-microvolt-L0 = <900000 900000 1150000>;
181
-			opp-microvolt-L1 = <825000 825000 1150000>;
182
-			opp-microvolt-L2 = <825000 825000 1150000>;
174
+			opp-microvolt-L1 = <850000 850000 1150000>;
175
+			opp-microvolt-L2 = <850000 850000 1150000>;
176
+			opp-microvolt-L3 = <850000 850000 1150000>;
183
177
 			clock-latency-ns = <40000>;
184
178
 		};
185
179
 		opp-1416000000 {
186
180
 			opp-hz = /bits/ 64 <1416000000>;
187
-			opp-microvolt = <1000000 1000000 1150000>;
188
-			opp-microvolt-L0 = <1000000 1000000 1150000>;
189
-			opp-microvolt-L1 = <925000 925000 1150000>;
190
-			opp-microvolt-L2 = <925000 925000 1150000>;
181
+			opp-microvolt = <1025000 1025000 1150000>;
182
+			opp-microvolt-L0 = <1025000 1025000 1150000>;
183
+			opp-microvolt-L1 = <975000 975000 1150000>;
184
+			opp-microvolt-L2 = <950000 950000 1150000>;
185
+			opp-microvolt-L3 = <925000 925000 1150000>;
191
186
 			clock-latency-ns = <40000>;
192
187
 		};
193
188
 		opp-1608000000 {
194
189
 			opp-hz = /bits/ 64 <1608000000>;
195
-			opp-microvolt = <1075000 1075000 1150000>;
196
-			opp-microvolt-L0 = <1075000 1075000 1150000>;
197
-			opp-microvolt-L1 = <1000000 1000000 1150000>;
198
-			opp-microvolt-L2 = <1000000 1000000 1150000>;
190
+			opp-microvolt = <1100000 1100000 1150000>;
191
+			opp-microvolt-L0 = <1100000 1100000 1150000>;
192
+			opp-microvolt-L1 = <1050000 1050000 1150000>;
193
+			opp-microvolt-L2 = <1025000 1025000 1150000>;
194
+			opp-microvolt-L3 = <1000000 1000000 1150000>;
199
195
 			clock-latency-ns = <40000>;
200
196
 		};
201
197
 		opp-1800000000 {
202
198
 			opp-hz = /bits/ 64 <1800000000>;
203
-			opp-microvolt = <1125000 1125000 1150000>;
204
-			opp-microvolt-L0 = <1125000 1125000 1150000>;
205
-			opp-microvolt-L1 = <1050000 1050000 1150000>;
206
-			opp-microvolt-L2 = <1050000 1050000 1150000>;
199
+			opp-microvolt = <1150000 1150000 1150000>;
200
+			opp-microvolt-L0 = <1150000 1150000 1150000>;
201
+			opp-microvolt-L1 = <1100000 1100000 1150000>;
202
+			opp-microvolt-L2 = <1075000 1075000 1150000>;
203
+			opp-microvolt-L3 = <1050000 1050000 1150000>;
207
204
 			clock-latency-ns = <40000>;
208
205
 		};
209
206
 		opp-1992000000 {
210
207
 			opp-hz = /bits/ 64 <1992000000>;
211
208
 			opp-microvolt = <1150000 1150000 1150000>;
212
209
 			opp-microvolt-L0 = <1150000 1150000 1150000>;
213
-			opp-microvolt-L1 = <1100000 1100000 1150000>;
214
-			opp-microvolt-L2 = <1075000 1075000 1150000>;
210
+			opp-microvolt-L1 = <1150000 1150000 1150000>;
211
+			opp-microvolt-L2 = <1125000 1125000 1150000>;
212
+			opp-microvolt-L3 = <1100000 1100000 1150000>;
215
213
 			clock-latency-ns = <40000>;
216
214
 		};
217
215
 	};
..
..
@@ -307,7 +305,7 @@
307
305
 				reg = <0x14>;
308
306
 				#clock-cells = <1>;
309
307
 
310
-				rockchip,clk-init = <1416000000>;
308
+				rockchip,clk-init = <1104000000>;
311
309
 			};
312
310
 		};
313
311
 
..
..
@@ -938,7 +936,7 @@
938
936
 		dmas = <&dmac0 0>, <&dmac0 1>;
939
937
 		pinctrl-names = "default";
940
938
 		pinctrl-0 = <&uart0_xfer>;
941
-		status = "okay";
939
+		status = "disabled";
942
940
 	};
943
941
 
944
942
 	pwm0: pwm@fdd70000 {
..
..
@@ -1109,76 +1107,70 @@
1109
1107
 		compatible = "operating-points-v2";
1110
1108
 
1111
1109
 		mbist-vmin = <825000 900000 950000>;
1112
-		nvmem-cells = <&npu_leakage>, <&core_pvtm>, <&mbist_vmin>;
1113
-		nvmem-cell-names = "leakage", "pvtm", "mbist-vmin";
1110
+		nvmem-cells = <&npu_leakage>, <&core_pvtm>, <&mbist_vmin>, <&npu_opp_info>;
1111
+		nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info";
1112
+		rockchip,max-volt = <1000000>;
1114
1113
 		rockchip,temp-hysteresis = <5000>;
1115
1114
 		rockchip,low-temp = <0>;
1116
1115
 		rockchip,low-temp-adjust-volt = <
1117
1116
 			/* MHz    MHz    uV */
1118
-			   0      700    50000
1117
+			   0      1000    50000
1119
1118
 		>;
1120
1119
 		rockchip,pvtm-voltage-sel = <
1121
1120
 			0        84000   0
1122
-			84001    91000   1
1123
-			91001    100000  2
1121
+			84001    87000   1
1122
+			87001    91000   2
1123
+			91001    100000  3
1124
1124
 		>;
1125
1125
 		rockchip,pvtm-ch = <0 5>;
1126
1126
 
1127
1127
 		opp-200000000 {
1128
1128
 			opp-hz = /bits/ 64 <200000000>;
1129
1129
 			opp-microvolt = <850000 850000 1000000>;
1130
-			opp-microvolt-L0 = <850000 850000 1000000>;
1131
-			opp-microvolt-L1 = <825000 825000 1000000>;
1132
-			opp-microvolt-L2 = <825000 825000 1000000>;
1133
1130
 		};
1134
1131
 		opp-300000000 {
1135
1132
 			opp-hz = /bits/ 64 <297000000>;
1136
1133
 			opp-microvolt = <850000 850000 1000000>;
1137
-			opp-microvolt-L0 = <850000 850000 1000000>;
1138
-			opp-microvolt-L1 = <825000 825000 1000000>;
1139
-			opp-microvolt-L2 = <825000 825000 1000000>;
1140
1134
 		};
1141
1135
 		opp-400000000 {
1142
1136
 			opp-hz = /bits/ 64 <400000000>;
1143
1137
 			opp-microvolt = <850000 850000 1000000>;
1144
-			opp-microvolt-L0 = <850000 850000 1000000>;
1145
-			opp-microvolt-L1 = <825000 825000 1000000>;
1146
-			opp-microvolt-L2 = <825000 825000 1000000>;
1147
1138
 		};
1148
1139
 		opp-600000000 {
1149
1140
 			opp-hz = /bits/ 64 <600000000>;
1150
-			opp-microvolt = <875000 875000 1000000>;
1151
-			opp-microvolt-L0 = <875000 875000 1000000>;
1152
-			opp-microvolt-L1 = <825000 825000 1000000>;
1153
-			opp-microvolt-L2 = <825000 825000 1000000>;
1141
+			opp-microvolt = <850000 850000 1000000>;
1154
1142
 		};
1155
1143
 		opp-700000000 {
1156
1144
 			opp-hz = /bits/ 64 <700000000>;
1157
-			opp-microvolt = <900000 900000 1000000>;
1158
-			opp-microvolt-L0 = <900000 900000 1000000>;
1145
+			opp-microvolt = <875000 875000 1000000>;
1146
+			opp-microvolt-L0 = <875000 875000 1000000>;
1159
1147
 			opp-microvolt-L1 = <850000 850000 1000000>;
1160
1148
 			opp-microvolt-L2 = <850000 850000 1000000>;
1149
+			opp-microvolt-L3 = <850000 850000 1000000>;
1161
1150
 		};
1162
1151
 		opp-800000000 {
1163
1152
 			opp-hz = /bits/ 64 <800000000>;
1164
1153
 			opp-microvolt = <925000 925000 1000000>;
1165
1154
 			opp-microvolt-L0 = <925000 925000 1000000>;
1166
-			opp-microvolt-L1 = <875000 875000 1000000>;
1155
+			opp-microvolt-L1 = <900000 900000 1000000>;
1167
1156
 			opp-microvolt-L2 = <875000 875000 1000000>;
1157
+			opp-microvolt-L3 = <875000 875000 1000000>;
1168
1158
 		};
1169
1159
 		opp-900000000 {
1170
1160
 			opp-hz = /bits/ 64 <900000000>;
1171
1161
 			opp-microvolt = <975000 975000 1000000>;
1172
1162
 			opp-microvolt-L0 = <975000 975000 1000000>;
1173
-			opp-microvolt-L1 = <925000 925000 1000000>;
1174
-			opp-microvolt-L2 = <900000 900000 1000000>;
1163
+			opp-microvolt-L1 = <950000 950000 1000000>;
1164
+			opp-microvolt-L2 = <925000 925000 1000000>;
1165
+			opp-microvolt-L3 = <900000 900000 1000000>;
1175
1166
 		};
1176
1167
 		opp-1000000000 {
1177
1168
 			opp-hz = /bits/ 64 <1000000000>;
1178
1169
 			opp-microvolt = <1000000 1000000 1000000>;
1179
1170
 			opp-microvolt-L0 = <1000000 1000000 1000000>;
1180
-			opp-microvolt-L1 = <950000 950000 1000000>;
1181
-			opp-microvolt-L2 = <925000 925000 1000000>;
1171
+			opp-microvolt-L1 = <975000 975000 1000000>;
1172
+			opp-microvolt-L2 = <950000 950000 1000000>;
1173
+			opp-microvolt-L3 = <925000 925000 1000000>;
1182
1174
 			status = "disabled";
1183
1175
 		};
1184
1176
 	};
..
..
@@ -1209,8 +1201,8 @@
1209
1201
 			opp-hz = /bits/ 64 <700000000>;
1210
1202
 			opp-microvolt = <900000>;
1211
1203
 			opp-microvolt-L0 = <900000>;
1212
-			opp-microvolt-L1 = <850000>;
1213
-			opp-microvolt-L2 = <850000>;
1204
+			opp-microvolt-L1 = <875000>;
1205
+			opp-microvolt-L2 = <875000>;
1214
1206
 		};
1215
1207
 		opp-900000000 {
1216
1208
 			opp-hz = /bits/ 64 <900000000>;
..
..
@@ -1271,56 +1263,58 @@
1271
1263
 		compatible = "operating-points-v2";
1272
1264
 
1273
1265
 		mbist-vmin = <825000 900000 950000>;
1274
-		nvmem-cells = <&gpu_leakage>, <&core_pvtm>, <&mbist_vmin>;
1275
-		nvmem-cell-names = "leakage", "pvtm", "mbist-vmin";
1266
+		nvmem-cells = <&gpu_leakage>, <&core_pvtm>, <&mbist_vmin>, <&gpu_opp_info>;
1267
+		nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info";
1268
+		rockchip,max-volt = <1000000>;
1269
+		rockchip,temp-hysteresis = <5000>;
1270
+		rockchip,low-temp = <0>;
1271
+		rockchip,low-temp-adjust-volt = <
1272
+			/* MHz    MHz    uV */
1273
+			   0      800    50000
1274
+		>;
1276
1275
 		rockchip,pvtm-voltage-sel = <
1277
1276
 			0        84000   0
1278
-			84001    91000   1
1279
-			91001    100000  2
1277
+			84001    87000   1
1278
+			87001    91000   2
1279
+			91001    100000  3
1280
1280
 		>;
1281
1281
 		rockchip,pvtm-ch = <0 5>;
1282
1282
 
1283
1283
 		opp-200000000 {
1284
1284
 			opp-hz = /bits/ 64 <200000000>;
1285
-			opp-microvolt = <850000>;
1286
-			opp-microvolt-L0 = <850000>;
1287
-			opp-microvolt-L1 = <825000>;
1288
-			opp-microvolt-L2 = <825000>;
1285
+			opp-microvolt = <850000 850000 1000000>;
1289
1286
 		};
1290
1287
 		opp-300000000 {
1291
1288
 			opp-hz = /bits/ 64 <300000000>;
1292
-			opp-microvolt = <850000>;
1293
-			opp-microvolt-L0 = <850000>;
1294
-			opp-microvolt-L1 = <825000>;
1295
-			opp-microvolt-L2 = <825000>;
1289
+			opp-microvolt = <850000 850000 1000000>;
1296
1290
 		};
1297
1291
 		opp-400000000 {
1298
1292
 			opp-hz = /bits/ 64 <400000000>;
1299
-			opp-microvolt = <850000>;
1300
-			opp-microvolt-L0 = <850000>;
1301
-			opp-microvolt-L1 = <825000>;
1302
-			opp-microvolt-L2 = <825000>;
1293
+			opp-microvolt = <850000 850000 1000000>;
1303
1294
 		};
1304
1295
 		opp-600000000 {
1305
1296
 			opp-hz = /bits/ 64 <600000000>;
1306
-			opp-microvolt = <875000>;
1307
-			opp-microvolt-L0 = <875000>;
1308
-			opp-microvolt-L1 = <825000>;
1309
-			opp-microvolt-L2 = <825000>;
1297
+			opp-microvolt = <900000 900000 1000000>;
1298
+			opp-microvolt-L0 = <900000 900000 1000000>;
1299
+			opp-microvolt-L1 = <875000 875000 1000000>;
1300
+			opp-microvolt-L2 = <850000 850000 1000000>;
1301
+			opp-microvolt-L3 = <850000 850000 1000000>;
1310
1302
 		};
1311
1303
 		opp-700000000 {
1312
1304
 			opp-hz = /bits/ 64 <700000000>;
1313
-			opp-microvolt = <950000>;
1314
-			opp-microvolt-L0 = <950000>;
1315
-			opp-microvolt-L1 = <900000>;
1316
-			opp-microvolt-L2 = <850000>;
1305
+			opp-microvolt = <950000 950000 1000000>;
1306
+			opp-microvolt-L0 = <950000 950000 1000000>;
1307
+			opp-microvolt-L1 = <925000 925000 1000000>;
1308
+			opp-microvolt-L2 = <900000 900000 1000000>;
1309
+			opp-microvolt-L3 = <875000 875000 1000000>;
1317
1310
 		};
1318
1311
 		opp-800000000 {
1319
1312
 			opp-hz = /bits/ 64 <800000000>;
1320
-			opp-microvolt = <1000000>;
1321
-			opp-microvolt-L0 = <1000000>;
1322
-			opp-microvolt-L1 = <950000>;
1323
-			opp-microvolt-L2 = <900000>;
1313
+			opp-microvolt = <1000000 1000000 1000000>;
1314
+			opp-microvolt-L0 = <1000000 1000000 1000000>;
1315
+			opp-microvolt-L1 = <975000 975000 1000000>;
1316
+			opp-microvolt-L2 = <950000 950000 1000000>;
1317
+			opp-microvolt-L3 = <925000 925000 1000000>;
1324
1318
 		};
1325
1319
 	};
1326
1320
 
..
..
@@ -1380,6 +1374,7 @@
1380
1374
 		clock-names = "aclk", "iface";
1381
1375
 		clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
1382
1376
 		power-domains = <&power RK3568_PD_VPU>;
1377
+		rockchip,shootdown-entire;
1383
1378
 		#iommu-cells = <0>;
1384
1379
 		status = "disabled";
1385
1380
 	};
..
..
@@ -1432,6 +1427,7 @@
1432
1427
 		clock-names = "aclk", "iface";
1433
1428
 		clocks = <&cru ACLK_JDEC>, <&cru HCLK_JDEC>;
1434
1429
 		power-domains = <&power RK3568_PD_RGA>;
1430
+		rockchip,shootdown-entire;
1435
1431
 		#iommu-cells = <0>;
1436
1432
 		status = "disabled";
1437
1433
 	};
..
..
@@ -1461,6 +1457,7 @@
1461
1457
 		clock-names = "aclk", "iface";
1462
1458
 		clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>;
1463
1459
 		power-domains = <&power RK3568_PD_RGA>;
1460
+		rockchip,shootdown-entire;
1464
1461
 		#iommu-cells = <0>;
1465
1462
 		status = "disabled";
1466
1463
 	};
..
..
@@ -1491,6 +1488,7 @@
1491
1488
 		clock-names = "aclk", "iface";
1492
1489
 		#iommu-cells = <0>;
1493
1490
 		power-domains = <&power RK3568_PD_RGA>;
1491
+		rockchip,shootdown-entire;
1494
1492
 		//rockchip,disable-device-link-resume;
1495
1493
 		status = "disabled";
1496
1494
 	};
..
..
@@ -1544,8 +1542,8 @@
1544
1542
 			opp-hz = /bits/ 64 <297000000>;
1545
1543
 			opp-microvolt = <900000>;
1546
1544
 			opp-microvolt-L0 = <900000>;
1547
-			opp-microvolt-L1 = <850000>;
1548
-			opp-microvolt-L2 = <850000>;
1545
+			opp-microvolt-L1 = <875000>;
1546
+			opp-microvolt-L2 = <875000>;
1549
1547
 		};
1550
1548
 		opp-400000000 {
1551
1549
 			opp-hz = /bits/ 64 <400000000>;
..
..
@@ -1566,6 +1564,7 @@
1566
1564
 		clock-names = "aclk", "iface";
1567
1565
 		rockchip,disable-mmu-reset;
1568
1566
 		rockchip,enable-cmd-retry;
1567
+		rockchip,shootdown-entire;
1569
1568
 		#iommu-cells = <0>;
1570
1569
 		power-domains = <&power RK3568_PD_RKVENC>;
1571
1570
 		status = "disabled";
..
..
@@ -1629,7 +1628,7 @@
1629
1628
 			opp-hz = /bits/ 64 <297000000>;
1630
1629
 			opp-microvolt = <900000>;
1631
1630
 			opp-microvolt-L0 = <900000>;
1632
-			opp-microvolt-L1 = <850000>;
1631
+			opp-microvolt-L1 = <875000>;
1633
1632
 		};
1634
1633
 		opp-400000000 {
1635
1634
 			opp-hz = /bits/ 64 <400000000>;
..
..
@@ -1645,6 +1644,7 @@
1645
1644
 		clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
1646
1645
 		clock-names = "aclk", "iface";
1647
1646
 		power-domains = <&power RK3568_PD_RKVDEC>;
1647
+		rockchip,shootdown-entire;
1648
1648
 		#iommu-cells = <0>;
1649
1649
 		status = "disabled";
1650
1650
 	};
..
..
@@ -1739,7 +1739,7 @@
1739
1739
 		rockchip,grf = <&grf>;
1740
1740
 		power-domains = <&power RK3568_PD_VI>;
1741
1741
 		iommus = <&rkisp_mmu>;
1742
-		rockchip,iq-feature = /bits/ 64 <0x3FBFFFE67FF>;
1742
+		rockchip,iq-feature = /bits/ 64 <0x1BFBFFFE67FF>;
1743
1743
 		status = "disabled";
1744
1744
 	};
1745
1745
 
..
..
@@ -1768,6 +1768,13 @@
1768
1768
 		status = "disabled";
1769
1769
 	};
1770
1770
 
1771
+	gmac_uio1: uio@fe010000 {
1772
+		compatible = "rockchip,uio-gmac";
1773
+		reg = <0x0 0xfe010000 0x0 0x10000>;
1774
+		rockchip,ethernet = <&gmac1>;
1775
+		status = "disabled";
1776
+	};
1777
+
1771
1778
 	gmac1: ethernet@fe010000 {
1772
1779
 		compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
1773
1780
 		reg = <0x0 0xfe010000 0x0 0x10000>;
..
..
@@ -1779,12 +1786,12 @@
1779
1786
 			 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>,
1780
1787
 			 <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>,
1781
1788
 			 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>,
1782
-			 <&cru PCLK_XPCS>;
1789
+			 <&cru PCLK_XPCS>, <&cru CLK_XPCS_EEE>;
1783
1790
 		clock-names = "stmmaceth", "mac_clk_rx",
1784
1791
 			      "mac_clk_tx", "clk_mac_refout",
1785
1792
 			      "aclk_mac", "pclk_mac",
1786
1793
 			      "clk_mac_speed", "ptp_ref",
1787
-			      "pclk_xpcs";
1794
+			      "pclk_xpcs", "clk_xpcs_eee";
1788
1795
 		resets = <&cru SRST_A_GMAC1>;
1789
1796
 		reset-names = "stmmaceth";
1790
1797
 
..
..
@@ -2005,7 +2012,8 @@
2005
2012
 	hdmi: hdmi@fe0a0000 {
2006
2013
 		compatible = "rockchip,rk3568-dw-hdmi";
2007
2014
 		reg = <0x0 0xfe0a0000 0x0 0x20000>;
2008
-		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
2015
+		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
2016
+		interrupt-names = "hdmi", "hdmi_wakeup";
2009
2017
 		clocks = <&cru PCLK_HDMI_HOST>,
2010
2018
 			 <&cru CLK_HDMI_SFR>,
2011
2019
 			 <&cru CLK_HDMI_CEC>,
..
..
@@ -2324,8 +2332,9 @@
2324
2332
 		compatible = "operating-points-v2";
2325
2333
 
2326
2334
 		mbist-vmin = <825000 900000 950000>;
2327
-		nvmem-cells = <&log_leakage>, <&core_pvtm>, <&mbist_vmin>;
2328
-		nvmem-cell-names = "leakage", "pvtm", "mbist-vmin";
2335
+		nvmem-cells = <&log_leakage>, <&core_pvtm>, <&mbist_vmin>, <&dmc_opp_info>;
2336
+		nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info";
2337
+		rockchip,max-volt = <1000000>;
2329
2338
 		rockchip,temp-hysteresis = <5000>;
2330
2339
 		rockchip,low-temp = <0>;
2331
2340
 		rockchip,low-temp-adjust-volt = <
..
..
@@ -2344,9 +2353,9 @@
2344
2353
 
2345
2354
 		opp-1560000000 {
2346
2355
 			opp-hz = /bits/ 64 <1560000000>;
2347
-			opp-microvolt = <900000>;
2348
-			opp-microvolt-L0 = <900000>;
2349
-			opp-microvolt-L1 = <850000>;
2356
+			opp-microvolt = <900000 900000 1000000>;
2357
+			opp-microvolt-L0 = <900000 900000 1000000>;
2358
+			opp-microvolt-L1 = <875000 875000 1000000>;
2350
2359
 		};
2351
2360
 	};
2352
2361
 
..
..
@@ -2516,6 +2525,13 @@
2516
2525
 		};
2517
2526
 	};
2518
2527
 
2528
+	gmac_uio0: uio@fe2a0000 {
2529
+		compatible = "rockchip,uio-gmac";
2530
+		reg = <0x0 0xfe2a0000 0x0 0x10000>;
2531
+		rockchip,ethernet = <&gmac0>;
2532
+		status = "disabled";
2533
+	};
2534
+
2519
2535
 	gmac0: ethernet@fe2a0000 {
2520
2536
 		compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
2521
2537
 		reg = <0x0 0xfe2a0000 0x0 0x10000>;
..
..
@@ -2527,12 +2543,12 @@
2527
2543
 			 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>,
2528
2544
 			 <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>,
2529
2545
 			 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>,
2530
-			 <&cru PCLK_XPCS>;
2546
+			 <&cru PCLK_XPCS>, <&cru CLK_XPCS_EEE>;
2531
2547
 		clock-names = "stmmaceth", "mac_clk_rx",
2532
2548
 			      "mac_clk_tx", "clk_mac_refout",
2533
2549
 			      "aclk_mac", "pclk_mac",
2534
2550
 			      "clk_mac_speed", "ptp_ref",
2535
-			      "pclk_xpcs";
2551
+			      "pclk_xpcs", "clk_xpcs_eee";
2536
2552
 		resets = <&cru SRST_A_GMAC0>;
2537
2553
 		reset-names = "stmmaceth";
2538
2554
 
..
..
@@ -2717,6 +2733,18 @@
2717
2733
 		};
2718
2734
 		tsadc_trim_base: tsadc-trim-base@32 {
2719
2735
 			reg = <0x32 0x1>;
2736
+		};
2737
+		cpu_opp_info: cpu-opp-info@36 {
2738
+			reg = <0x36 0x6>;
2739
+		};
2740
+		gpu_opp_info: gpu-opp-info@3c {
2741
+			reg = <0x3c 0x6>;
2742
+		};
2743
+		npu_opp_info: npu-opp-info@42 {
2744
+			reg = <0x42 0x6>;
2745
+		};
2746
+		dmc_opp_info: dmc-opp-info@48 {
2747
+			reg = <0x48 0x6>;
2720
2748
 		};
2721
2749
 	};
2722
2750
 
..
..
@@ -3111,7 +3139,7 @@
3111
3139
 		dmas = <&dmac0 2>, <&dmac0 3>;
3112
3140
 		pinctrl-names = "default";
3113
3141
 		pinctrl-0 = <&uart1m0_xfer>;
3114
-		status = "okay";
3142
+		status = "disabled";
3115
3143
 	};
3116
3144
 
3117
3145
 	uart2: serial@fe660000 {