blame | history | patch | commit | commitdiff
hc
2023-11-06 e3e12f52b214121840b44c91de5b3e5af5d3eb84 
 kernel/arch/arm64/boot/dts/rockchip/rk3568.dtsi
old mode 100755new mode 100644
....@@ -22,7 +22,6 @@
2222 	#address-cells = <2>;
2323 	#size-cells = <2>;
2424 
25
-
2625 	aliases {
2726 		csi2dphy0 = &csi2_dphy0;
2827 		csi2dphy1 = &csi2_dphy1;
....@@ -127,12 +126,14 @@
127126 		opp-shared;
128127 
129128 		mbist-vmin = <825000 900000 950000>;
130
-		nvmem-cells = <&cpu_leakage>, <&core_pvtm>, <&mbist_vmin>;
131
-		nvmem-cell-names = "leakage", "pvtm", "mbist-vmin";
129
+		nvmem-cells = <&cpu_leakage>, <&core_pvtm>, <&mbist_vmin>, <&cpu_opp_info>;
130
+		nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info";
131
+		rockchip,max-volt = <1150000>;
132132 		rockchip,pvtm-voltage-sel = <
133133 			0        84000   0
134
-			84001    91000   1
135
-			91001    100000  2
134
+			84001    87000   1
135
+			87001    91000   2
136
+			91001    100000  3
136137 		>;
137138 		rockchip,pvtm-freq = <408000>;
138139 		rockchip,pvtm-volt = <900000>;
....@@ -147,31 +148,22 @@
147148 		rockchip,low-temp = <0>;
148149 		rockchip,low-temp-adjust-volt = <
149150 			/* MHz    MHz    uV */
150
-			   0      1608   75000
151
+			   0      1992   75000
151152 		>;
152153 
153154 		opp-408000000 {
154155 			opp-hz = /bits/ 64 <408000000>;
155156 			opp-microvolt = <850000 850000 1150000>;
156
-			opp-microvolt-L0 = <850000 850000 1150000>;
157
-			opp-microvolt-L1 = <825000 825000 1150000>;
158
-			opp-microvolt-L2 = <825000 825000 1150000>;
159157 			clock-latency-ns = <40000>;
160158 		};
161159 		opp-600000000 {
162160 			opp-hz = /bits/ 64 <600000000>;
163
-			opp-microvolt = <850000 825000 1150000>;
164
-			opp-microvolt-L0 = <850000 850000 1150000>;
165
-			opp-microvolt-L1 = <825000 825000 1150000>;
166
-			opp-microvolt-L2 = <825000 825000 1150000>;
161
+			opp-microvolt = <850000 850000 1150000>;
167162 			clock-latency-ns = <40000>;
168163 		};
169164 		opp-816000000 {
170165 			opp-hz = /bits/ 64 <816000000>;
171166 			opp-microvolt = <850000 850000 1150000>;
172
-			opp-microvolt-L0 = <850000 850000 1150000>;
173
-			opp-microvolt-L1 = <825000 825000 1150000>;
174
-			opp-microvolt-L2 = <825000 825000 1150000>;
175167 			clock-latency-ns = <40000>;
176168 			opp-suspend;
177169 		};
....@@ -179,40 +171,45 @@
179171 			opp-hz = /bits/ 64 <1104000000>;
180172 			opp-microvolt = <900000 900000 1150000>;
181173 			opp-microvolt-L0 = <900000 900000 1150000>;
182
-			opp-microvolt-L1 = <825000 825000 1150000>;
183
-			opp-microvolt-L2 = <825000 825000 1150000>;
174
+			opp-microvolt-L1 = <850000 850000 1150000>;
175
+			opp-microvolt-L2 = <850000 850000 1150000>;
176
+			opp-microvolt-L3 = <850000 850000 1150000>;
184177 			clock-latency-ns = <40000>;
185178 		};
186179 		opp-1416000000 {
187180 			opp-hz = /bits/ 64 <1416000000>;
188
-			opp-microvolt = <1000000 1000000 1150000>;
189
-			opp-microvolt-L0 = <1000000 1000000 1150000>;
190
-			opp-microvolt-L1 = <925000 925000 1150000>;
191
-			opp-microvolt-L2 = <925000 925000 1150000>;
181
+			opp-microvolt = <1025000 1025000 1150000>;
182
+			opp-microvolt-L0 = <1025000 1025000 1150000>;
183
+			opp-microvolt-L1 = <975000 975000 1150000>;
184
+			opp-microvolt-L2 = <950000 950000 1150000>;
185
+			opp-microvolt-L3 = <925000 925000 1150000>;
192186 			clock-latency-ns = <40000>;
193187 		};
194188 		opp-1608000000 {
195189 			opp-hz = /bits/ 64 <1608000000>;
196
-			opp-microvolt = <1075000 1075000 1150000>;
197
-			opp-microvolt-L0 = <1075000 1075000 1150000>;
198
-			opp-microvolt-L1 = <1000000 1000000 1150000>;
199
-			opp-microvolt-L2 = <1000000 1000000 1150000>;
190
+			opp-microvolt = <1100000 1100000 1150000>;
191
+			opp-microvolt-L0 = <1100000 1100000 1150000>;
192
+			opp-microvolt-L1 = <1050000 1050000 1150000>;
193
+			opp-microvolt-L2 = <1025000 1025000 1150000>;
194
+			opp-microvolt-L3 = <1000000 1000000 1150000>;
200195 			clock-latency-ns = <40000>;
201196 		};
202197 		opp-1800000000 {
203198 			opp-hz = /bits/ 64 <1800000000>;
204
-			opp-microvolt = <1125000 1125000 1150000>;
205
-			opp-microvolt-L0 = <1125000 1125000 1150000>;
206
-			opp-microvolt-L1 = <1050000 1050000 1150000>;
207
-			opp-microvolt-L2 = <1050000 1050000 1150000>;
199
+			opp-microvolt = <1150000 1150000 1150000>;
200
+			opp-microvolt-L0 = <1150000 1150000 1150000>;
201
+			opp-microvolt-L1 = <1100000 1100000 1150000>;
202
+			opp-microvolt-L2 = <1075000 1075000 1150000>;
203
+			opp-microvolt-L3 = <1050000 1050000 1150000>;
208204 			clock-latency-ns = <40000>;
209205 		};
210206 		opp-1992000000 {
211207 			opp-hz = /bits/ 64 <1992000000>;
212208 			opp-microvolt = <1150000 1150000 1150000>;
213209 			opp-microvolt-L0 = <1150000 1150000 1150000>;
214
-			opp-microvolt-L1 = <1100000 1100000 1150000>;
215
-			opp-microvolt-L2 = <1075000 1075000 1150000>;
210
+			opp-microvolt-L1 = <1150000 1150000 1150000>;
211
+			opp-microvolt-L2 = <1125000 1125000 1150000>;
212
+			opp-microvolt-L3 = <1100000 1100000 1150000>;
216213 			clock-latency-ns = <40000>;
217214 		};
218215 	};
....@@ -254,7 +251,7 @@
254251 				logo,kernel = "logo_kernel.bmp";
255252 				logo,mode = "center";
256253 				charge_logo,mode = "center";
257
-				connect = <&vp1_out_dsi1>;
254
+				connect = <&vp0_out_dsi1>;
258255 			};
259256 			route_edp: route-edp {
260257 				status = "disabled";
....@@ -262,7 +259,7 @@
262259 				logo,kernel = "logo_kernel.bmp";
263260 				logo,mode = "center";
264261 				charge_logo,mode = "center";
265
-				connect = <&vp1_out_edp>;
262
+				connect = <&vp0_out_edp>;
266263 			};
267264 			route_hdmi: route-hdmi {
268265 				status = "disabled";
....@@ -270,7 +267,7 @@
270267 				logo,kernel = "logo_kernel.bmp";
271268 				logo,mode = "center";
272269 				charge_logo,mode = "center";
273
-				connect = <&vp0_out_hdmi>;
270
+				connect = <&vp1_out_hdmi>;
274271 			};
275272 			route_lvds: route-lvds {
276273 				status = "disabled";
....@@ -308,7 +305,7 @@
308305 				reg = <0x14>;
309306 				#clock-cells = <1>;
310307 
311
-				rockchip,clk-init = <1416000000>;
308
+				rockchip,clk-init = <1104000000>;
312309 			};
313310 		};
314311 
....@@ -939,7 +936,7 @@
939936 		dmas = <&dmac0 0>, <&dmac0 1>;
940937 		pinctrl-names = "default";
941938 		pinctrl-0 = <&uart0_xfer>;
942
-		status = "okay";
939
+		status = "disabled";
943940 	};
944941 
945942 	pwm0: pwm@fdd70000 {
....@@ -1110,76 +1107,70 @@
11101107 		compatible = "operating-points-v2";
11111108 
11121109 		mbist-vmin = <825000 900000 950000>;
1113
-		nvmem-cells = <&npu_leakage>, <&core_pvtm>, <&mbist_vmin>;
1114
-		nvmem-cell-names = "leakage", "pvtm", "mbist-vmin";
1110
+		nvmem-cells = <&npu_leakage>, <&core_pvtm>, <&mbist_vmin>, <&npu_opp_info>;
1111
+		nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info";
1112
+		rockchip,max-volt = <1000000>;
11151113 		rockchip,temp-hysteresis = <5000>;
11161114 		rockchip,low-temp = <0>;
11171115 		rockchip,low-temp-adjust-volt = <
11181116 			/* MHz    MHz    uV */
1119
-			   0      700    50000
1117
+			   0      1000    50000
11201118 		>;
11211119 		rockchip,pvtm-voltage-sel = <
11221120 			0        84000   0
1123
-			84001    91000   1
1124
-			91001    100000  2
1121
+			84001    87000   1
1122
+			87001    91000   2
1123
+			91001    100000  3
11251124 		>;
11261125 		rockchip,pvtm-ch = <0 5>;
11271126 
11281127 		opp-200000000 {
11291128 			opp-hz = /bits/ 64 <200000000>;
11301129 			opp-microvolt = <850000 850000 1000000>;
1131
-			opp-microvolt-L0 = <850000 850000 1000000>;
1132
-			opp-microvolt-L1 = <825000 825000 1000000>;
1133
-			opp-microvolt-L2 = <825000 825000 1000000>;
11341130 		};
11351131 		opp-300000000 {
11361132 			opp-hz = /bits/ 64 <297000000>;
11371133 			opp-microvolt = <850000 850000 1000000>;
1138
-			opp-microvolt-L0 = <850000 850000 1000000>;
1139
-			opp-microvolt-L1 = <825000 825000 1000000>;
1140
-			opp-microvolt-L2 = <825000 825000 1000000>;
11411134 		};
11421135 		opp-400000000 {
11431136 			opp-hz = /bits/ 64 <400000000>;
11441137 			opp-microvolt = <850000 850000 1000000>;
1145
-			opp-microvolt-L0 = <850000 850000 1000000>;
1146
-			opp-microvolt-L1 = <825000 825000 1000000>;
1147
-			opp-microvolt-L2 = <825000 825000 1000000>;
11481138 		};
11491139 		opp-600000000 {
11501140 			opp-hz = /bits/ 64 <600000000>;
1151
-			opp-microvolt = <875000 875000 1000000>;
1152
-			opp-microvolt-L0 = <875000 875000 1000000>;
1153
-			opp-microvolt-L1 = <825000 825000 1000000>;
1154
-			opp-microvolt-L2 = <825000 825000 1000000>;
1141
+			opp-microvolt = <850000 850000 1000000>;
11551142 		};
11561143 		opp-700000000 {
11571144 			opp-hz = /bits/ 64 <700000000>;
1158
-			opp-microvolt = <900000 900000 1000000>;
1159
-			opp-microvolt-L0 = <900000 900000 1000000>;
1145
+			opp-microvolt = <875000 875000 1000000>;
1146
+			opp-microvolt-L0 = <875000 875000 1000000>;
11601147 			opp-microvolt-L1 = <850000 850000 1000000>;
11611148 			opp-microvolt-L2 = <850000 850000 1000000>;
1149
+			opp-microvolt-L3 = <850000 850000 1000000>;
11621150 		};
11631151 		opp-800000000 {
11641152 			opp-hz = /bits/ 64 <800000000>;
11651153 			opp-microvolt = <925000 925000 1000000>;
11661154 			opp-microvolt-L0 = <925000 925000 1000000>;
1167
-			opp-microvolt-L1 = <875000 875000 1000000>;
1155
+			opp-microvolt-L1 = <900000 900000 1000000>;
11681156 			opp-microvolt-L2 = <875000 875000 1000000>;
1157
+			opp-microvolt-L3 = <875000 875000 1000000>;
11691158 		};
11701159 		opp-900000000 {
11711160 			opp-hz = /bits/ 64 <900000000>;
11721161 			opp-microvolt = <975000 975000 1000000>;
11731162 			opp-microvolt-L0 = <975000 975000 1000000>;
1174
-			opp-microvolt-L1 = <925000 925000 1000000>;
1175
-			opp-microvolt-L2 = <900000 900000 1000000>;
1163
+			opp-microvolt-L1 = <950000 950000 1000000>;
1164
+			opp-microvolt-L2 = <925000 925000 1000000>;
1165
+			opp-microvolt-L3 = <900000 900000 1000000>;
11761166 		};
11771167 		opp-1000000000 {
11781168 			opp-hz = /bits/ 64 <1000000000>;
11791169 			opp-microvolt = <1000000 1000000 1000000>;
11801170 			opp-microvolt-L0 = <1000000 1000000 1000000>;
1181
-			opp-microvolt-L1 = <950000 950000 1000000>;
1182
-			opp-microvolt-L2 = <925000 925000 1000000>;
1171
+			opp-microvolt-L1 = <975000 975000 1000000>;
1172
+			opp-microvolt-L2 = <950000 950000 1000000>;
1173
+			opp-microvolt-L3 = <925000 925000 1000000>;
11831174 			status = "disabled";
11841175 		};
11851176 	};
....@@ -1210,8 +1201,8 @@
12101201 			opp-hz = /bits/ 64 <700000000>;
12111202 			opp-microvolt = <900000>;
12121203 			opp-microvolt-L0 = <900000>;
1213
-			opp-microvolt-L1 = <850000>;
1214
-			opp-microvolt-L2 = <850000>;
1204
+			opp-microvolt-L1 = <875000>;
1205
+			opp-microvolt-L2 = <875000>;
12151206 		};
12161207 		opp-900000000 {
12171208 			opp-hz = /bits/ 64 <900000000>;
....@@ -1272,56 +1263,58 @@
12721263 		compatible = "operating-points-v2";
12731264 
12741265 		mbist-vmin = <825000 900000 950000>;
1275
-		nvmem-cells = <&gpu_leakage>, <&core_pvtm>, <&mbist_vmin>;
1276
-		nvmem-cell-names = "leakage", "pvtm", "mbist-vmin";
1266
+		nvmem-cells = <&gpu_leakage>, <&core_pvtm>, <&mbist_vmin>, <&gpu_opp_info>;
1267
+		nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info";
1268
+		rockchip,max-volt = <1000000>;
1269
+		rockchip,temp-hysteresis = <5000>;
1270
+		rockchip,low-temp = <0>;
1271
+		rockchip,low-temp-adjust-volt = <
1272
+			/* MHz    MHz    uV */
1273
+			   0      800    50000
1274
+		>;
12771275 		rockchip,pvtm-voltage-sel = <
12781276 			0        84000   0
1279
-			84001    91000   1
1280
-			91001    100000  2
1277
+			84001    87000   1
1278
+			87001    91000   2
1279
+			91001    100000  3
12811280 		>;
12821281 		rockchip,pvtm-ch = <0 5>;
12831282 
12841283 		opp-200000000 {
12851284 			opp-hz = /bits/ 64 <200000000>;
1286
-			opp-microvolt = <850000>;
1287
-			opp-microvolt-L0 = <850000>;
1288
-			opp-microvolt-L1 = <825000>;
1289
-			opp-microvolt-L2 = <825000>;
1285
+			opp-microvolt = <850000 850000 1000000>;
12901286 		};
12911287 		opp-300000000 {
12921288 			opp-hz = /bits/ 64 <300000000>;
1293
-			opp-microvolt = <850000>;
1294
-			opp-microvolt-L0 = <850000>;
1295
-			opp-microvolt-L1 = <825000>;
1296
-			opp-microvolt-L2 = <825000>;
1289
+			opp-microvolt = <850000 850000 1000000>;
12971290 		};
12981291 		opp-400000000 {
12991292 			opp-hz = /bits/ 64 <400000000>;
1300
-			opp-microvolt = <850000>;
1301
-			opp-microvolt-L0 = <850000>;
1302
-			opp-microvolt-L1 = <825000>;
1303
-			opp-microvolt-L2 = <825000>;
1293
+			opp-microvolt = <850000 850000 1000000>;
13041294 		};
13051295 		opp-600000000 {
13061296 			opp-hz = /bits/ 64 <600000000>;
1307
-			opp-microvolt = <875000>;
1308
-			opp-microvolt-L0 = <875000>;
1309
-			opp-microvolt-L1 = <825000>;
1310
-			opp-microvolt-L2 = <825000>;
1297
+			opp-microvolt = <900000 900000 1000000>;
1298
+			opp-microvolt-L0 = <900000 900000 1000000>;
1299
+			opp-microvolt-L1 = <875000 875000 1000000>;
1300
+			opp-microvolt-L2 = <850000 850000 1000000>;
1301
+			opp-microvolt-L3 = <850000 850000 1000000>;
13111302 		};
13121303 		opp-700000000 {
13131304 			opp-hz = /bits/ 64 <700000000>;
1314
-			opp-microvolt = <950000>;
1315
-			opp-microvolt-L0 = <950000>;
1316
-			opp-microvolt-L1 = <900000>;
1317
-			opp-microvolt-L2 = <850000>;
1305
+			opp-microvolt = <950000 950000 1000000>;
1306
+			opp-microvolt-L0 = <950000 950000 1000000>;
1307
+			opp-microvolt-L1 = <925000 925000 1000000>;
1308
+			opp-microvolt-L2 = <900000 900000 1000000>;
1309
+			opp-microvolt-L3 = <875000 875000 1000000>;
13181310 		};
13191311 		opp-800000000 {
13201312 			opp-hz = /bits/ 64 <800000000>;
1321
-			opp-microvolt = <1000000>;
1322
-			opp-microvolt-L0 = <1000000>;
1323
-			opp-microvolt-L1 = <950000>;
1324
-			opp-microvolt-L2 = <900000>;
1313
+			opp-microvolt = <1000000 1000000 1000000>;
1314
+			opp-microvolt-L0 = <1000000 1000000 1000000>;
1315
+			opp-microvolt-L1 = <975000 975000 1000000>;
1316
+			opp-microvolt-L2 = <950000 950000 1000000>;
1317
+			opp-microvolt-L3 = <925000 925000 1000000>;
13251318 		};
13261319 	};
13271320 
....@@ -1381,6 +1374,7 @@
13811374 		clock-names = "aclk", "iface";
13821375 		clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
13831376 		power-domains = <&power RK3568_PD_VPU>;
1377
+		rockchip,shootdown-entire;
13841378 		#iommu-cells = <0>;
13851379 		status = "disabled";
13861380 	};
....@@ -1433,6 +1427,7 @@
14331427 		clock-names = "aclk", "iface";
14341428 		clocks = <&cru ACLK_JDEC>, <&cru HCLK_JDEC>;
14351429 		power-domains = <&power RK3568_PD_RGA>;
1430
+		rockchip,shootdown-entire;
14361431 		#iommu-cells = <0>;
14371432 		status = "disabled";
14381433 	};
....@@ -1462,6 +1457,7 @@
14621457 		clock-names = "aclk", "iface";
14631458 		clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>;
14641459 		power-domains = <&power RK3568_PD_RGA>;
1460
+		rockchip,shootdown-entire;
14651461 		#iommu-cells = <0>;
14661462 		status = "disabled";
14671463 	};
....@@ -1492,6 +1488,7 @@
14921488 		clock-names = "aclk", "iface";
14931489 		#iommu-cells = <0>;
14941490 		power-domains = <&power RK3568_PD_RGA>;
1491
+		rockchip,shootdown-entire;
14951492 		//rockchip,disable-device-link-resume;
14961493 		status = "disabled";
14971494 	};
....@@ -1545,8 +1542,8 @@
15451542 			opp-hz = /bits/ 64 <297000000>;
15461543 			opp-microvolt = <900000>;
15471544 			opp-microvolt-L0 = <900000>;
1548
-			opp-microvolt-L1 = <850000>;
1549
-			opp-microvolt-L2 = <850000>;
1545
+			opp-microvolt-L1 = <875000>;
1546
+			opp-microvolt-L2 = <875000>;
15501547 		};
15511548 		opp-400000000 {
15521549 			opp-hz = /bits/ 64 <400000000>;
....@@ -1567,6 +1564,7 @@
15671564 		clock-names = "aclk", "iface";
15681565 		rockchip,disable-mmu-reset;
15691566 		rockchip,enable-cmd-retry;
1567
+		rockchip,shootdown-entire;
15701568 		#iommu-cells = <0>;
15711569 		power-domains = <&power RK3568_PD_RKVENC>;
15721570 		status = "disabled";
....@@ -1630,7 +1628,7 @@
16301628 			opp-hz = /bits/ 64 <297000000>;
16311629 			opp-microvolt = <900000>;
16321630 			opp-microvolt-L0 = <900000>;
1633
-			opp-microvolt-L1 = <850000>;
1631
+			opp-microvolt-L1 = <875000>;
16341632 		};
16351633 		opp-400000000 {
16361634 			opp-hz = /bits/ 64 <400000000>;
....@@ -1646,6 +1644,7 @@
16461644 		clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
16471645 		clock-names = "aclk", "iface";
16481646 		power-domains = <&power RK3568_PD_RKVDEC>;
1647
+		rockchip,shootdown-entire;
16491648 		#iommu-cells = <0>;
16501649 		status = "disabled";
16511650 	};
....@@ -1740,7 +1739,7 @@
17401739 		rockchip,grf = <&grf>;
17411740 		power-domains = <&power RK3568_PD_VI>;
17421741 		iommus = <&rkisp_mmu>;
1743
-		rockchip,iq-feature = /bits/ 64 <0x3FBFFFE67FF>;
1742
+		rockchip,iq-feature = /bits/ 64 <0x1BFBFFFE67FF>;
17441743 		status = "disabled";
17451744 	};
17461745 
....@@ -1769,6 +1768,13 @@
17691768 		status = "disabled";
17701769 	};
17711770 
1771
+	gmac_uio1: uio@fe010000 {
1772
+		compatible = "rockchip,uio-gmac";
1773
+		reg = <0x0 0xfe010000 0x0 0x10000>;
1774
+		rockchip,ethernet = <&gmac1>;
1775
+		status = "disabled";
1776
+	};
1777
+
17721778 	gmac1: ethernet@fe010000 {
17731779 		compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
17741780 		reg = <0x0 0xfe010000 0x0 0x10000>;
....@@ -1780,12 +1786,12 @@
17801786 			 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>,
17811787 			 <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>,
17821788 			 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>,
1783
-			 <&cru PCLK_XPCS>;
1789
+			 <&cru PCLK_XPCS>, <&cru CLK_XPCS_EEE>;
17841790 		clock-names = "stmmaceth", "mac_clk_rx",
17851791 			      "mac_clk_tx", "clk_mac_refout",
17861792 			      "aclk_mac", "pclk_mac",
17871793 			      "clk_mac_speed", "ptp_ref",
1788
-			      "pclk_xpcs";
1794
+			      "pclk_xpcs", "clk_xpcs_eee";
17891795 		resets = <&cru SRST_A_GMAC1>;
17901796 		reset-names = "stmmaceth";
17911797 
....@@ -2006,7 +2012,8 @@
20062012 	hdmi: hdmi@fe0a0000 {
20072013 		compatible = "rockchip,rk3568-dw-hdmi";
20082014 		reg = <0x0 0xfe0a0000 0x0 0x20000>;
2009
-		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
2015
+		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
2016
+		interrupt-names = "hdmi", "hdmi_wakeup";
20102017 		clocks = <&cru PCLK_HDMI_HOST>,
20112018 			 <&cru CLK_HDMI_SFR>,
20122019 			 <&cru CLK_HDMI_CEC>,
....@@ -2325,8 +2332,9 @@
23252332 		compatible = "operating-points-v2";
23262333 
23272334 		mbist-vmin = <825000 900000 950000>;
2328
-		nvmem-cells = <&log_leakage>, <&core_pvtm>, <&mbist_vmin>;
2329
-		nvmem-cell-names = "leakage", "pvtm", "mbist-vmin";
2335
+		nvmem-cells = <&log_leakage>, <&core_pvtm>, <&mbist_vmin>, <&dmc_opp_info>;
2336
+		nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info";
2337
+		rockchip,max-volt = <1000000>;
23302338 		rockchip,temp-hysteresis = <5000>;
23312339 		rockchip,low-temp = <0>;
23322340 		rockchip,low-temp-adjust-volt = <
....@@ -2345,9 +2353,9 @@
23452353 
23462354 		opp-1560000000 {
23472355 			opp-hz = /bits/ 64 <1560000000>;
2348
-			opp-microvolt = <900000>;
2349
-			opp-microvolt-L0 = <900000>;
2350
-			opp-microvolt-L1 = <850000>;
2356
+			opp-microvolt = <900000 900000 1000000>;
2357
+			opp-microvolt-L0 = <900000 900000 1000000>;
2358
+			opp-microvolt-L1 = <875000 875000 1000000>;
23512359 		};
23522360 	};
23532361 
....@@ -2398,7 +2406,7 @@
23982406 		reg-names = "pcie-dbi", "pcie-apb";
23992407 		resets = <&cru SRST_PCIE20_POWERUP>;
24002408 		reset-names = "pipe";
2401
-		status = "okay";
2409
+		status = "disabled";
24022410 
24032411 		pcie2x1_intc: legacy-interrupt-controller {
24042412 			interrupt-controller;
....@@ -2517,6 +2525,13 @@
25172525 		};
25182526 	};
25192527 
2528
+	gmac_uio0: uio@fe2a0000 {
2529
+		compatible = "rockchip,uio-gmac";
2530
+		reg = <0x0 0xfe2a0000 0x0 0x10000>;
2531
+		rockchip,ethernet = <&gmac0>;
2532
+		status = "disabled";
2533
+	};
2534
+
25202535 	gmac0: ethernet@fe2a0000 {
25212536 		compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
25222537 		reg = <0x0 0xfe2a0000 0x0 0x10000>;
....@@ -2528,12 +2543,12 @@
25282543 			 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>,
25292544 			 <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>,
25302545 			 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>,
2531
-			 <&cru PCLK_XPCS>;
2546
+			 <&cru PCLK_XPCS>, <&cru CLK_XPCS_EEE>;
25322547 		clock-names = "stmmaceth", "mac_clk_rx",
25332548 			      "mac_clk_tx", "clk_mac_refout",
25342549 			      "aclk_mac", "pclk_mac",
25352550 			      "clk_mac_speed", "ptp_ref",
2536
-			      "pclk_xpcs";
2551
+			      "pclk_xpcs", "clk_xpcs_eee";
25372552 		resets = <&cru SRST_A_GMAC0>;
25382553 		reset-names = "stmmaceth";
25392554 
....@@ -2718,6 +2733,18 @@
27182733 		};
27192734 		tsadc_trim_base: tsadc-trim-base@32 {
27202735 			reg = <0x32 0x1>;
2736
+		};
2737
+		cpu_opp_info: cpu-opp-info@36 {
2738
+			reg = <0x36 0x6>;
2739
+		};
2740
+		gpu_opp_info: gpu-opp-info@3c {
2741
+			reg = <0x3c 0x6>;
2742
+		};
2743
+		npu_opp_info: npu-opp-info@42 {
2744
+			reg = <0x42 0x6>;
2745
+		};
2746
+		dmc_opp_info: dmc-opp-info@48 {
2747
+			reg = <0x48 0x6>;
27212748 		};
27222749 	};
27232750 
....@@ -3112,7 +3139,7 @@
31123139 		dmas = <&dmac0 2>, <&dmac0 3>;
31133140 		pinctrl-names = "default";
31143141 		pinctrl-0 = <&uart1m0_xfer>;
3115
-		status = "okay";
3142
+		status = "disabled";
31163143 	};
31173144 
31183145 	uart2: serial@fe660000 {