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2023-11-06 e3e12f52b214121840b44c91de5b3e5af5d3eb84 
 kernel/arch/arm64/boot/dts/rockchip/rk3568.dtsi
old mode 100755new mode 100644
....@@ -126,12 +126,14 @@
126126 		opp-shared;
127127 
128128 		mbist-vmin = <825000 900000 950000>;
129
-		nvmem-cells = <&cpu_leakage>, <&core_pvtm>, <&mbist_vmin>;
130
-		nvmem-cell-names = "leakage", "pvtm", "mbist-vmin";
129
+		nvmem-cells = <&cpu_leakage>, <&core_pvtm>, <&mbist_vmin>, <&cpu_opp_info>;
130
+		nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info";
131
+		rockchip,max-volt = <1150000>;
131132 		rockchip,pvtm-voltage-sel = <
132133 			0        84000   0
133
-			84001    91000   1
134
-			91001    100000  2
134
+			84001    87000   1
135
+			87001    91000   2
136
+			91001    100000  3
135137 		>;
136138 		rockchip,pvtm-freq = <408000>;
137139 		rockchip,pvtm-volt = <900000>;
....@@ -146,31 +148,22 @@
146148 		rockchip,low-temp = <0>;
147149 		rockchip,low-temp-adjust-volt = <
148150 			/* MHz    MHz    uV */
149
-			   0      1608   75000
151
+			   0      1992   75000
150152 		>;
151153 
152154 		opp-408000000 {
153155 			opp-hz = /bits/ 64 <408000000>;
154156 			opp-microvolt = <850000 850000 1150000>;
155
-			opp-microvolt-L0 = <850000 850000 1150000>;
156
-			opp-microvolt-L1 = <825000 825000 1150000>;
157
-			opp-microvolt-L2 = <825000 825000 1150000>;
158157 			clock-latency-ns = <40000>;
159158 		};
160159 		opp-600000000 {
161160 			opp-hz = /bits/ 64 <600000000>;
162
-			opp-microvolt = <850000 825000 1150000>;
163
-			opp-microvolt-L0 = <850000 850000 1150000>;
164
-			opp-microvolt-L1 = <825000 825000 1150000>;
165
-			opp-microvolt-L2 = <825000 825000 1150000>;
161
+			opp-microvolt = <850000 850000 1150000>;
166162 			clock-latency-ns = <40000>;
167163 		};
168164 		opp-816000000 {
169165 			opp-hz = /bits/ 64 <816000000>;
170166 			opp-microvolt = <850000 850000 1150000>;
171
-			opp-microvolt-L0 = <850000 850000 1150000>;
172
-			opp-microvolt-L1 = <825000 825000 1150000>;
173
-			opp-microvolt-L2 = <825000 825000 1150000>;
174167 			clock-latency-ns = <40000>;
175168 			opp-suspend;
176169 		};
....@@ -178,40 +171,45 @@
178171 			opp-hz = /bits/ 64 <1104000000>;
179172 			opp-microvolt = <900000 900000 1150000>;
180173 			opp-microvolt-L0 = <900000 900000 1150000>;
181
-			opp-microvolt-L1 = <825000 825000 1150000>;
182
-			opp-microvolt-L2 = <825000 825000 1150000>;
174
+			opp-microvolt-L1 = <850000 850000 1150000>;
175
+			opp-microvolt-L2 = <850000 850000 1150000>;
176
+			opp-microvolt-L3 = <850000 850000 1150000>;
183177 			clock-latency-ns = <40000>;
184178 		};
185179 		opp-1416000000 {
186180 			opp-hz = /bits/ 64 <1416000000>;
187
-			opp-microvolt = <1000000 1000000 1150000>;
188
-			opp-microvolt-L0 = <1000000 1000000 1150000>;
189
-			opp-microvolt-L1 = <925000 925000 1150000>;
190
-			opp-microvolt-L2 = <925000 925000 1150000>;
181
+			opp-microvolt = <1025000 1025000 1150000>;
182
+			opp-microvolt-L0 = <1025000 1025000 1150000>;
183
+			opp-microvolt-L1 = <975000 975000 1150000>;
184
+			opp-microvolt-L2 = <950000 950000 1150000>;
185
+			opp-microvolt-L3 = <925000 925000 1150000>;
191186 			clock-latency-ns = <40000>;
192187 		};
193188 		opp-1608000000 {
194189 			opp-hz = /bits/ 64 <1608000000>;
195
-			opp-microvolt = <1075000 1075000 1150000>;
196
-			opp-microvolt-L0 = <1075000 1075000 1150000>;
197
-			opp-microvolt-L1 = <1000000 1000000 1150000>;
198
-			opp-microvolt-L2 = <1000000 1000000 1150000>;
190
+			opp-microvolt = <1100000 1100000 1150000>;
191
+			opp-microvolt-L0 = <1100000 1100000 1150000>;
192
+			opp-microvolt-L1 = <1050000 1050000 1150000>;
193
+			opp-microvolt-L2 = <1025000 1025000 1150000>;
194
+			opp-microvolt-L3 = <1000000 1000000 1150000>;
199195 			clock-latency-ns = <40000>;
200196 		};
201197 		opp-1800000000 {
202198 			opp-hz = /bits/ 64 <1800000000>;
203
-			opp-microvolt = <1125000 1125000 1150000>;
204
-			opp-microvolt-L0 = <1125000 1125000 1150000>;
205
-			opp-microvolt-L1 = <1050000 1050000 1150000>;
206
-			opp-microvolt-L2 = <1050000 1050000 1150000>;
199
+			opp-microvolt = <1150000 1150000 1150000>;
200
+			opp-microvolt-L0 = <1150000 1150000 1150000>;
201
+			opp-microvolt-L1 = <1100000 1100000 1150000>;
202
+			opp-microvolt-L2 = <1075000 1075000 1150000>;
203
+			opp-microvolt-L3 = <1050000 1050000 1150000>;
207204 			clock-latency-ns = <40000>;
208205 		};
209206 		opp-1992000000 {
210207 			opp-hz = /bits/ 64 <1992000000>;
211208 			opp-microvolt = <1150000 1150000 1150000>;
212209 			opp-microvolt-L0 = <1150000 1150000 1150000>;
213
-			opp-microvolt-L1 = <1100000 1100000 1150000>;
214
-			opp-microvolt-L2 = <1075000 1075000 1150000>;
210
+			opp-microvolt-L1 = <1150000 1150000 1150000>;
211
+			opp-microvolt-L2 = <1125000 1125000 1150000>;
212
+			opp-microvolt-L3 = <1100000 1100000 1150000>;
215213 			clock-latency-ns = <40000>;
216214 		};
217215 	};
....@@ -256,20 +254,20 @@
256254 				connect = <&vp0_out_dsi1>;
257255 			};
258256 			route_edp: route-edp {
259
-				status = "okay";
257
+				status = "disabled";
260258 				logo,uboot = "logo.bmp";
261259 				logo,kernel = "logo_kernel.bmp";
262260 				logo,mode = "center";
263261 				charge_logo,mode = "center";
264
-				connect = <&vp1_out_edp>;
262
+				connect = <&vp0_out_edp>;
265263 			};
266264 			route_hdmi: route-hdmi {
267
-				status = "okay";
265
+				status = "disabled";
268266 				logo,uboot = "logo.bmp";
269267 				logo,kernel = "logo_kernel.bmp";
270268 				logo,mode = "center";
271269 				charge_logo,mode = "center";
272
-				connect = <&vp0_out_hdmi>;
270
+				connect = <&vp1_out_hdmi>;
273271 			};
274272 			route_lvds: route-lvds {
275273 				status = "disabled";
....@@ -307,7 +305,7 @@
307305 				reg = <0x14>;
308306 				#clock-cells = <1>;
309307 
310
-				rockchip,clk-init = <1416000000>;
308
+				rockchip,clk-init = <1104000000>;
311309 			};
312310 		};
313311 
....@@ -938,7 +936,7 @@
938936 		dmas = <&dmac0 0>, <&dmac0 1>;
939937 		pinctrl-names = "default";
940938 		pinctrl-0 = <&uart0_xfer>;
941
-		status = "okay";
939
+		status = "disabled";
942940 	};
943941 
944942 	pwm0: pwm@fdd70000 {
....@@ -1109,76 +1107,70 @@
11091107 		compatible = "operating-points-v2";
11101108 
11111109 		mbist-vmin = <825000 900000 950000>;
1112
-		nvmem-cells = <&npu_leakage>, <&core_pvtm>, <&mbist_vmin>;
1113
-		nvmem-cell-names = "leakage", "pvtm", "mbist-vmin";
1110
+		nvmem-cells = <&npu_leakage>, <&core_pvtm>, <&mbist_vmin>, <&npu_opp_info>;
1111
+		nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info";
1112
+		rockchip,max-volt = <1000000>;
11141113 		rockchip,temp-hysteresis = <5000>;
11151114 		rockchip,low-temp = <0>;
11161115 		rockchip,low-temp-adjust-volt = <
11171116 			/* MHz    MHz    uV */
1118
-			   0      700    50000
1117
+			   0      1000    50000
11191118 		>;
11201119 		rockchip,pvtm-voltage-sel = <
11211120 			0        84000   0
1122
-			84001    91000   1
1123
-			91001    100000  2
1121
+			84001    87000   1
1122
+			87001    91000   2
1123
+			91001    100000  3
11241124 		>;
11251125 		rockchip,pvtm-ch = <0 5>;
11261126 
11271127 		opp-200000000 {
11281128 			opp-hz = /bits/ 64 <200000000>;
11291129 			opp-microvolt = <850000 850000 1000000>;
1130
-			opp-microvolt-L0 = <850000 850000 1000000>;
1131
-			opp-microvolt-L1 = <825000 825000 1000000>;
1132
-			opp-microvolt-L2 = <825000 825000 1000000>;
11331130 		};
11341131 		opp-300000000 {
11351132 			opp-hz = /bits/ 64 <297000000>;
11361133 			opp-microvolt = <850000 850000 1000000>;
1137
-			opp-microvolt-L0 = <850000 850000 1000000>;
1138
-			opp-microvolt-L1 = <825000 825000 1000000>;
1139
-			opp-microvolt-L2 = <825000 825000 1000000>;
11401134 		};
11411135 		opp-400000000 {
11421136 			opp-hz = /bits/ 64 <400000000>;
11431137 			opp-microvolt = <850000 850000 1000000>;
1144
-			opp-microvolt-L0 = <850000 850000 1000000>;
1145
-			opp-microvolt-L1 = <825000 825000 1000000>;
1146
-			opp-microvolt-L2 = <825000 825000 1000000>;
11471138 		};
11481139 		opp-600000000 {
11491140 			opp-hz = /bits/ 64 <600000000>;
1150
-			opp-microvolt = <875000 875000 1000000>;
1151
-			opp-microvolt-L0 = <875000 875000 1000000>;
1152
-			opp-microvolt-L1 = <825000 825000 1000000>;
1153
-			opp-microvolt-L2 = <825000 825000 1000000>;
1141
+			opp-microvolt = <850000 850000 1000000>;
11541142 		};
11551143 		opp-700000000 {
11561144 			opp-hz = /bits/ 64 <700000000>;
1157
-			opp-microvolt = <900000 900000 1000000>;
1158
-			opp-microvolt-L0 = <900000 900000 1000000>;
1145
+			opp-microvolt = <875000 875000 1000000>;
1146
+			opp-microvolt-L0 = <875000 875000 1000000>;
11591147 			opp-microvolt-L1 = <850000 850000 1000000>;
11601148 			opp-microvolt-L2 = <850000 850000 1000000>;
1149
+			opp-microvolt-L3 = <850000 850000 1000000>;
11611150 		};
11621151 		opp-800000000 {
11631152 			opp-hz = /bits/ 64 <800000000>;
11641153 			opp-microvolt = <925000 925000 1000000>;
11651154 			opp-microvolt-L0 = <925000 925000 1000000>;
1166
-			opp-microvolt-L1 = <875000 875000 1000000>;
1155
+			opp-microvolt-L1 = <900000 900000 1000000>;
11671156 			opp-microvolt-L2 = <875000 875000 1000000>;
1157
+			opp-microvolt-L3 = <875000 875000 1000000>;
11681158 		};
11691159 		opp-900000000 {
11701160 			opp-hz = /bits/ 64 <900000000>;
11711161 			opp-microvolt = <975000 975000 1000000>;
11721162 			opp-microvolt-L0 = <975000 975000 1000000>;
1173
-			opp-microvolt-L1 = <925000 925000 1000000>;
1174
-			opp-microvolt-L2 = <900000 900000 1000000>;
1163
+			opp-microvolt-L1 = <950000 950000 1000000>;
1164
+			opp-microvolt-L2 = <925000 925000 1000000>;
1165
+			opp-microvolt-L3 = <900000 900000 1000000>;
11751166 		};
11761167 		opp-1000000000 {
11771168 			opp-hz = /bits/ 64 <1000000000>;
11781169 			opp-microvolt = <1000000 1000000 1000000>;
11791170 			opp-microvolt-L0 = <1000000 1000000 1000000>;
1180
-			opp-microvolt-L1 = <950000 950000 1000000>;
1181
-			opp-microvolt-L2 = <925000 925000 1000000>;
1171
+			opp-microvolt-L1 = <975000 975000 1000000>;
1172
+			opp-microvolt-L2 = <950000 950000 1000000>;
1173
+			opp-microvolt-L3 = <925000 925000 1000000>;
11821174 			status = "disabled";
11831175 		};
11841176 	};
....@@ -1209,8 +1201,8 @@
12091201 			opp-hz = /bits/ 64 <700000000>;
12101202 			opp-microvolt = <900000>;
12111203 			opp-microvolt-L0 = <900000>;
1212
-			opp-microvolt-L1 = <850000>;
1213
-			opp-microvolt-L2 = <850000>;
1204
+			opp-microvolt-L1 = <875000>;
1205
+			opp-microvolt-L2 = <875000>;
12141206 		};
12151207 		opp-900000000 {
12161208 			opp-hz = /bits/ 64 <900000000>;
....@@ -1271,56 +1263,58 @@
12711263 		compatible = "operating-points-v2";
12721264 
12731265 		mbist-vmin = <825000 900000 950000>;
1274
-		nvmem-cells = <&gpu_leakage>, <&core_pvtm>, <&mbist_vmin>;
1275
-		nvmem-cell-names = "leakage", "pvtm", "mbist-vmin";
1266
+		nvmem-cells = <&gpu_leakage>, <&core_pvtm>, <&mbist_vmin>, <&gpu_opp_info>;
1267
+		nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info";
1268
+		rockchip,max-volt = <1000000>;
1269
+		rockchip,temp-hysteresis = <5000>;
1270
+		rockchip,low-temp = <0>;
1271
+		rockchip,low-temp-adjust-volt = <
1272
+			/* MHz    MHz    uV */
1273
+			   0      800    50000
1274
+		>;
12761275 		rockchip,pvtm-voltage-sel = <
12771276 			0        84000   0
1278
-			84001    91000   1
1279
-			91001    100000  2
1277
+			84001    87000   1
1278
+			87001    91000   2
1279
+			91001    100000  3
12801280 		>;
12811281 		rockchip,pvtm-ch = <0 5>;
12821282 
12831283 		opp-200000000 {
12841284 			opp-hz = /bits/ 64 <200000000>;
1285
-			opp-microvolt = <850000>;
1286
-			opp-microvolt-L0 = <850000>;
1287
-			opp-microvolt-L1 = <825000>;
1288
-			opp-microvolt-L2 = <825000>;
1285
+			opp-microvolt = <850000 850000 1000000>;
12891286 		};
12901287 		opp-300000000 {
12911288 			opp-hz = /bits/ 64 <300000000>;
1292
-			opp-microvolt = <850000>;
1293
-			opp-microvolt-L0 = <850000>;
1294
-			opp-microvolt-L1 = <825000>;
1295
-			opp-microvolt-L2 = <825000>;
1289
+			opp-microvolt = <850000 850000 1000000>;
12961290 		};
12971291 		opp-400000000 {
12981292 			opp-hz = /bits/ 64 <400000000>;
1299
-			opp-microvolt = <850000>;
1300
-			opp-microvolt-L0 = <850000>;
1301
-			opp-microvolt-L1 = <825000>;
1302
-			opp-microvolt-L2 = <825000>;
1293
+			opp-microvolt = <850000 850000 1000000>;
13031294 		};
13041295 		opp-600000000 {
13051296 			opp-hz = /bits/ 64 <600000000>;
1306
-			opp-microvolt = <875000>;
1307
-			opp-microvolt-L0 = <875000>;
1308
-			opp-microvolt-L1 = <825000>;
1309
-			opp-microvolt-L2 = <825000>;
1297
+			opp-microvolt = <900000 900000 1000000>;
1298
+			opp-microvolt-L0 = <900000 900000 1000000>;
1299
+			opp-microvolt-L1 = <875000 875000 1000000>;
1300
+			opp-microvolt-L2 = <850000 850000 1000000>;
1301
+			opp-microvolt-L3 = <850000 850000 1000000>;
13101302 		};
13111303 		opp-700000000 {
13121304 			opp-hz = /bits/ 64 <700000000>;
1313
-			opp-microvolt = <950000>;
1314
-			opp-microvolt-L0 = <950000>;
1315
-			opp-microvolt-L1 = <900000>;
1316
-			opp-microvolt-L2 = <850000>;
1305
+			opp-microvolt = <950000 950000 1000000>;
1306
+			opp-microvolt-L0 = <950000 950000 1000000>;
1307
+			opp-microvolt-L1 = <925000 925000 1000000>;
1308
+			opp-microvolt-L2 = <900000 900000 1000000>;
1309
+			opp-microvolt-L3 = <875000 875000 1000000>;
13171310 		};
13181311 		opp-800000000 {
13191312 			opp-hz = /bits/ 64 <800000000>;
1320
-			opp-microvolt = <1000000>;
1321
-			opp-microvolt-L0 = <1000000>;
1322
-			opp-microvolt-L1 = <950000>;
1323
-			opp-microvolt-L2 = <900000>;
1313
+			opp-microvolt = <1000000 1000000 1000000>;
1314
+			opp-microvolt-L0 = <1000000 1000000 1000000>;
1315
+			opp-microvolt-L1 = <975000 975000 1000000>;
1316
+			opp-microvolt-L2 = <950000 950000 1000000>;
1317
+			opp-microvolt-L3 = <925000 925000 1000000>;
13241318 		};
13251319 	};
13261320 
....@@ -1380,6 +1374,7 @@
13801374 		clock-names = "aclk", "iface";
13811375 		clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
13821376 		power-domains = <&power RK3568_PD_VPU>;
1377
+		rockchip,shootdown-entire;
13831378 		#iommu-cells = <0>;
13841379 		status = "disabled";
13851380 	};
....@@ -1432,6 +1427,7 @@
14321427 		clock-names = "aclk", "iface";
14331428 		clocks = <&cru ACLK_JDEC>, <&cru HCLK_JDEC>;
14341429 		power-domains = <&power RK3568_PD_RGA>;
1430
+		rockchip,shootdown-entire;
14351431 		#iommu-cells = <0>;
14361432 		status = "disabled";
14371433 	};
....@@ -1461,6 +1457,7 @@
14611457 		clock-names = "aclk", "iface";
14621458 		clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>;
14631459 		power-domains = <&power RK3568_PD_RGA>;
1460
+		rockchip,shootdown-entire;
14641461 		#iommu-cells = <0>;
14651462 		status = "disabled";
14661463 	};
....@@ -1491,6 +1488,7 @@
14911488 		clock-names = "aclk", "iface";
14921489 		#iommu-cells = <0>;
14931490 		power-domains = <&power RK3568_PD_RGA>;
1491
+		rockchip,shootdown-entire;
14941492 		//rockchip,disable-device-link-resume;
14951493 		status = "disabled";
14961494 	};
....@@ -1544,8 +1542,8 @@
15441542 			opp-hz = /bits/ 64 <297000000>;
15451543 			opp-microvolt = <900000>;
15461544 			opp-microvolt-L0 = <900000>;
1547
-			opp-microvolt-L1 = <850000>;
1548
-			opp-microvolt-L2 = <850000>;
1545
+			opp-microvolt-L1 = <875000>;
1546
+			opp-microvolt-L2 = <875000>;
15491547 		};
15501548 		opp-400000000 {
15511549 			opp-hz = /bits/ 64 <400000000>;
....@@ -1566,6 +1564,7 @@
15661564 		clock-names = "aclk", "iface";
15671565 		rockchip,disable-mmu-reset;
15681566 		rockchip,enable-cmd-retry;
1567
+		rockchip,shootdown-entire;
15691568 		#iommu-cells = <0>;
15701569 		power-domains = <&power RK3568_PD_RKVENC>;
15711570 		status = "disabled";
....@@ -1629,7 +1628,7 @@
16291628 			opp-hz = /bits/ 64 <297000000>;
16301629 			opp-microvolt = <900000>;
16311630 			opp-microvolt-L0 = <900000>;
1632
-			opp-microvolt-L1 = <850000>;
1631
+			opp-microvolt-L1 = <875000>;
16331632 		};
16341633 		opp-400000000 {
16351634 			opp-hz = /bits/ 64 <400000000>;
....@@ -1645,6 +1644,7 @@
16451644 		clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
16461645 		clock-names = "aclk", "iface";
16471646 		power-domains = <&power RK3568_PD_RKVDEC>;
1647
+		rockchip,shootdown-entire;
16481648 		#iommu-cells = <0>;
16491649 		status = "disabled";
16501650 	};
....@@ -1739,7 +1739,7 @@
17391739 		rockchip,grf = <&grf>;
17401740 		power-domains = <&power RK3568_PD_VI>;
17411741 		iommus = <&rkisp_mmu>;
1742
-		rockchip,iq-feature = /bits/ 64 <0x3FBFFFE67FF>;
1742
+		rockchip,iq-feature = /bits/ 64 <0x1BFBFFFE67FF>;
17431743 		status = "disabled";
17441744 	};
17451745 
....@@ -1768,6 +1768,13 @@
17681768 		status = "disabled";
17691769 	};
17701770 
1771
+	gmac_uio1: uio@fe010000 {
1772
+		compatible = "rockchip,uio-gmac";
1773
+		reg = <0x0 0xfe010000 0x0 0x10000>;
1774
+		rockchip,ethernet = <&gmac1>;
1775
+		status = "disabled";
1776
+	};
1777
+
17711778 	gmac1: ethernet@fe010000 {
17721779 		compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
17731780 		reg = <0x0 0xfe010000 0x0 0x10000>;
....@@ -1779,12 +1786,12 @@
17791786 			 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>,
17801787 			 <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>,
17811788 			 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>,
1782
-			 <&cru PCLK_XPCS>;
1789
+			 <&cru PCLK_XPCS>, <&cru CLK_XPCS_EEE>;
17831790 		clock-names = "stmmaceth", "mac_clk_rx",
17841791 			      "mac_clk_tx", "clk_mac_refout",
17851792 			      "aclk_mac", "pclk_mac",
17861793 			      "clk_mac_speed", "ptp_ref",
1787
-			      "pclk_xpcs";
1794
+			      "pclk_xpcs", "clk_xpcs_eee";
17881795 		resets = <&cru SRST_A_GMAC1>;
17891796 		reset-names = "stmmaceth";
17901797 
....@@ -2005,7 +2012,8 @@
20052012 	hdmi: hdmi@fe0a0000 {
20062013 		compatible = "rockchip,rk3568-dw-hdmi";
20072014 		reg = <0x0 0xfe0a0000 0x0 0x20000>;
2008
-		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
2015
+		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
2016
+		interrupt-names = "hdmi", "hdmi_wakeup";
20092017 		clocks = <&cru PCLK_HDMI_HOST>,
20102018 			 <&cru CLK_HDMI_SFR>,
20112019 			 <&cru CLK_HDMI_CEC>,
....@@ -2324,8 +2332,9 @@
23242332 		compatible = "operating-points-v2";
23252333 
23262334 		mbist-vmin = <825000 900000 950000>;
2327
-		nvmem-cells = <&log_leakage>, <&core_pvtm>, <&mbist_vmin>;
2328
-		nvmem-cell-names = "leakage", "pvtm", "mbist-vmin";
2335
+		nvmem-cells = <&log_leakage>, <&core_pvtm>, <&mbist_vmin>, <&dmc_opp_info>;
2336
+		nvmem-cell-names = "leakage", "pvtm", "mbist-vmin", "opp-info";
2337
+		rockchip,max-volt = <1000000>;
23292338 		rockchip,temp-hysteresis = <5000>;
23302339 		rockchip,low-temp = <0>;
23312340 		rockchip,low-temp-adjust-volt = <
....@@ -2344,9 +2353,9 @@
23442353 
23452354 		opp-1560000000 {
23462355 			opp-hz = /bits/ 64 <1560000000>;
2347
-			opp-microvolt = <900000>;
2348
-			opp-microvolt-L0 = <900000>;
2349
-			opp-microvolt-L1 = <850000>;
2356
+			opp-microvolt = <900000 900000 1000000>;
2357
+			opp-microvolt-L0 = <900000 900000 1000000>;
2358
+			opp-microvolt-L1 = <875000 875000 1000000>;
23502359 		};
23512360 	};
23522361 
....@@ -2397,7 +2406,7 @@
23972406 		reg-names = "pcie-dbi", "pcie-apb";
23982407 		resets = <&cru SRST_PCIE20_POWERUP>;
23992408 		reset-names = "pipe";
2400
-		status = "okay";
2409
+		status = "disabled";
24012410 
24022411 		pcie2x1_intc: legacy-interrupt-controller {
24032412 			interrupt-controller;
....@@ -2516,6 +2525,13 @@
25162525 		};
25172526 	};
25182527 
2528
+	gmac_uio0: uio@fe2a0000 {
2529
+		compatible = "rockchip,uio-gmac";
2530
+		reg = <0x0 0xfe2a0000 0x0 0x10000>;
2531
+		rockchip,ethernet = <&gmac0>;
2532
+		status = "disabled";
2533
+	};
2534
+
25192535 	gmac0: ethernet@fe2a0000 {
25202536 		compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
25212537 		reg = <0x0 0xfe2a0000 0x0 0x10000>;
....@@ -2527,12 +2543,12 @@
25272543 			 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_MAC0_REFOUT>,
25282544 			 <&cru ACLK_GMAC0>, <&cru PCLK_GMAC0>,
25292545 			 <&cru SCLK_GMAC0_RX_TX>, <&cru CLK_GMAC0_PTP_REF>,
2530
-			 <&cru PCLK_XPCS>;
2546
+			 <&cru PCLK_XPCS>, <&cru CLK_XPCS_EEE>;
25312547 		clock-names = "stmmaceth", "mac_clk_rx",
25322548 			      "mac_clk_tx", "clk_mac_refout",
25332549 			      "aclk_mac", "pclk_mac",
25342550 			      "clk_mac_speed", "ptp_ref",
2535
-			      "pclk_xpcs";
2551
+			      "pclk_xpcs", "clk_xpcs_eee";
25362552 		resets = <&cru SRST_A_GMAC0>;
25372553 		reset-names = "stmmaceth";
25382554 
....@@ -2717,6 +2733,18 @@
27172733 		};
27182734 		tsadc_trim_base: tsadc-trim-base@32 {
27192735 			reg = <0x32 0x1>;
2736
+		};
2737
+		cpu_opp_info: cpu-opp-info@36 {
2738
+			reg = <0x36 0x6>;
2739
+		};
2740
+		gpu_opp_info: gpu-opp-info@3c {
2741
+			reg = <0x3c 0x6>;
2742
+		};
2743
+		npu_opp_info: npu-opp-info@42 {
2744
+			reg = <0x42 0x6>;
2745
+		};
2746
+		dmc_opp_info: dmc-opp-info@48 {
2747
+			reg = <0x48 0x6>;
27202748 		};
27212749 	};
27222750 
....@@ -3111,7 +3139,7 @@
31113139 		dmas = <&dmac0 2>, <&dmac0 3>;
31123140 		pinctrl-names = "default";
31133141 		pinctrl-0 = <&uart1m0_xfer>;
3114
-		status = "okay";
3142
+		status = "disabled";
31153143 	};
31163144 
31173145 	uart2: serial@fe660000 {