rk3568 rt init

hc

2023-11-06 e3e12f52b214121840b44c91de5b3e5af5d3eb84

 kernel/arch/arm64/boot/dts/rockchip/px30s-dram-default-timing.dtsi
..
..
@@ -310,12 +310,12 @@
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 		dram_dll_dis_freq = <IGNORE_THIS>;
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 		phy_dll_dis_freq = <IGNORE_THIS>;
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 		/* drv when odt on */
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-		phy_dq_drv_odten = <35>;
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+		phy_dq_drv_odten = <44>;
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 		phy_ca_drv_odten = <38>;
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 		phy_clk_drv_odten = <47>;
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 		dram_dq_drv_odten = <40>;
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 		/* drv when odt off */
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-		phy_dq_drv_odtoff = <35>;
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+		phy_dq_drv_odtoff = <44>;
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 		phy_ca_drv_odtoff = <38>;
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 		phy_clk_drv_odtoff = <47>;
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 		dram_dq_drv_odtoff = <40>;
..
..
@@ -328,11 +328,11 @@
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 		dram_dq_odt_en_freq = <800>;
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 		phy_odt_en_freq = <800>;
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 		/* slew rate when odt enable */
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-		phy_dq_sr_odten = <0x0>;
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+		phy_dq_sr_odten = <0x7>;
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 		phy_ca_sr_odten = <0x1>;
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 		phy_clk_sr_odten = <0x1>;
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 		/* slew rate when odt disable */
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-		phy_dq_sr_odtoff = <0x0>;
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+		phy_dq_sr_odtoff = <0x7>;
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 		phy_ca_sr_odtoff = <0x1>;
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 		phy_clk_sr_odtoff = <0x1>;
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 		/* ssmod setting*/
..
..
@@ -371,7 +371,7 @@
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 		lp4_dq_vref_odten = <276>;
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 		lp4_ca_vref_odten = <380>;
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 		/* lp4 vref info when odt disable */
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-		phy_lp4_dq_vref_odtoff = <340>;
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+		phy_lp4_dq_vref_odtoff = <420>;
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 		lp4_dq_vref_odtoff = <420>;
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 		lp4_ca_vref_odtoff = <420>;
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 	};