hc
2023-11-06 e3e12f52b214121840b44c91de5b3e5af5d3eb84
kernel/arch/arm/mach-qcom/platsmp.c
....@@ -46,7 +46,7 @@
4646
4747 extern void secondary_startup_arm(void);
4848
49
-static DEFINE_SPINLOCK(boot_lock);
49
+static DEFINE_RAW_SPINLOCK(boot_lock);
5050
5151 #ifdef CONFIG_HOTPLUG_CPU
5252 static void qcom_cpu_die(unsigned int cpu)
....@@ -60,8 +60,8 @@
6060 /*
6161 * Synchronise with the boot thread.
6262 */
63
- spin_lock(&boot_lock);
64
- spin_unlock(&boot_lock);
63
+ raw_spin_lock(&boot_lock);
64
+ raw_spin_unlock(&boot_lock);
6565 }
6666
6767 static int scss_release_secondary(unsigned int cpu)
....@@ -284,7 +284,7 @@
284284 * set synchronisation state between this boot processor
285285 * and the secondary one
286286 */
287
- spin_lock(&boot_lock);
287
+ raw_spin_lock(&boot_lock);
288288
289289 /*
290290 * Send the secondary CPU a soft interrupt, thereby causing
....@@ -297,7 +297,7 @@
297297 * now the secondary core is starting up let it run its
298298 * calibrations, then wait for it to finish
299299 */
300
- spin_unlock(&boot_lock);
300
+ raw_spin_unlock(&boot_lock);
301301
302302 return ret;
303303 }