.. | .. |
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69 | 69 | .startup_addr = omap5_secondary_startup, |
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70 | 70 | }; |
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71 | 71 | |
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72 | | -static DEFINE_SPINLOCK(boot_lock); |
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| 72 | +static DEFINE_RAW_SPINLOCK(boot_lock); |
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73 | 73 | |
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74 | 74 | void __iomem *omap4_get_scu_base(void) |
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75 | 75 | { |
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.. | .. |
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177 | 177 | /* |
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178 | 178 | * Synchronise with the boot thread. |
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179 | 179 | */ |
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180 | | - spin_lock(&boot_lock); |
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181 | | - spin_unlock(&boot_lock); |
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| 180 | + raw_spin_lock(&boot_lock); |
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| 181 | + raw_spin_unlock(&boot_lock); |
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182 | 182 | } |
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183 | 183 | |
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184 | 184 | static int omap4_boot_secondary(unsigned int cpu, struct task_struct *idle) |
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.. | .. |
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191 | 191 | * Set synchronisation state between this boot processor |
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192 | 192 | * and the secondary one |
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193 | 193 | */ |
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194 | | - spin_lock(&boot_lock); |
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| 194 | + raw_spin_lock(&boot_lock); |
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195 | 195 | |
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196 | 196 | /* |
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197 | 197 | * Update the AuxCoreBoot0 with boot state for secondary core. |
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.. | .. |
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270 | 270 | * Now the secondary core is starting up let it run its |
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271 | 271 | * calibrations, then wait for it to finish |
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272 | 272 | */ |
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273 | | - spin_unlock(&boot_lock); |
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| 273 | + raw_spin_unlock(&boot_lock); |
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274 | 274 | |
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275 | 275 | return 0; |
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276 | 276 | } |
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