hc
2023-11-06 e3e12f52b214121840b44c91de5b3e5af5d3eb84
kernel/arch/arm/mach-omap2/omap-smp.c
....@@ -69,7 +69,7 @@
6969 .startup_addr = omap5_secondary_startup,
7070 };
7171
72
-static DEFINE_SPINLOCK(boot_lock);
72
+static DEFINE_RAW_SPINLOCK(boot_lock);
7373
7474 void __iomem *omap4_get_scu_base(void)
7575 {
....@@ -177,8 +177,8 @@
177177 /*
178178 * Synchronise with the boot thread.
179179 */
180
- spin_lock(&boot_lock);
181
- spin_unlock(&boot_lock);
180
+ raw_spin_lock(&boot_lock);
181
+ raw_spin_unlock(&boot_lock);
182182 }
183183
184184 static int omap4_boot_secondary(unsigned int cpu, struct task_struct *idle)
....@@ -191,7 +191,7 @@
191191 * Set synchronisation state between this boot processor
192192 * and the secondary one
193193 */
194
- spin_lock(&boot_lock);
194
+ raw_spin_lock(&boot_lock);
195195
196196 /*
197197 * Update the AuxCoreBoot0 with boot state for secondary core.
....@@ -270,7 +270,7 @@
270270 * Now the secondary core is starting up let it run its
271271 * calibrations, then wait for it to finish
272272 */
273
- spin_unlock(&boot_lock);
273
+ raw_spin_unlock(&boot_lock);
274274
275275 return 0;
276276 }