.. | .. |
---|
465 | 465 | bias-pull-pin-default; |
---|
466 | 466 | }; |
---|
467 | 467 | |
---|
468 | | - pcfg_pull_up: pcfg-pull-up { |
---|
469 | | - bias-pull-up; |
---|
470 | | - }; |
---|
471 | | - |
---|
472 | 468 | pcfg_pull_none: pcfg_pull_none { |
---|
473 | 469 | bias-disable; |
---|
474 | 470 | }; |
---|
.. | .. |
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609 | 605 | |
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610 | 606 | uart0 { |
---|
611 | 607 | uart0_xfer: uart0-xfer { |
---|
612 | | - rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up>, |
---|
613 | | - <1 RK_PA1 1 &pcfg_pull_up>; |
---|
| 608 | + rockchip,pins = <1 RK_PA0 1 &pcfg_pull_default>, |
---|
| 609 | + <1 RK_PA1 1 &pcfg_pull_default>; |
---|
614 | 610 | }; |
---|
615 | 611 | |
---|
616 | 612 | uart0_cts: uart0-cts { |
---|
.. | .. |
---|
624 | 620 | |
---|
625 | 621 | uart1 { |
---|
626 | 622 | uart1_xfer: uart1-xfer { |
---|
627 | | - rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up>, |
---|
628 | | - <1 RK_PA5 1 &pcfg_pull_up>; |
---|
| 623 | + rockchip,pins = <1 RK_PA4 1 &pcfg_pull_default>, |
---|
| 624 | + <1 RK_PA5 1 &pcfg_pull_default>; |
---|
629 | 625 | }; |
---|
630 | 626 | |
---|
631 | 627 | uart1_cts: uart1-cts { |
---|
.. | .. |
---|
639 | 635 | |
---|
640 | 636 | uart2 { |
---|
641 | 637 | uart2_xfer: uart2-xfer { |
---|
642 | | - rockchip,pins = <1 RK_PB0 1 &pcfg_pull_up>, |
---|
643 | | - <1 RK_PB1 1 &pcfg_pull_up>; |
---|
| 638 | + rockchip,pins = <1 RK_PB0 1 &pcfg_pull_default>, |
---|
| 639 | + <1 RK_PB1 1 &pcfg_pull_default>; |
---|
644 | 640 | }; |
---|
645 | 641 | /* no rts / cts for uart2 */ |
---|
646 | 642 | }; |
---|
647 | 643 | |
---|
648 | 644 | uart3 { |
---|
649 | 645 | uart3_xfer: uart3-xfer { |
---|
650 | | - rockchip,pins = <3 RK_PD3 1 &pcfg_pull_up>, |
---|
651 | | - <3 RK_PD4 1 &pcfg_pull_up>; |
---|
| 646 | + rockchip,pins = <3 RK_PD3 1 &pcfg_pull_default>, |
---|
| 647 | + <3 RK_PD4 1 &pcfg_pull_default>; |
---|
652 | 648 | }; |
---|
653 | 649 | |
---|
654 | 650 | uart3_cts: uart3-cts { |
---|