~ljy/RK356X_SDK_RELEASE.git

..	..	@@ -19,11 +19,14 @@
19	19	#include <media/videobuf2-dma-sg.h>
20	20	#include <soc/rockchip/rockchip-system-status.h>
21	21	#include <dt-bindings/soc/rockchip-system-status.h>
	22	+#include <soc/rockchip/rockchip_iommu.h>
22	23
23	24	#include "dev.h"
24	25	#include "mipi-csi2.h"
	26	+#include "common.h"
	27	+#include "rkcif-externel.h"
25	28
26		-#define CIF_REQ_BUFS_MIN 3
	29	+#define CIF_REQ_BUFS_MIN 1
27	30	#define CIF_MIN_WIDTH 64
28	31	#define CIF_MIN_HEIGHT 64
29	32	#define CIF_MAX_WIDTH 8192
..	..	@@ -33,6 +36,7 @@
33	36
34	37	#define RKCIF_PLANE_Y 0
35	38	#define RKCIF_PLANE_CBCR 1
	39	+#define RKCIF_MAX_PLANE 3
36	40
37	41	#define STREAM_PAD_SINK 0
38	42	#define STREAM_PAD_SOURCE 1
..	..	@@ -146,10 +150,18 @@
146	150	.csi_fmt_val = CSI_WRDDR_TYPE_RGB888,
147	151	.fmt_type = CIF_FMT_TYPE_RAW,
148	152	}, {
	153	+ .fourcc = V4L2_PIX_FMT_BGR24,
	154	+ .cplanes = 1,
	155	+ .mplanes = 1,
	156	+ .bpp = { 24 },
	157	+ .csi_fmt_val = CSI_WRDDR_TYPE_RGB888,
	158	+ .fmt_type = CIF_FMT_TYPE_RAW,
	159	+ }, {
149	160	.fourcc = V4L2_PIX_FMT_RGB565,
150	161	.cplanes = 1,
151	162	.mplanes = 1,
152	163	.bpp = { 16 },
	164	+ .csi_fmt_val = CSI_WRDDR_TYPE_RGB565,
153	165	.fmt_type = CIF_FMT_TYPE_RAW,
154	166	}, {
155	167	.fourcc = V4L2_PIX_FMT_BGR666,
..	..	@@ -262,6 +274,30 @@
262	274	.csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
263	275	.fmt_type = CIF_FMT_TYPE_RAW,
264	276	}, {
	277	+ .fourcc = V4L2_PIX_FMT_SGBRG16,
	278	+ .cplanes = 1,
	279	+ .mplanes = 1,
	280	+ .bpp = { 16 },
	281	+ .raw_bpp = 16,
	282	+ .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
	283	+ .fmt_type = CIF_FMT_TYPE_RAW,
	284	+ }, {
	285	+ .fourcc = V4L2_PIX_FMT_SGRBG16,
	286	+ .cplanes = 1,
	287	+ .mplanes = 1,
	288	+ .bpp = { 16 },
	289	+ .raw_bpp = 16,
	290	+ .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
	291	+ .fmt_type = CIF_FMT_TYPE_RAW,
	292	+ }, {
	293	+ .fourcc = V4L2_PIX_FMT_SRGGB16,
	294	+ .cplanes = 1,
	295	+ .mplanes = 1,
	296	+ .bpp = { 16 },
	297	+ .raw_bpp = 16,
	298	+ .csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
	299	+ .fmt_type = CIF_FMT_TYPE_RAW,
	300	+ }, {
265	301	.fourcc = V4L2_PIX_FMT_Y16,
266	302	.cplanes = 1,
267	303	.mplanes = 1,
..	..	@@ -293,8 +329,51 @@
293	329	.raw_bpp = 16,
294	330	.csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
295	331	.fmt_type = CIF_FMT_TYPE_RAW,
	332	+ }, {
	333	+ .fourcc = V4L2_PIX_FMT_Y12,
	334	+ .cplanes = 1,
	335	+ .mplanes = 1,
	336	+ .bpp = { 16 },
	337	+ .raw_bpp = 12,
	338	+ .csi_fmt_val = CSI_WRDDR_TYPE_RAW12,
	339	+ .fmt_type = CIF_FMT_TYPE_RAW,
	340	+ }, {
	341	+ .fourcc = V4L2_PIX_FMT_Y10,
	342	+ .cplanes = 1,
	343	+ .mplanes = 1,
	344	+ .bpp = { 16 },
	345	+ .raw_bpp = 10,
	346	+ .csi_fmt_val = CSI_WRDDR_TYPE_RAW10,
	347	+ .fmt_type = CIF_FMT_TYPE_RAW,
	348	+ }, {
	349	+ .fourcc = V4L2_PIX_FMT_SRGGB16,
	350	+ .cplanes = 1,
	351	+ .mplanes = 1,
	352	+ .bpp = { 16 },
	353	+ .raw_bpp = 16,
	354	+ .fmt_type = CIF_FMT_TYPE_RAW,
	355	+ }, {
	356	+ .fourcc = V4L2_PIX_FMT_SGRBG16,
	357	+ .cplanes = 1,
	358	+ .mplanes = 1,
	359	+ .bpp = { 16 },
	360	+ .raw_bpp = 16,
	361	+ .fmt_type = CIF_FMT_TYPE_RAW,
	362	+ }, {
	363	+ .fourcc = V4L2_PIX_FMT_SGBRG16,
	364	+ .cplanes = 1,
	365	+ .mplanes = 1,
	366	+ .bpp = { 16 },
	367	+ .raw_bpp = 16,
	368	+ .fmt_type = CIF_FMT_TYPE_RAW,
	369	+ }, {
	370	+ .fourcc = V4L2_PIX_FMT_SBGGR16,
	371	+ .cplanes = 1,
	372	+ .mplanes = 1,
	373	+ .bpp = { 16 },
	374	+ .raw_bpp = 16,
	375	+ .fmt_type = CIF_FMT_TYPE_RAW,
296	376	}
297		-
298	377	/* TODO: We can support NV12M/NV21M/NV16M/NV61M too */
299	378	};
300	379
..	..	@@ -432,6 +511,14 @@
432	511	.csi_fmt_val = CSI_WRDDR_TYPE_RGB888,
433	512	.field = V4L2_FIELD_NONE,
434	513	}, {
	514	+ .mbus_code = MEDIA_BUS_FMT_BGR888_1X24,
	515	+ .csi_fmt_val = CSI_WRDDR_TYPE_RGB888,
	516	+ .field = V4L2_FIELD_NONE,
	517	+ }, {
	518	+ .mbus_code = MEDIA_BUS_FMT_RGB565_1X16,
	519	+ .csi_fmt_val = CSI_WRDDR_TYPE_RGB565,
	520	+ .field = V4L2_FIELD_NONE,
	521	+ }, {
435	522	.mbus_code = MEDIA_BUS_FMT_Y8_1X8,
436	523	.dvp_fmt_val = INPUT_MODE_RAW \| RAW_DATA_WIDTH_8,
437	524	.csi_fmt_val = CSI_WRDDR_TYPE_RAW8,
..	..	@@ -463,6 +550,143 @@
463	550	.field = V4L2_FIELD_NONE,
464	551	}
465	552	};
	553	+
	554	+static int rkcif_output_fmt_check(struct rkcif_stream *stream,
	555	+ const struct cif_output_fmt *output_fmt)
	556	+{
	557	+ const struct cif_input_fmt *input_fmt = stream->cif_fmt_in;
	558	+ struct csi_channel_info *channel = &stream->cifdev->channels[stream->id];
	559	+ int ret = -EINVAL;
	560	+
	561	+ switch (input_fmt->mbus_code) {
	562	+ case MEDIA_BUS_FMT_YUYV8_2X8:
	563	+ case MEDIA_BUS_FMT_YVYU8_2X8:
	564	+ case MEDIA_BUS_FMT_UYVY8_2X8:
	565	+ case MEDIA_BUS_FMT_VYUY8_2X8:
	566	+ if (output_fmt->fourcc == V4L2_PIX_FMT_NV16 \|\|
	567	+ output_fmt->fourcc == V4L2_PIX_FMT_NV61 \|\|
	568	+ output_fmt->fourcc == V4L2_PIX_FMT_NV12 \|\|
	569	+ output_fmt->fourcc == V4L2_PIX_FMT_NV21 \|\|
	570	+ output_fmt->fourcc == V4L2_PIX_FMT_YUYV \|\|
	571	+ output_fmt->fourcc == V4L2_PIX_FMT_YVYU \|\|
	572	+ output_fmt->fourcc == V4L2_PIX_FMT_UYVY \|\|
	573	+ output_fmt->fourcc == V4L2_PIX_FMT_VYUY)
	574	+ ret = 0;
	575	+ break;
	576	+ case MEDIA_BUS_FMT_SBGGR8_1X8:
	577	+ case MEDIA_BUS_FMT_SGBRG8_1X8:
	578	+ case MEDIA_BUS_FMT_SGRBG8_1X8:
	579	+ case MEDIA_BUS_FMT_SRGGB8_1X8:
	580	+ case MEDIA_BUS_FMT_Y8_1X8:
	581	+ if (output_fmt->fourcc == V4L2_PIX_FMT_SRGGB8 \|\|
	582	+ output_fmt->fourcc == V4L2_PIX_FMT_SGRBG8 \|\|
	583	+ output_fmt->fourcc == V4L2_PIX_FMT_SGBRG8 \|\|
	584	+ output_fmt->fourcc == V4L2_PIX_FMT_SBGGR8 \|\|
	585	+ output_fmt->fourcc == V4L2_PIX_FMT_GREY)
	586	+ ret = 0;
	587	+ break;
	588	+ case MEDIA_BUS_FMT_SBGGR10_1X10:
	589	+ case MEDIA_BUS_FMT_SGBRG10_1X10:
	590	+ case MEDIA_BUS_FMT_SGRBG10_1X10:
	591	+ case MEDIA_BUS_FMT_SRGGB10_1X10:
	592	+ case MEDIA_BUS_FMT_Y10_1X10:
	593	+ if (output_fmt->fourcc == V4L2_PIX_FMT_SRGGB10 \|\|
	594	+ output_fmt->fourcc == V4L2_PIX_FMT_SGRBG10 \|\|
	595	+ output_fmt->fourcc == V4L2_PIX_FMT_SGBRG10 \|\|
	596	+ output_fmt->fourcc == V4L2_PIX_FMT_SBGGR10 \|\|
	597	+ output_fmt->fourcc == V4L2_PIX_FMT_Y10)
	598	+ ret = 0;
	599	+ break;
	600	+ case MEDIA_BUS_FMT_SBGGR12_1X12:
	601	+ case MEDIA_BUS_FMT_SGBRG12_1X12:
	602	+ case MEDIA_BUS_FMT_SGRBG12_1X12:
	603	+ case MEDIA_BUS_FMT_SRGGB12_1X12:
	604	+ case MEDIA_BUS_FMT_Y12_1X12:
	605	+ if (output_fmt->fourcc == V4L2_PIX_FMT_SRGGB12 \|\|
	606	+ output_fmt->fourcc == V4L2_PIX_FMT_SGRBG12 \|\|
	607	+ output_fmt->fourcc == V4L2_PIX_FMT_SGBRG12 \|\|
	608	+ output_fmt->fourcc == V4L2_PIX_FMT_SBGGR12 \|\|
	609	+ output_fmt->fourcc == V4L2_PIX_FMT_Y12)
	610	+ ret = 0;
	611	+ break;
	612	+ case MEDIA_BUS_FMT_RGB888_1X24:
	613	+ case MEDIA_BUS_FMT_BGR888_1X24:
	614	+ if (output_fmt->fourcc == V4L2_PIX_FMT_RGB24 \|\|
	615	+ output_fmt->fourcc == V4L2_PIX_FMT_BGR24)
	616	+ ret = 0;
	617	+ break;
	618	+ case MEDIA_BUS_FMT_RGB565_1X16:
	619	+ if (output_fmt->fourcc == V4L2_PIX_FMT_RGB565)
	620	+ ret = 0;
	621	+ break;
	622	+ case MEDIA_BUS_FMT_EBD_1X8:
	623	+ if (output_fmt->fourcc == V4l2_PIX_FMT_EBD8 \|\|
	624	+ (channel->data_bit == 8 &&
	625	+ (output_fmt->fourcc == V4L2_PIX_FMT_SRGGB8 \|\|
	626	+ output_fmt->fourcc == V4L2_PIX_FMT_SGRBG8 \|\|
	627	+ output_fmt->fourcc == V4L2_PIX_FMT_SGBRG8 \|\|
	628	+ output_fmt->fourcc == V4L2_PIX_FMT_SBGGR8)) \|\|
	629	+ (channel->data_bit == 10 &&
	630	+ (output_fmt->fourcc == V4L2_PIX_FMT_SRGGB10 \|\|
	631	+ output_fmt->fourcc == V4L2_PIX_FMT_SGRBG10 \|\|
	632	+ output_fmt->fourcc == V4L2_PIX_FMT_SGBRG10 \|\|
	633	+ output_fmt->fourcc == V4L2_PIX_FMT_SBGGR10)) \|\|
	634	+ (channel->data_bit == 12 &&
	635	+ (output_fmt->fourcc == V4L2_PIX_FMT_SRGGB12 \|\|
	636	+ output_fmt->fourcc == V4L2_PIX_FMT_SGRBG12 \|\|
	637	+ output_fmt->fourcc == V4L2_PIX_FMT_SGBRG12 \|\|
	638	+ output_fmt->fourcc == V4L2_PIX_FMT_SBGGR12)) \|\|
	639	+ (channel->data_bit == 16 &&
	640	+ (output_fmt->fourcc == V4L2_PIX_FMT_SRGGB16 \|\|
	641	+ output_fmt->fourcc == V4L2_PIX_FMT_SGRBG16 \|\|
	642	+ output_fmt->fourcc == V4L2_PIX_FMT_SGBRG16 \|\|
	643	+ output_fmt->fourcc == V4L2_PIX_FMT_SBGGR16)))
	644	+ ret = 0;
	645	+ break;
	646	+ case MEDIA_BUS_FMT_SPD_2X8:
	647	+ if (output_fmt->fourcc == V4l2_PIX_FMT_SPD16 \|\|
	648	+ (channel->data_bit == 8 &&
	649	+ (output_fmt->fourcc == V4L2_PIX_FMT_SRGGB8 \|\|
	650	+ output_fmt->fourcc == V4L2_PIX_FMT_SGRBG8 \|\|
	651	+ output_fmt->fourcc == V4L2_PIX_FMT_SGBRG8 \|\|
	652	+ output_fmt->fourcc == V4L2_PIX_FMT_SBGGR8)) \|\|
	653	+ (channel->data_bit == 10 &&
	654	+ (output_fmt->fourcc == V4L2_PIX_FMT_SRGGB10 \|\|
	655	+ output_fmt->fourcc == V4L2_PIX_FMT_SGRBG10 \|\|
	656	+ output_fmt->fourcc == V4L2_PIX_FMT_SGBRG10 \|\|
	657	+ output_fmt->fourcc == V4L2_PIX_FMT_SBGGR10)) \|\|
	658	+ (channel->data_bit == 12 &&
	659	+ (output_fmt->fourcc == V4L2_PIX_FMT_SRGGB12 \|\|
	660	+ output_fmt->fourcc == V4L2_PIX_FMT_SGRBG12 \|\|
	661	+ output_fmt->fourcc == V4L2_PIX_FMT_SGBRG12 \|\|
	662	+ output_fmt->fourcc == V4L2_PIX_FMT_SBGGR12)) \|\|
	663	+ (channel->data_bit == 16 &&
	664	+ (output_fmt->fourcc == V4L2_PIX_FMT_SRGGB16 \|\|
	665	+ output_fmt->fourcc == V4L2_PIX_FMT_SGRBG16 \|\|
	666	+ output_fmt->fourcc == V4L2_PIX_FMT_SGBRG16 \|\|
	667	+ output_fmt->fourcc == V4L2_PIX_FMT_SBGGR16)))
	668	+ ret = 0;
	669	+ break;
	670	+ default:
	671	+ break;
	672	+ }
	673	+ if (ret)
	674	+ v4l2_err(&stream->cifdev->v4l2_dev,
	675	+ "input mbus_code 0x%x, can't transform to %c%c%c%c\n",
	676	+ input_fmt->mbus_code,
	677	+ output_fmt->fourcc & 0xff,
	678	+ (output_fmt->fourcc >> 8) & 0xff,
	679	+ (output_fmt->fourcc >> 16) & 0xff,
	680	+ (output_fmt->fourcc >> 24) & 0xff);
	681	+ return ret;
	682	+}
	683	+
	684	+static int rkcif_stop_dma_capture(struct rkcif_stream *stream);
	685	+
	686	+struct rkcif_rx_buffer to_cif_rx_buf(struct rkisp_rx_buf dbufs)
	687	+{
	688	+ return container_of(dbufs, struct rkcif_rx_buffer, dbufs);
	689	+}
466	690
467	691	static struct v4l2_subdev get_remote_sensor(struct rkcif_stream stream, u16 *index)
468	692	{
..	..	@@ -553,18 +777,21 @@
553	777	case MEDIA_BUS_FMT_SGBRG8_1X8:
554	778	case MEDIA_BUS_FMT_SGRBG8_1X8:
555	779	case MEDIA_BUS_FMT_SRGGB8_1X8:
	780	+ case MEDIA_BUS_FMT_Y8_1X8:
556	781	return 0x2a;
557	782	/* csi raw10 */
558	783	case MEDIA_BUS_FMT_SBGGR10_1X10:
559	784	case MEDIA_BUS_FMT_SGBRG10_1X10:
560	785	case MEDIA_BUS_FMT_SGRBG10_1X10:
561	786	case MEDIA_BUS_FMT_SRGGB10_1X10:
	787	+ case MEDIA_BUS_FMT_Y10_1X10:
562	788	return 0x2b;
563	789	/* csi raw12 */
564	790	case MEDIA_BUS_FMT_SBGGR12_1X12:
565	791	case MEDIA_BUS_FMT_SGBRG12_1X12:
566	792	case MEDIA_BUS_FMT_SGRBG12_1X12:
567	793	case MEDIA_BUS_FMT_SRGGB12_1X12:
	794	+ case MEDIA_BUS_FMT_Y12_1X12:
568	795	return 0x2c;
569	796	/* csi uyvy 422 */
570	797	case MEDIA_BUS_FMT_UYVY8_2X8:
..	..	@@ -572,7 +799,8 @@
572	799	case MEDIA_BUS_FMT_YUYV8_2X8:
573	800	case MEDIA_BUS_FMT_YVYU8_2X8:
574	801	return 0x1e;
575		- case MEDIA_BUS_FMT_RGB888_1X24: {
	802	+ case MEDIA_BUS_FMT_RGB888_1X24:
	803	+ case MEDIA_BUS_FMT_BGR888_1X24:
576	804	if (dsi_input) {
577	805	if (cmd_mode_en) /* dsi command mode*/
578	806	return 0x39;
..	..	@@ -581,7 +809,15 @@
581	809	} else {
582	810	return 0x24;
583	811	}
584		- }
	812	+ case MEDIA_BUS_FMT_RGB565_1X16:
	813	+ if (dsi_input) {
	814	+ if (cmd_mode_en) /* dsi command mode*/
	815	+ return 0x39;
	816	+ else /* dsi video mode */
	817	+ return 0x0e;
	818	+ } else {
	819	+ return 0x22;
	820	+ }
585	821	case MEDIA_BUS_FMT_EBD_1X8:
586	822	return 0x12;
587	823	case MEDIA_BUS_FMT_SPD_2X8:
..	..	@@ -597,6 +833,8 @@
597	833	switch (fmt_in->csi_fmt_val) {
598	834	case CSI_WRDDR_TYPE_RGB888:
599	835	return 24;
	836	+ case CSI_WRDDR_TYPE_RGB565:
	837	+ return 16;
600	838	case CSI_WRDDR_TYPE_RAW10:
601	839	case CSI_WRDDR_TYPE_RAW12:
602	840	return 4;
..	..	@@ -608,51 +846,61 @@
608	846	}
609	847	}
610	848
611		-static const struct
612		-cif_input_fmt get_input_fmt(struct v4l2_subdev sd, struct v4l2_rect *rect,
613		- u32 pad, int *vc)
	849	+const struct
	850	+cif_input_fmt rkcif_get_input_fmt(struct rkcif_device dev, struct v4l2_rect *rect,
	851	+ u32 pad_id, struct csi_channel_info *csi_info)
614	852	{
615	853	struct v4l2_subdev_format fmt;
	854	+ struct v4l2_subdev *sd = dev->terminal_sensor.sd;
	855	+ struct rkmodule_channel_info ch_info = {0};
	856	+ struct rkmodule_capture_info capture_info;
616	857	int ret;
617	858	u32 i;
618		- struct rkmodule_vc_fmt_info vc_info = {0};
619	859
620		- ret = v4l2_subdev_call(sd,
621		- core, ioctl,
622		- RKMODULE_GET_VC_FMT_INFO,
623		- &vc_info);
624		- if (ret < 0)
625		- v4l2_warn(sd->v4l2_dev,
626		- "get sensor vc info failed, maybe not support\n");
627		-
628		- fmt.pad = pad;
	860	+ fmt.pad = 0;
629	861	fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
630	862	fmt.reserved[0] = 0;
	863	+ fmt.format.field = V4L2_FIELD_NONE;
631	864	ret = v4l2_subdev_call(sd, pad, get_fmt, NULL, &fmt);
632	865	if (ret < 0) {
633	866	v4l2_warn(sd->v4l2_dev,
634	867	"sensor fmt invalid, set to default size\n");
635	868	goto set_default;
636	869	}
637		-
638		- /* v4l2_subdev_format reserved[0]
639		- * using as mipi virtual channel
640		- */
641		- switch (fmt.reserved[0]) {
642		- case V4L2_MBUS_CSI2_CHANNEL_3:
643		- *vc = 3;
644		- break;
645		- case V4L2_MBUS_CSI2_CHANNEL_2:
646		- *vc = 2;
647		- break;
648		- case V4L2_MBUS_CSI2_CHANNEL_1:
649		- *vc = 1;
650		- break;
651		- case V4L2_MBUS_CSI2_CHANNEL_0:
652		- *vc = 0;
653		- break;
654		- default:
655		- *vc = -1;
	870	+ ch_info.index = pad_id;
	871	+ ret = v4l2_subdev_call(sd,
	872	+ core, ioctl,
	873	+ RKMODULE_GET_CHANNEL_INFO,
	874	+ &ch_info);
	875	+ if (!ret) {
	876	+ fmt.format.width = ch_info.width;
	877	+ fmt.format.height = ch_info.height;
	878	+ fmt.format.code = ch_info.bus_fmt;
	879	+ switch (ch_info.vc) {
	880	+ case V4L2_MBUS_CSI2_CHANNEL_3:
	881	+ csi_info->vc = 3;
	882	+ break;
	883	+ case V4L2_MBUS_CSI2_CHANNEL_2:
	884	+ csi_info->vc = 2;
	885	+ break;
	886	+ case V4L2_MBUS_CSI2_CHANNEL_1:
	887	+ csi_info->vc = 1;
	888	+ break;
	889	+ case V4L2_MBUS_CSI2_CHANNEL_0:
	890	+ csi_info->vc = 0;
	891	+ break;
	892	+ default:
	893	+ csi_info->vc = 0xff;
	894	+ }
	895	+ if (ch_info.bus_fmt == MEDIA_BUS_FMT_SPD_2X8 \|\|
	896	+ ch_info.bus_fmt == MEDIA_BUS_FMT_EBD_1X8) {
	897	+ if (ch_info.data_type > 0)
	898	+ csi_info->data_type = ch_info.data_type;
	899	+ if (ch_info.data_bit > 0)
	900	+ csi_info->data_bit = ch_info.data_bit;
	901	+ }
	902	+ } else {
	903	+ csi_info->vc = 0xff;
656	904	}
657	905
658	906	v4l2_dbg(1, rkcif_debug, sd->v4l2_dev,
..	..	@@ -663,7 +911,26 @@
663	911	rect->top = 0;
664	912	rect->width = fmt.format.width;
665	913	rect->height = fmt.format.height;
666		-
	914	+ ret = v4l2_subdev_call(sd,
	915	+ core, ioctl,
	916	+ RKMODULE_GET_CAPTURE_MODE,
	917	+ &capture_info);
	918	+ if (!ret) {
	919	+ if (capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE &&
	920	+ dev->hw_dev->is_rk3588s2) {
	921	+ for (i = 0; i < capture_info.multi_dev.dev_num; i++) {
	922	+ if (capture_info.multi_dev.dev_idx[i] == 0)
	923	+ capture_info.multi_dev.dev_idx[i] = 2;
	924	+ else if (capture_info.multi_dev.dev_idx[i] == 2)
	925	+ capture_info.multi_dev.dev_idx[i] = 4;
	926	+ else if (capture_info.multi_dev.dev_idx[i] == 3)
	927	+ capture_info.multi_dev.dev_idx[i] = 5;
	928	+ }
	929	+ }
	930	+ csi_info->capture_info = capture_info;
	931	+ } else {
	932	+ csi_info->capture_info.mode = RKMODULE_CAPTURE_MODE_NONE;
	933	+ }
667	934	for (i = 0; i < ARRAY_SIZE(in_fmts); i++)
668	935	if (fmt.format.code == in_fmts[i].mbus_code &&
669	936	fmt.format.field == in_fmts[i].field)
..	..	@@ -680,8 +947,8 @@
680	947	return NULL;
681	948	}
682	949
683		-static const struct
684		-cif_output_fmt find_output_fmt(struct rkcif_stream stream, u32 pixelfmt)
	950	+const struct
	951	+cif_output_fmt rkcif_find_output_fmt(struct rkcif_stream stream, u32 pixelfmt)
685	952	{
686	953	const struct cif_output_fmt *fmt;
687	954	u32 i;
..	..	@@ -714,6 +981,31 @@
714	981	break;
715	982	default:
716	983	index = CIF_REG_MIPI_LVDS_ID0_CTRL0;
	984	+ break;
	985	+ }
	986	+
	987	+ return index;
	988	+}
	989	+
	990	+static enum cif_reg_index get_reg_index_of_lvds_id_ctrl0(int channel_id)
	991	+{
	992	+ enum cif_reg_index index;
	993	+
	994	+ switch (channel_id) {
	995	+ case 0:
	996	+ index = CIF_REG_LVDS_ID0_CTRL0;
	997	+ break;
	998	+ case 1:
	999	+ index = CIF_REG_LVDS_ID1_CTRL0;
	1000	+ break;
	1001	+ case 2:
	1002	+ index = CIF_REG_LVDS_ID2_CTRL0;
	1003	+ break;
	1004	+ case 3:
	1005	+ index = CIF_REG_LVDS_ID3_CTRL0;
	1006	+ break;
	1007	+ default:
	1008	+ index = CIF_REG_LVDS_ID0_CTRL0;
717	1009	break;
718	1010	}
719	1011
..	..	@@ -1170,12 +1462,50 @@
1170	1462	return index;
1171	1463	}
1172	1464
	1465	+int rkcif_get_linetime(struct rkcif_stream *stream)
	1466	+{
	1467	+ struct rkcif_device *cif_dev = stream->cifdev;
	1468	+ struct rkcif_sensor_info *sensor = &cif_dev->terminal_sensor;
	1469	+ u32 numerator, denominator;
	1470	+ u32 def_fps = 0;
	1471	+ int line_time = 0;
	1472	+ int vblank_def = 0;
	1473	+ int vblank_curr = 0;
	1474	+
	1475	+ numerator = sensor->fi.interval.numerator;
	1476	+ denominator = sensor->fi.interval.denominator;
	1477	+ if (!numerator \|\| !denominator) {
	1478	+ v4l2_err(&cif_dev->v4l2_dev,
	1479	+ "get frame interval fail, numerator %d, denominator %d\n",
	1480	+ numerator, denominator);
	1481	+ return -EINVAL;
	1482	+ }
	1483	+ def_fps = denominator / numerator;
	1484	+ if (!def_fps) {
	1485	+ v4l2_err(&cif_dev->v4l2_dev,
	1486	+ "get fps fail, numerator %d, denominator %d\n",
	1487	+ numerator, denominator);
	1488	+ return -EINVAL;
	1489	+ }
	1490	+ vblank_def = rkcif_get_sensor_vblank_def(cif_dev);
	1491	+ vblank_curr = rkcif_get_sensor_vblank(cif_dev);
	1492	+ if (!vblank_def \|\| !vblank_curr) {
	1493	+ v4l2_err(&cif_dev->v4l2_dev,
	1494	+ "get vblank fail, vblank_def %d, vblank_curr %d\n",
	1495	+ vblank_def, vblank_curr);
	1496	+ return -EINVAL;
	1497	+ }
	1498	+ line_time = div_u64(1000000000, def_fps);
	1499	+ line_time = div_u64(line_time, vblank_def + sensor->raw_rect.height);
	1500	+ return line_time;
	1501	+}
	1502	+
1173	1503	/*************************** stream operations ****************************/
1174	1504	static int rkcif_assign_new_buffer_oneframe(struct rkcif_stream *stream,
1175		- enum rkcif_yuvaddr_state stat)
	1505	+ enum rkcif_yuvaddr_state stat)
1176	1506	{
1177	1507	struct rkcif_device *dev = stream->cifdev;
1178		- struct rkcif_dummy_buffer *dummy_buf = &dev->dummy_buf;
	1508	+ struct rkcif_dummy_buffer *dummy_buf = &dev->hw_dev->dummy_buf;
1179	1509	struct rkcif_buffer *buffer = NULL;
1180	1510	u32 frm_addr_y = CIF_REG_DVP_FRM0_ADDR_Y;
1181	1511	u32 frm_addr_uv = CIF_REG_DVP_FRM0_ADDR_UV;
..	..	@@ -1270,12 +1600,696 @@
1270	1600	} else {
1271	1601	ret = -EINVAL;
1272	1602	}
1273		- v4l2_dbg(1, rkcif_debug, &dev->v4l2_dev,
1274		- "not active buffer, frame Drop\n");
	1603	+ dev->err_state \|= (RKCIF_ERR_ID0_NOT_BUF << stream->id);
	1604	+ dev->irq_stats.not_active_buf_cnt[stream->id]++;
1275	1605	}
1276	1606	}
1277	1607	spin_unlock_irqrestore(&stream->vbq_lock, flags);
1278	1608	return ret;
	1609	+}
	1610	+
	1611	+static void rkcif_rx_buffer_free(struct rkcif_stream *stream)
	1612	+{
	1613	+ struct media_pad *pad = NULL;
	1614	+ struct v4l2_subdev *sd;
	1615	+ struct rkisp_rx_buf *dbufs;
	1616	+ struct rkcif_device *dev = stream->cifdev;
	1617	+
	1618	+ if (dev->sditf[0] && dev->sditf[0]->sd.entity.num_links) {
	1619	+ if (dev->sditf[0]->is_combine_mode)
	1620	+ pad = media_entity_remote_pad(&dev->sditf[0]->pads[1]);
	1621	+ else
	1622	+ pad = media_entity_remote_pad(&dev->sditf[0]->pads[0]);
	1623	+ } else {
	1624	+ return;
	1625	+ }
	1626	+
	1627	+ if (pad)
	1628	+ sd = media_entity_to_v4l2_subdev(pad->entity);
	1629	+ else
	1630	+ return;
	1631	+
	1632	+ while (!list_empty(&stream->rx_buf_head_vicap)) {
	1633	+ dbufs = list_first_entry(&stream->rx_buf_head_vicap, struct rkisp_rx_buf, list);
	1634	+ if (dbufs->is_init)
	1635	+ v4l2_subdev_call(sd, core, ioctl,
	1636	+ RKISP_VICAP_CMD_RX_BUFFER_FREE, dbufs);
	1637	+ dma_buf_put(dbufs->dbuf);
	1638	+ list_del(&dbufs->list);
	1639	+ kfree(dbufs);
	1640	+ }
	1641	+}
	1642	+
	1643	+static void rkcif_s_rx_buffer(struct rkcif_device dev, struct rkisp_rx_buf dbufs)
	1644	+{
	1645	+ struct media_pad *pad = NULL;
	1646	+ struct v4l2_subdev *sd;
	1647	+ struct rkcif_rx_buffer *rx_buf = NULL;
	1648	+
	1649	+ if (dev->sditf[0]) {
	1650	+ if (dev->sditf[0]->is_combine_mode)
	1651	+ pad = media_entity_remote_pad(&dev->sditf[0]->pads[1]);
	1652	+ else
	1653	+ pad = media_entity_remote_pad(&dev->sditf[0]->pads[0]);
	1654	+ } else {
	1655	+ return;
	1656	+ }
	1657	+ if (pad)
	1658	+ sd = media_entity_to_v4l2_subdev(pad->entity);
	1659	+ else
	1660	+ return;
	1661	+ if (dev->rdbk_debug &&
	1662	+ dbufs->sequence < 15) {
	1663	+ rx_buf = to_cif_rx_buf(dbufs);
	1664	+ v4l2_info(&dev->v4l2_dev,
	1665	+ "s_buf seq %d type %d, dma addr %x, %lld\n",
	1666	+ dbufs->sequence, dbufs->type, (u32)rx_buf->dummy.dma_addr,
	1667	+ ktime_get_ns());
	1668	+ }
	1669	+ v4l2_subdev_call(sd, video, s_rx_buffer, dbufs, NULL);
	1670	+}
	1671	+
	1672	+static void rkcif_enable_skip_frame(struct rkcif_stream *stream, int cap_m, int skip_n)
	1673	+{
	1674	+ struct rkcif_device *dev = stream->cifdev;
	1675	+ u32 val = 0;
	1676	+
	1677	+ val = rkcif_read_register(dev, CIF_REG_MIPI_LVDS_CTRL);
	1678	+ val &= 0xc00fffff;
	1679	+ val \|= cap_m << RKCIF_CAP_SHIFT \| skip_n << RKCIF_SKIP_SHIFT \| RKCIF_SKIP_EN(stream->id);
	1680	+ rkcif_write_register(dev, CIF_REG_MIPI_LVDS_CTRL, val);
	1681	+ stream->skip_info.skip_en = true;
	1682	+}
	1683	+
	1684	+static void rkcif_disable_skip_frame(struct rkcif_stream *stream)
	1685	+{ struct rkcif_device *dev = stream->cifdev;
	1686	+ u32 val = 0;
	1687	+
	1688	+ val = rkcif_read_register(dev, CIF_REG_MIPI_LVDS_CTRL);
	1689	+ val &= ~(RKCIF_SKIP_EN(stream->id));
	1690	+ rkcif_write_register(dev, CIF_REG_MIPI_LVDS_CTRL, val);
	1691	+ stream->skip_info.skip_en = false;
	1692	+}
	1693	+
	1694	+static void rkcif_rdbk_with_tools(struct rkcif_stream *stream,
	1695	+ struct rkcif_rx_buffer *active_buf)
	1696	+{
	1697	+ unsigned long flags;
	1698	+
	1699	+ spin_lock_irqsave(&stream->tools_vdev->vbq_lock, flags);
	1700	+ if (stream->tools_vdev->state == RKCIF_STATE_STREAMING) {
	1701	+ list_add_tail(&active_buf->list, &stream->tools_vdev->buf_done_head);
	1702	+ if (!work_busy(&stream->tools_vdev->work))
	1703	+ schedule_work(&stream->tools_vdev->work);
	1704	+ }
	1705	+ spin_unlock_irqrestore(&stream->tools_vdev->vbq_lock, flags);
	1706	+}
	1707	+
	1708	+static void rkcif_rdbk_frame_end_toisp(struct rkcif_stream *stream,
	1709	+ struct rkcif_rx_buffer *buffer)
	1710	+{
	1711	+ struct rkcif_device *dev = stream->cifdev;
	1712	+ struct rkcif_sensor_info *sensor = &stream->cifdev->terminal_sensor;
	1713	+ u32 denominator, numerator;
	1714	+ u64 l_ts, m_ts, s_ts, time = 30000000LL;
	1715	+ int ret, fps = -1;
	1716	+ unsigned long flags;
	1717	+
	1718	+ spin_lock_irqsave(&dev->hdr_lock, flags);
	1719	+ if (dev->rdbk_rx_buf[stream->id]) {
	1720	+ list_add_tail(&dev->rdbk_rx_buf[stream->id]->list, &stream->rx_buf_head);
	1721	+ dev->rdbk_rx_buf[stream->id] = buffer;
	1722	+ } else {
	1723	+ dev->rdbk_rx_buf[stream->id] = buffer;
	1724	+ }
	1725	+
	1726	+ numerator = sensor->fi.interval.numerator;
	1727	+ denominator = sensor->fi.interval.denominator;
	1728	+ if (denominator && numerator)
	1729	+ time = numerator * 1000 / denominator * 1000 * 1000;
	1730	+
	1731	+ if (dev->hdr.hdr_mode == HDR_X3 &&
	1732	+ dev->rdbk_rx_buf[RDBK_L] &&
	1733	+ dev->rdbk_rx_buf[RDBK_M] &&
	1734	+ dev->rdbk_rx_buf[RDBK_S]) {
	1735	+ l_ts = dev->rdbk_rx_buf[RDBK_L]->fe_timestamp;
	1736	+ m_ts = dev->rdbk_rx_buf[RDBK_M]->fe_timestamp;
	1737	+ s_ts = dev->rdbk_rx_buf[RDBK_S]->fe_timestamp;
	1738	+
	1739	+ if (m_ts < l_ts \|\| s_ts < m_ts) {
	1740	+ v4l2_err(&dev->v4l2_dev,
	1741	+ "s/m/l frame err, timestamp s:%lld m:%lld l:%lld\n",
	1742	+ s_ts, m_ts, l_ts);
	1743	+ goto RDBK_TOISP_UNMATCH;
	1744	+ }
	1745	+
	1746	+ if ((m_ts - l_ts) > time \|\| (s_ts - m_ts) > time) {
	1747	+ ret = v4l2_subdev_call(sensor->sd,
	1748	+ video,
	1749	+ g_frame_interval,
	1750	+ &sensor->fi);
	1751	+ if (!ret) {
	1752	+ denominator = sensor->fi.interval.denominator;
	1753	+ numerator = sensor->fi.interval.numerator;
	1754	+ if (denominator && numerator) {
	1755	+ time = numerator * 1000 / denominator * 1000 * 1000;
	1756	+ fps = denominator / numerator;
	1757	+ }
	1758	+ }
	1759	+
	1760	+ if ((m_ts - l_ts) > time \|\| (s_ts - m_ts) > time) {
	1761	+ v4l2_err(&dev->v4l2_dev,
	1762	+ "timestamp no match, s:%lld m:%lld l:%lld, fps:%d\n",
	1763	+ s_ts, m_ts, l_ts, fps);
	1764	+ goto RDBK_TOISP_UNMATCH;
	1765	+ }
	1766	+ }
	1767	+ dev->rdbk_rx_buf[RDBK_M]->dbufs.sequence = dev->rdbk_rx_buf[RDBK_L]->dbufs.sequence;
	1768	+ dev->rdbk_rx_buf[RDBK_S]->dbufs.sequence = dev->rdbk_rx_buf[RDBK_L]->dbufs.sequence;
	1769	+ rkcif_s_rx_buffer(dev, &dev->rdbk_rx_buf[RDBK_L]->dbufs);
	1770	+ rkcif_s_rx_buffer(dev, &dev->rdbk_rx_buf[RDBK_M]->dbufs);
	1771	+ rkcif_s_rx_buffer(dev, &dev->rdbk_rx_buf[RDBK_S]->dbufs);
	1772	+ rkcif_rdbk_with_tools(&dev->stream[RDBK_L], dev->rdbk_rx_buf[RDBK_L]);
	1773	+ rkcif_rdbk_with_tools(&dev->stream[RDBK_M], dev->rdbk_rx_buf[RDBK_M]);
	1774	+ rkcif_rdbk_with_tools(&dev->stream[RDBK_S], dev->rdbk_rx_buf[RDBK_S]);
	1775	+ atomic_dec(&dev->stream[RDBK_L].buf_cnt);
	1776	+ atomic_dec(&dev->stream[RDBK_M].buf_cnt);
	1777	+ atomic_dec(&dev->stream[RDBK_S].buf_cnt);
	1778	+ dev->rdbk_rx_buf[RDBK_L] = NULL;
	1779	+ dev->rdbk_rx_buf[RDBK_M] = NULL;
	1780	+ dev->rdbk_rx_buf[RDBK_S] = NULL;
	1781	+ } else if (dev->hdr.hdr_mode == HDR_X2 &&
	1782	+ dev->rdbk_rx_buf[RDBK_L] && dev->rdbk_rx_buf[RDBK_M]) {
	1783	+ l_ts = dev->rdbk_rx_buf[RDBK_L]->fe_timestamp;
	1784	+ s_ts = dev->rdbk_rx_buf[RDBK_M]->fe_timestamp;
	1785	+
	1786	+ if (s_ts < l_ts) {
	1787	+ v4l2_err(&dev->v4l2_dev,
	1788	+ "s/l frame err, timestamp s:%lld l:%lld\n",
	1789	+ s_ts, l_ts);
	1790	+ goto RDBK_TOISP_UNMATCH;
	1791	+ }
	1792	+
	1793	+ if ((s_ts - l_ts) > time) {
	1794	+ ret = v4l2_subdev_call(sensor->sd,
	1795	+ video,
	1796	+ g_frame_interval,
	1797	+ &sensor->fi);
	1798	+ if (!ret) {
	1799	+ denominator = sensor->fi.interval.denominator;
	1800	+ numerator = sensor->fi.interval.numerator;
	1801	+ if (denominator && numerator) {
	1802	+ time = numerator * 1000 / denominator * 1000 * 1000;
	1803	+ fps = denominator / numerator;
	1804	+ }
	1805	+ }
	1806	+ if ((s_ts - l_ts) > time) {
	1807	+ v4l2_err(&dev->v4l2_dev,
	1808	+ "timestamp no match, s:%lld l:%lld, fps:%d\n",
	1809	+ s_ts, l_ts, fps);
	1810	+ goto RDBK_TOISP_UNMATCH;
	1811	+ }
	1812	+ }
	1813	+ dev->rdbk_rx_buf[RDBK_M]->dbufs.sequence = dev->rdbk_rx_buf[RDBK_L]->dbufs.sequence;
	1814	+ rkcif_s_rx_buffer(dev, &dev->rdbk_rx_buf[RDBK_L]->dbufs);
	1815	+ rkcif_s_rx_buffer(dev, &dev->rdbk_rx_buf[RDBK_M]->dbufs);
	1816	+ rkcif_rdbk_with_tools(&dev->stream[RDBK_L], dev->rdbk_rx_buf[RDBK_L]);
	1817	+ rkcif_rdbk_with_tools(&dev->stream[RDBK_M], dev->rdbk_rx_buf[RDBK_M]);
	1818	+ atomic_dec(&dev->stream[RDBK_L].buf_cnt);
	1819	+ atomic_dec(&dev->stream[RDBK_M].buf_cnt);
	1820	+ dev->rdbk_rx_buf[RDBK_L] = NULL;
	1821	+ dev->rdbk_rx_buf[RDBK_M] = NULL;
	1822	+ }
	1823	+
	1824	+ spin_unlock_irqrestore(&dev->hdr_lock, flags);
	1825	+ return;
	1826	+
	1827	+RDBK_TOISP_UNMATCH:
	1828	+ spin_unlock_irqrestore(&dev->hdr_lock, flags);
	1829	+}
	1830	+
	1831	+static void rkcif_write_buff_addr_multi_dev_combine(struct rkcif_stream *stream,
	1832	+ u32 frm_addr_y, u32 frm_addr_uv,
	1833	+ u32 buff_addr_y, u32 buff_addr_cbcr,
	1834	+ bool is_dummy_buf)
	1835	+{
	1836	+ struct rkcif_device *dev = stream->cifdev;
	1837	+ struct rkmodule_capture_info *capture_info = &dev->channels[stream->id].capture_info;
	1838	+ u32 addr_y, addr_cbcr;
	1839	+ int addr_offset = 0;
	1840	+ int i = 0;
	1841	+ int tmp_host_index = dev->csi_host_idx;
	1842	+
	1843	+ for (i = 0; i < capture_info->multi_dev.dev_num; i++) {
	1844	+ if (is_dummy_buf) {
	1845	+ addr_y = buff_addr_y;
	1846	+ } else {
	1847	+ addr_offset = dev->channels[stream->id].left_virtual_width;
	1848	+ addr_y = buff_addr_y + addr_offset * i;
	1849	+ }
	1850	+ dev->csi_host_idx = capture_info->multi_dev.dev_idx[i];
	1851	+ rkcif_write_register(dev, frm_addr_y, addr_y);
	1852	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW &&
	1853	+ frm_addr_uv && buff_addr_cbcr) {
	1854	+ if (is_dummy_buf) {
	1855	+ addr_cbcr = buff_addr_cbcr;
	1856	+ } else {
	1857	+ addr_offset = dev->channels[stream->id].left_virtual_width;
	1858	+ addr_cbcr = buff_addr_cbcr + addr_offset * i;
	1859	+ }
	1860	+ rkcif_write_register(dev, frm_addr_uv, addr_cbcr);
	1861	+ }
	1862	+ }
	1863	+ dev->csi_host_idx = tmp_host_index;
	1864	+}
	1865	+
	1866	+static void rkcif_assign_new_buffer_init_toisp(struct rkcif_stream *stream,
	1867	+ int channel_id)
	1868	+{
	1869	+ struct rkcif_device *dev = stream->cifdev;
	1870	+ struct rkcif_rx_buffer *rx_buf;
	1871	+ struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
	1872	+ struct rkmodule_capture_info *capture_info = &dev->channels[channel_id].capture_info;
	1873	+ u32 frm0_addr_y;
	1874	+ u32 frm1_addr_y;
	1875	+ u32 buff_addr_y;
	1876	+ unsigned long flags;
	1877	+
	1878	+ if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
	1879	+ mbus_cfg->type == V4L2_MBUS_CSI2_CPHY \|\|
	1880	+ mbus_cfg->type == V4L2_MBUS_CCP2) {
	1881	+ frm0_addr_y = get_reg_index_of_frm0_y_addr(channel_id);
	1882	+ frm1_addr_y = get_reg_index_of_frm1_y_addr(channel_id);
	1883	+ } else {
	1884	+ frm0_addr_y = get_dvp_reg_index_of_frm0_y_addr(channel_id);
	1885	+ frm1_addr_y = get_dvp_reg_index_of_frm1_y_addr(channel_id);
	1886	+ }
	1887	+
	1888	+ spin_lock_irqsave(&stream->vbq_lock, flags);
	1889	+
	1890	+ if (!stream->curr_buf_toisp) {
	1891	+ if (!list_empty(&stream->rx_buf_head)) {
	1892	+ rx_buf = list_first_entry(&stream->rx_buf_head,
	1893	+ struct rkcif_rx_buffer,
	1894	+ list);
	1895	+ if (rx_buf) {
	1896	+ list_del(&rx_buf->list);
	1897	+ stream->curr_buf_toisp = rx_buf;
	1898	+ }
	1899	+ }
	1900	+ }
	1901	+
	1902	+ if (stream->curr_buf_toisp) {
	1903	+ buff_addr_y = stream->curr_buf_toisp->dummy.dma_addr;
	1904	+ if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	1905	+ rkcif_write_buff_addr_multi_dev_combine(stream, frm0_addr_y, 0,
	1906	+ buff_addr_y, 0, false);
	1907	+ } else {
	1908	+ rkcif_write_register(dev, frm0_addr_y, buff_addr_y);
	1909	+ }
	1910	+ }
	1911	+
	1912	+ if (!stream->next_buf_toisp) {
	1913	+ if (!list_empty(&stream->rx_buf_head)) {
	1914	+ rx_buf = list_first_entry(&stream->rx_buf_head,
	1915	+ struct rkcif_rx_buffer, list);
	1916	+ if (rx_buf) {
	1917	+ list_del(&rx_buf->list);
	1918	+ stream->next_buf_toisp = rx_buf;
	1919	+ } else {
	1920	+ stream->next_buf_toisp = stream->curr_buf_toisp;
	1921	+ }
	1922	+ } else {
	1923	+ stream->next_buf_toisp = stream->curr_buf_toisp;
	1924	+ }
	1925	+ }
	1926	+
	1927	+ if (stream->next_buf_toisp) {
	1928	+ buff_addr_y = stream->next_buf_toisp->dummy.dma_addr;
	1929	+ if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	1930	+ rkcif_write_buff_addr_multi_dev_combine(stream, frm1_addr_y, 0,
	1931	+ buff_addr_y, 0, false);
	1932	+ } else {
	1933	+ rkcif_write_register(dev, frm1_addr_y, buff_addr_y);
	1934	+ }
	1935	+ }
	1936	+
	1937	+ spin_unlock_irqrestore(&stream->vbq_lock, flags);
	1938	+ stream->buf_owner = RKCIF_DMAEN_BY_ISP;
	1939	+}
	1940	+
	1941	+static int rkcif_assign_new_buffer_update_toisp(struct rkcif_stream *stream,
	1942	+ int channel_id)
	1943	+{
	1944	+ struct rkcif_device *dev = stream->cifdev;
	1945	+ struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
	1946	+ struct rkmodule_capture_info *capture_info = &dev->channels[channel_id].capture_info;
	1947	+ struct rkcif_rx_buffer *buffer = NULL;
	1948	+ struct rkcif_rx_buffer *active_buf = NULL;
	1949	+ struct sditf_priv *priv = dev->sditf[0];
	1950	+ u32 frm_addr_y, buff_addr_y;
	1951	+ unsigned long flags;
	1952	+
	1953	+ if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
	1954	+ mbus_cfg->type == V4L2_MBUS_CSI2_CPHY \|\|
	1955	+ mbus_cfg->type == V4L2_MBUS_CCP2) {
	1956	+ frm_addr_y = stream->frame_phase & CIF_CSI_FRAME0_READY ?
	1957	+ get_reg_index_of_frm0_y_addr(channel_id) :
	1958	+ get_reg_index_of_frm1_y_addr(channel_id);
	1959	+ } else {
	1960	+ frm_addr_y = stream->frame_phase & CIF_CSI_FRAME0_READY ?
	1961	+ get_dvp_reg_index_of_frm0_y_addr(channel_id) :
	1962	+ get_dvp_reg_index_of_frm1_y_addr(channel_id);
	1963	+ }
	1964	+ spin_lock_irqsave(&stream->vbq_lock, flags);
	1965	+ if (!list_empty(&stream->rx_buf_head)) {
	1966	+ if (stream->frame_phase == CIF_CSI_FRAME0_READY) {
	1967	+ if (stream->curr_buf_toisp == stream->next_buf_toisp)
	1968	+ active_buf = NULL;
	1969	+ else
	1970	+ active_buf = stream->curr_buf_toisp;
	1971	+
	1972	+ buffer = list_first_entry(&stream->rx_buf_head,
	1973	+ struct rkcif_rx_buffer, list);
	1974	+ if (buffer) {
	1975	+ list_del(&buffer->list);
	1976	+ stream->curr_buf_toisp = buffer;
	1977	+ }
	1978	+ if (priv && priv->mode.rdbk_mode == RKISP_VICAP_RDBK_AUTO) {
	1979	+ if (!active_buf)
	1980	+ goto out_get_buf;
	1981	+ if (stream->frame_idx == 1)
	1982	+ active_buf->dbufs.is_first = true;
	1983	+ active_buf->dbufs.sequence = stream->frame_idx - 1;
	1984	+ active_buf->dbufs.timestamp = stream->readout.fs_timestamp;
	1985	+ active_buf->fe_timestamp = ktime_get_ns();
	1986	+ stream->last_frame_idx = stream->frame_idx;
	1987	+ if (dev->hdr.hdr_mode == NO_HDR) {
	1988	+ rkcif_s_rx_buffer(dev, &active_buf->dbufs);
	1989	+ if (dev->is_support_tools && stream->tools_vdev)
	1990	+ rkcif_rdbk_with_tools(stream, active_buf);
	1991	+ atomic_dec(&stream->buf_cnt);
	1992	+ } else {
	1993	+ rkcif_rdbk_frame_end_toisp(stream, active_buf);
	1994	+ }
	1995	+ } else {
	1996	+ rkcif_s_rx_buffer(dev, &active_buf->dbufs);
	1997	+ if (dev->is_support_tools && stream->tools_vdev)
	1998	+ rkcif_rdbk_with_tools(stream, active_buf);
	1999	+ }
	2000	+ } else if (stream->frame_phase == CIF_CSI_FRAME1_READY) {
	2001	+ if (stream->curr_buf_toisp == stream->next_buf_toisp)
	2002	+ active_buf = NULL;
	2003	+ else
	2004	+ active_buf = stream->next_buf_toisp;
	2005	+ buffer = list_first_entry(&stream->rx_buf_head,
	2006	+ struct rkcif_rx_buffer, list);
	2007	+ if (buffer) {
	2008	+ list_del(&buffer->list);
	2009	+ stream->next_buf_toisp = buffer;
	2010	+ }
	2011	+ if (priv && priv->mode.rdbk_mode == RKISP_VICAP_RDBK_AUTO) {
	2012	+ if (!active_buf)
	2013	+ goto out_get_buf;
	2014	+ if (stream->frame_idx == 1)
	2015	+ active_buf->dbufs.is_first = true;
	2016	+ active_buf->dbufs.sequence = stream->frame_idx - 1;
	2017	+ active_buf->dbufs.timestamp = stream->readout.fs_timestamp;
	2018	+ active_buf->fe_timestamp = ktime_get_ns();
	2019	+ stream->last_frame_idx = stream->frame_idx;
	2020	+ if (dev->hdr.hdr_mode == NO_HDR) {
	2021	+ rkcif_s_rx_buffer(dev, &active_buf->dbufs);
	2022	+ if (dev->is_support_tools && stream->tools_vdev)
	2023	+ rkcif_rdbk_with_tools(stream, active_buf);
	2024	+ atomic_dec(&stream->buf_cnt);
	2025	+ } else {
	2026	+ rkcif_rdbk_frame_end_toisp(stream, active_buf);
	2027	+ }
	2028	+ } else {
	2029	+ rkcif_s_rx_buffer(dev, &active_buf->dbufs);
	2030	+ if (dev->is_support_tools && stream->tools_vdev)
	2031	+ rkcif_rdbk_with_tools(stream, active_buf);
	2032	+ }
	2033	+ }
	2034	+ if (stream->lack_buf_cnt)
	2035	+ stream->lack_buf_cnt--;
	2036	+ } else {
	2037	+ if (priv->mode.rdbk_mode == RKISP_VICAP_ONLINE)
	2038	+ goto out_get_buf;
	2039	+ if (stream->lack_buf_cnt < 2)
	2040	+ stream->lack_buf_cnt++;
	2041	+ if (dev->hw_dev->dummy_buf.vaddr) {
	2042	+ if (stream->frame_phase == CIF_CSI_FRAME0_READY) {
	2043	+ active_buf = stream->curr_buf_toisp;
	2044	+ stream->curr_buf_toisp = NULL;
	2045	+ } else {
	2046	+ active_buf = stream->next_buf_toisp;
	2047	+ stream->next_buf_toisp = NULL;
	2048	+ }
	2049	+ } else if (stream->curr_buf_toisp && stream->next_buf_toisp &&
	2050	+ stream->curr_buf_toisp != stream->next_buf_toisp) {
	2051	+ if (stream->frame_phase == CIF_CSI_FRAME0_READY) {
	2052	+ active_buf = stream->curr_buf_toisp;
	2053	+ stream->curr_buf_toisp = stream->next_buf_toisp;
	2054	+ buffer = stream->next_buf_toisp;
	2055	+ } else if (stream->frame_phase == CIF_CSI_FRAME1_READY) {
	2056	+ active_buf = stream->next_buf_toisp;
	2057	+ stream->next_buf_toisp = stream->curr_buf_toisp;
	2058	+ buffer = stream->curr_buf_toisp;
	2059	+ }
	2060	+ if (stream->cifdev->rdbk_debug)
	2061	+ v4l2_info(&stream->cifdev->v4l2_dev,
	2062	+ "stream[%d] hold buf %x\n",
	2063	+ stream->id,
	2064	+ (u32)stream->next_buf_toisp->dummy.dma_addr);
	2065	+ }
	2066	+ if (active_buf) {
	2067	+ if (stream->frame_idx == 1)
	2068	+ active_buf->dbufs.is_first = true;
	2069	+ active_buf->dbufs.sequence = stream->frame_idx - 1;
	2070	+ active_buf->dbufs.timestamp = stream->readout.fs_timestamp;
	2071	+ active_buf->fe_timestamp = ktime_get_ns();
	2072	+ stream->last_frame_idx = stream->frame_idx;
	2073	+ if (dev->hdr.hdr_mode == NO_HDR) {
	2074	+ rkcif_s_rx_buffer(dev, &active_buf->dbufs);
	2075	+ if (dev->is_support_tools && stream->tools_vdev)
	2076	+ rkcif_rdbk_with_tools(stream, active_buf);
	2077	+ atomic_dec(&stream->buf_cnt);
	2078	+ } else {
	2079	+ rkcif_rdbk_frame_end_toisp(stream, active_buf);
	2080	+ }
	2081	+ } else {
	2082	+ if (stream->cifdev->rdbk_debug && dev->hw_dev->dummy_buf.vaddr)
	2083	+ v4l2_info(&stream->cifdev->v4l2_dev,
	2084	+ "stream[%d] loss frame %d\n",
	2085	+ stream->id,
	2086	+ stream->frame_idx - 1);
	2087	+ }
	2088	+ if (dev->is_support_tools && stream->tools_vdev && stream->curr_buf_toisp)
	2089	+ rkcif_rdbk_with_tools(stream, stream->curr_buf_toisp);
	2090	+ }
	2091	+
	2092	+out_get_buf:
	2093	+ stream->frame_phase_cache = stream->frame_phase;
	2094	+ if (buffer) {
	2095	+ buff_addr_y = buffer->dummy.dma_addr;
	2096	+ if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	2097	+ rkcif_write_buff_addr_multi_dev_combine(stream, frm_addr_y, 0,
	2098	+ buff_addr_y, 0, false);
	2099	+ } else {
	2100	+ rkcif_write_register(dev, frm_addr_y, buff_addr_y);
	2101	+ }
	2102	+ if (dev->rdbk_debug > 1 &&
	2103	+ stream->frame_idx < 15)
	2104	+ v4l2_info(&dev->v4l2_dev,
	2105	+ "stream[%d] update, seq %d, reg %x, buf %x\n",
	2106	+ stream->id,
	2107	+ stream->frame_idx - 1,
	2108	+ frm_addr_y, (u32)buffer->dummy.dma_addr);
	2109	+ } else if (dev->hw_dev->dummy_buf.vaddr && priv &&
	2110	+ priv->mode.rdbk_mode == RKISP_VICAP_RDBK_AUTO) {
	2111	+ buff_addr_y = dev->hw_dev->dummy_buf.dma_addr;
	2112	+ if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	2113	+ rkcif_write_buff_addr_multi_dev_combine(stream, frm_addr_y, 0,
	2114	+ buff_addr_y, 0, true);
	2115	+ } else {
	2116	+ rkcif_write_register(dev, frm_addr_y, buff_addr_y);
	2117	+ }
	2118	+ }
	2119	+ spin_unlock_irqrestore(&stream->vbq_lock, flags);
	2120	+ return 0;
	2121	+}
	2122	+
	2123	+static int rkcif_assign_new_buffer_pingpong_toisp(struct rkcif_stream *stream,
	2124	+ int init, int channel_id)
	2125	+{
	2126	+ int ret = 0;
	2127	+
	2128	+ if (init)
	2129	+ rkcif_assign_new_buffer_init_toisp(stream, channel_id);
	2130	+ else
	2131	+ ret = rkcif_assign_new_buffer_update_toisp(stream, channel_id);
	2132	+ return ret;
	2133	+}
	2134	+
	2135	+void rkcif_assign_check_buffer_update_toisp(struct rkcif_stream *stream)
	2136	+{
	2137	+ struct rkcif_device *dev = stream->cifdev;
	2138	+ struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
	2139	+ struct rkcif_rx_buffer *buffer = NULL;
	2140	+ struct rkmodule_capture_info *capture_info = &dev->channels[stream->id].capture_info;
	2141	+ struct rkcif_rx_buffer *active_buf = NULL;
	2142	+ u32 frm_addr_y, buff_addr_y;
	2143	+ u32 vblank = 0;
	2144	+ u32 vblank_ns = 0;
	2145	+ u64 cur_time = 0;
	2146	+ int frame_phase = 0;
	2147	+ int frame_phase_next = 0;
	2148	+ bool is_early_update = false;
	2149	+
	2150	+ if (stream->curr_buf_toisp != stream->next_buf_toisp) {
	2151	+ if (dev->rdbk_debug > 2 &&
	2152	+ stream->frame_idx < 15)
	2153	+ v4l2_info(&dev->v4l2_dev,
	2154	+ "stream[%d] addr check not equal 0x%x 0x%x\n",
	2155	+ stream->id,
	2156	+ (u32)stream->curr_buf_toisp->dummy.dma_addr,
	2157	+ (u32)stream->next_buf_toisp->dummy.dma_addr);
	2158	+ return;
	2159	+ }
	2160	+ if (!dev->sensor_linetime)
	2161	+ dev->sensor_linetime = rkcif_get_linetime(stream);
	2162	+ vblank = rkcif_get_sensor_vblank(dev);
	2163	+ vblank_ns = vblank * dev->sensor_linetime;
	2164	+ cur_time = ktime_get_ns();
	2165	+
	2166	+ if (dev->chip_id > CHIP_RK3568_CIF &&
	2167	+ dev->hdr.hdr_mode == NO_HDR &&
	2168	+ cur_time - stream->readout.fe_timestamp < (vblank_ns - 500000) &&
	2169	+ stream->lack_buf_cnt == 2 &&
	2170	+ stream->frame_idx > stream->last_frame_idx) {
	2171	+ is_early_update = true;
	2172	+ frame_phase = stream->frame_phase & CIF_CSI_FRAME0_READY ?
	2173	+ CIF_CSI_FRAME1_READY : CIF_CSI_FRAME0_READY;
	2174	+ frame_phase_next = stream->frame_phase & CIF_CSI_FRAME0_READY ?
	2175	+ CIF_CSI_FRAME0_READY : CIF_CSI_FRAME1_READY;
	2176	+ } else {
	2177	+ frame_phase = stream->frame_phase;
	2178	+ }
	2179	+ if (dev->rdbk_debug > 2 &&
	2180	+ stream->frame_idx < 15)
	2181	+ v4l2_info(&dev->v4l2_dev,
	2182	+ "stream[%d] check update, cur %lld, fe %lld, vb %u lack_buf %d\n",
	2183	+ stream->id,
	2184	+ cur_time, stream->readout.fe_timestamp,
	2185	+ vblank_ns, stream->lack_buf_cnt);
	2186	+ if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
	2187	+ mbus_cfg->type == V4L2_MBUS_CSI2_CPHY \|\|
	2188	+ mbus_cfg->type == V4L2_MBUS_CCP2) {
	2189	+ frm_addr_y = frame_phase & CIF_CSI_FRAME0_READY ?
	2190	+ get_reg_index_of_frm0_y_addr(stream->id) :
	2191	+ get_reg_index_of_frm1_y_addr(stream->id);
	2192	+ } else {
	2193	+ frm_addr_y = frame_phase & CIF_CSI_FRAME0_READY ?
	2194	+ get_dvp_reg_index_of_frm0_y_addr(stream->id) :
	2195	+ get_dvp_reg_index_of_frm1_y_addr(stream->id);
	2196	+ }
	2197	+ if (!list_empty(&stream->rx_buf_head)) {
	2198	+ if (frame_phase == CIF_CSI_FRAME0_READY) {
	2199	+ active_buf = stream->curr_buf_toisp;
	2200	+ buffer = list_first_entry(&stream->rx_buf_head,
	2201	+ struct rkcif_rx_buffer, list);
	2202	+ if (buffer) {
	2203	+ list_del(&buffer->list);
	2204	+ stream->curr_buf_toisp = buffer;
	2205	+ buff_addr_y = stream->curr_buf_toisp->dummy.dma_addr;
	2206	+ if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	2207	+ rkcif_write_buff_addr_multi_dev_combine(stream,
	2208	+ frm_addr_y, 0,
	2209	+ buff_addr_y, 0,
	2210	+ false);
	2211	+ } else {
	2212	+ rkcif_write_register(dev, frm_addr_y, buff_addr_y);
	2213	+ }
	2214	+ if (dev->rdbk_debug > 1 &&
	2215	+ stream->frame_idx < 15)
	2216	+ v4l2_info(&dev->v4l2_dev,
	2217	+ "stream[%d] check update, seq %d, addr 0x%x, buf 0x%x\n",
	2218	+ stream->id,
	2219	+ stream->frame_idx - 1, frm_addr_y,
	2220	+ (u32)stream->curr_buf_toisp->dummy.dma_addr);
	2221	+ }
	2222	+ } else if (frame_phase == CIF_CSI_FRAME1_READY) {
	2223	+ active_buf = stream->next_buf_toisp;
	2224	+ buffer = list_first_entry(&stream->rx_buf_head,
	2225	+ struct rkcif_rx_buffer, list);
	2226	+ if (buffer) {
	2227	+ list_del(&buffer->list);
	2228	+ stream->next_buf_toisp = buffer;
	2229	+ buff_addr_y = stream->next_buf_toisp->dummy.dma_addr;
	2230	+ if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	2231	+ rkcif_write_buff_addr_multi_dev_combine(stream,
	2232	+ frm_addr_y, 0,
	2233	+ buff_addr_y, 0,
	2234	+ false);
	2235	+ } else {
	2236	+ rkcif_write_register(dev, frm_addr_y, buff_addr_y);
	2237	+ }
	2238	+ if (dev->rdbk_debug > 1 &&
	2239	+ stream->frame_idx < 15)
	2240	+ v4l2_info(&dev->v4l2_dev,
	2241	+ "stream[%d] check update, seq %d, addr 0x%x, buf 0x%x\n",
	2242	+ stream->id,
	2243	+ stream->frame_idx - 1, frm_addr_y,
	2244	+ (u32)stream->next_buf_toisp->dummy.dma_addr);
	2245	+ }
	2246	+ }
	2247	+ if (stream->lack_buf_cnt)
	2248	+ stream->lack_buf_cnt--;
	2249	+ }
	2250	+ if (is_early_update) {
	2251	+ if (dev->rdbk_debug > 1 &&
	2252	+ stream->frame_idx < 15)
	2253	+ v4l2_info(&dev->v4l2_dev,
	2254	+ "stream[%d] early update, seq %d\n",
	2255	+ stream->id,
	2256	+ stream->frame_idx - 1);
	2257	+ if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
	2258	+ mbus_cfg->type == V4L2_MBUS_CSI2_CPHY)
	2259	+ rkcif_write_register_or(dev, CIF_REG_MIPI_LVDS_CTRL, 0x00010000);
	2260	+ else
	2261	+ rkcif_write_register_or(dev, CIF_REG_DVP_CTRL, 0x00010000);
	2262	+ if (active_buf) {
	2263	+ active_buf->dbufs.sequence = stream->frame_idx - 1;
	2264	+ active_buf->dbufs.timestamp = stream->readout.fs_timestamp;
	2265	+ stream->last_frame_idx = stream->frame_idx;
	2266	+ rkcif_s_rx_buffer(dev, &active_buf->dbufs);
	2267	+ }
	2268	+ if (dev->hw_dev->dummy_buf.vaddr)
	2269	+ return;
	2270	+ if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
	2271	+ mbus_cfg->type == V4L2_MBUS_CSI2_CPHY \|\|
	2272	+ mbus_cfg->type == V4L2_MBUS_CCP2) {
	2273	+ frm_addr_y = frame_phase_next & CIF_CSI_FRAME0_READY ?
	2274	+ get_reg_index_of_frm0_y_addr(stream->id) :
	2275	+ get_reg_index_of_frm1_y_addr(stream->id);
	2276	+ } else {
	2277	+ frm_addr_y = frame_phase_next & CIF_CSI_FRAME0_READY ?
	2278	+ get_dvp_reg_index_of_frm0_y_addr(stream->id) :
	2279	+ get_dvp_reg_index_of_frm1_y_addr(stream->id);
	2280	+ }
	2281	+ if (frame_phase == CIF_CSI_FRAME0_READY)
	2282	+ stream->next_buf_toisp = stream->curr_buf_toisp;
	2283	+ else
	2284	+ stream->curr_buf_toisp = stream->next_buf_toisp;
	2285	+ buff_addr_y = stream->curr_buf_toisp->dummy.dma_addr;
	2286	+ if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	2287	+ rkcif_write_buff_addr_multi_dev_combine(stream, frm_addr_y, 0,
	2288	+ buff_addr_y, 0, false);
	2289	+ } else {
	2290	+ rkcif_write_register(dev, frm_addr_y, buff_addr_y);
	2291	+ }
	2292	+ }
1279	2293	}
1280	2294
1281	2295	static void rkcif_assign_new_buffer_init(struct rkcif_stream *stream,
..	..	@@ -1285,11 +2299,13 @@
1285	2299	struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
1286	2300	u32 frm0_addr_y, frm0_addr_uv;
1287	2301	u32 frm1_addr_y, frm1_addr_uv;
	2302	+ u32 buff_addr_y, buff_addr_cbcr;
1288	2303	unsigned long flags;
1289		- struct rkcif_dummy_buffer *dummy_buf = &dev->dummy_buf;
	2304	+ struct rkcif_dummy_buffer *dummy_buf = &dev->hw_dev->dummy_buf;
1290	2305	struct csi_channel_info *channel = &dev->channels[channel_id];
1291	2306
1292		- if (mbus_cfg->type == V4L2_MBUS_CSI2 \|\|
	2307	+ if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
	2308	+ mbus_cfg->type == V4L2_MBUS_CSI2_CPHY \|\|
1293	2309	mbus_cfg->type == V4L2_MBUS_CCP2) {
1294	2310	frm0_addr_y = get_reg_index_of_frm0_y_addr(channel_id);
1295	2311	frm0_addr_uv = get_reg_index_of_frm0_uv_addr(channel_id);
..	..	@@ -1309,53 +2325,117 @@
1309	2325	stream->curr_buf = list_first_entry(&stream->buf_head,
1310	2326	struct rkcif_buffer,
1311	2327	queue);
	2328	+ v4l2_dbg(4, rkcif_debug, &dev->v4l2_dev, "%s %d, stream[%d] buf idx %d\n",
	2329	+ __func__, __LINE__, stream->id, stream->curr_buf->vb.vb2_buf.index);
1312	2330	list_del(&stream->curr_buf->queue);
1313	2331	}
1314	2332	}
1315	2333
1316	2334	if (stream->curr_buf) {
1317		- rkcif_write_register(dev, frm0_addr_y,
1318		- stream->curr_buf->buff_addr[RKCIF_PLANE_Y]);
1319		- if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
1320		- rkcif_write_register(dev, frm0_addr_uv,
1321		- stream->curr_buf->buff_addr[RKCIF_PLANE_CBCR]);
	2335	+ buff_addr_y = stream->curr_buf->buff_addr[RKCIF_PLANE_Y];
	2336	+ buff_addr_cbcr = stream->curr_buf->buff_addr[RKCIF_PLANE_CBCR];
	2337	+ if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	2338	+ rkcif_write_buff_addr_multi_dev_combine(stream,
	2339	+ frm0_addr_y,
	2340	+ frm0_addr_uv,
	2341	+ buff_addr_y,
	2342	+ buff_addr_cbcr,
	2343	+ false);
	2344	+ } else {
	2345	+ rkcif_write_register(dev, frm0_addr_y,
	2346	+ stream->curr_buf->buff_addr[RKCIF_PLANE_Y]);
	2347	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	2348	+ rkcif_write_register(dev, frm0_addr_uv,
	2349	+ stream->curr_buf->buff_addr[RKCIF_PLANE_CBCR]);
	2350	+ }
1322	2351	} else {
1323	2352	if (dummy_buf->vaddr) {
1324		- rkcif_write_register(dev, frm0_addr_y, dummy_buf->dma_addr);
1325		- if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
1326		- rkcif_write_register(dev, frm0_addr_uv, dummy_buf->dma_addr);
	2353	+ buff_addr_y = dummy_buf->dma_addr;
	2354	+ buff_addr_cbcr = dummy_buf->dma_addr;
	2355	+ if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	2356	+ rkcif_write_buff_addr_multi_dev_combine(stream,
	2357	+ frm0_addr_y,
	2358	+ frm0_addr_uv,
	2359	+ buff_addr_y,
	2360	+ buff_addr_cbcr,
	2361	+ true);
	2362	+ } else {
	2363	+ rkcif_write_register(dev, frm0_addr_y, buff_addr_y);
	2364	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	2365	+ rkcif_write_register(dev, frm0_addr_uv, buff_addr_cbcr);
	2366	+ }
	2367	+ } else {
	2368	+ if (stream->lack_buf_cnt < 2)
	2369	+ stream->lack_buf_cnt++;
1327	2370	}
1328	2371	}
1329	2372
1330	2373	if (stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED) {
1331	2374	stream->next_buf = stream->curr_buf;
1332	2375	if (stream->next_buf) {
1333		- rkcif_write_register(dev, frm1_addr_y,
1334		- stream->next_buf->buff_addr[RKCIF_PLANE_Y] + (channel->virtual_width / 2));
1335		- if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
1336		- rkcif_write_register(dev, frm1_addr_uv,
1337		- stream->next_buf->buff_addr[RKCIF_PLANE_CBCR] + (channel->virtual_width / 2));
	2376	+ buff_addr_y = stream->next_buf->buff_addr[RKCIF_PLANE_Y];
	2377	+ buff_addr_cbcr = stream->next_buf->buff_addr[RKCIF_PLANE_CBCR];
	2378	+ if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	2379	+ rkcif_write_buff_addr_multi_dev_combine(stream,
	2380	+ frm1_addr_y,
	2381	+ frm1_addr_uv,
	2382	+ buff_addr_y,
	2383	+ buff_addr_cbcr,
	2384	+ false);
	2385	+ } else {
	2386	+ rkcif_write_register(dev, frm1_addr_y,
	2387	+ buff_addr_y + (channel->virtual_width / 2));
	2388	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	2389	+ rkcif_write_register(dev, frm1_addr_uv,
	2390	+ buff_addr_cbcr + (channel->virtual_width / 2));
	2391	+ }
1338	2392	}
1339	2393	} else {
1340	2394	if (!stream->next_buf) {
1341	2395	if (!list_empty(&stream->buf_head)) {
1342	2396	stream->next_buf = list_first_entry(&stream->buf_head,
1343	2397	struct rkcif_buffer, queue);
	2398	+ v4l2_dbg(4, rkcif_debug, &dev->v4l2_dev, "%s %d, stream[%d] buf idx %d\n",
	2399	+ __func__, __LINE__, stream->id, stream->next_buf->vb.vb2_buf.index);
1344	2400	list_del(&stream->next_buf->queue);
1345	2401	}
1346	2402	}
1347	2403
1348		- if (stream->next_buf) {
1349		- rkcif_write_register(dev, frm1_addr_y,
1350		- stream->next_buf->buff_addr[RKCIF_PLANE_Y]);
1351		- if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
1352		- rkcif_write_register(dev, frm1_addr_uv,
1353		- stream->next_buf->buff_addr[RKCIF_PLANE_CBCR]);
1354		- } else {
1355		- if (dummy_buf->vaddr) {
	2404	+ if (!stream->next_buf && dummy_buf->vaddr) {
	2405	+ buff_addr_y = dummy_buf->dma_addr;
	2406	+ buff_addr_cbcr = dummy_buf->dma_addr;
	2407	+ if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	2408	+ rkcif_write_buff_addr_multi_dev_combine(stream,
	2409	+ frm1_addr_y,
	2410	+ frm1_addr_uv,
	2411	+ buff_addr_y,
	2412	+ buff_addr_cbcr,
	2413	+ true);
	2414	+ } else {
1356	2415	rkcif_write_register(dev, frm1_addr_y, dummy_buf->dma_addr);
1357	2416	if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
1358	2417	rkcif_write_register(dev, frm1_addr_uv, dummy_buf->dma_addr);
	2418	+ }
	2419	+
	2420	+ } else if (!stream->next_buf && stream->curr_buf) {
	2421	+ stream->next_buf = stream->curr_buf;
	2422	+ if (stream->lack_buf_cnt < 2)
	2423	+ stream->lack_buf_cnt++;
	2424	+ }
	2425	+ if (stream->next_buf) {
	2426	+ buff_addr_y = stream->next_buf->buff_addr[RKCIF_PLANE_Y];
	2427	+ buff_addr_cbcr = stream->next_buf->buff_addr[RKCIF_PLANE_CBCR];
	2428	+ if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	2429	+ rkcif_write_buff_addr_multi_dev_combine(stream,
	2430	+ frm1_addr_y,
	2431	+ frm1_addr_uv,
	2432	+ buff_addr_y,
	2433	+ buff_addr_cbcr,
	2434	+ false);
	2435	+ } else {
	2436	+ rkcif_write_register(dev, frm1_addr_y, buff_addr_y);
	2437	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	2438	+ rkcif_write_register(dev, frm1_addr_uv, buff_addr_cbcr);
1359	2439	}
1360	2440	}
1361	2441	}
..	..	@@ -1388,22 +2468,26 @@
1388	2468	}
1389	2469	}
1390	2470	}
1391		-
	2471	+ stream->buf_owner = RKCIF_DMAEN_BY_VICAP;
1392	2472	}
1393	2473
1394	2474	static int rkcif_assign_new_buffer_update(struct rkcif_stream *stream,
1395		- int channel_id)
	2475	+ int channel_id)
1396	2476	{
1397	2477	struct rkcif_device *dev = stream->cifdev;
1398		- struct rkcif_dummy_buffer *dummy_buf = &dev->dummy_buf;
	2478	+ struct rkcif_dummy_buffer *dummy_buf = &dev->hw_dev->dummy_buf;
1399	2479	struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
1400	2480	struct rkcif_buffer *buffer = NULL;
1401	2481	u32 frm_addr_y, frm_addr_uv;
1402	2482	struct csi_channel_info *channel = &dev->channels[channel_id];
	2483	+ struct rkisp_rx_buf *dbufs = NULL;
	2484	+ struct dma_buf *dbuf = NULL;
1403	2485	int ret = 0;
	2486	+ u32 buff_addr_y, buff_addr_cbcr;
1404	2487	unsigned long flags;
1405	2488
1406		- if (mbus_cfg->type == V4L2_MBUS_CSI2 \|\|
	2489	+ if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
	2490	+ mbus_cfg->type == V4L2_MBUS_CSI2_CPHY \|\|
1407	2491	mbus_cfg->type == V4L2_MBUS_CCP2) {
1408	2492	frm_addr_y = stream->frame_phase & CIF_CSI_FRAME0_READY ?
1409	2493	get_reg_index_of_frm0_y_addr(channel_id) :
..	..	@@ -1420,20 +2504,43 @@
1420	2504	get_dvp_reg_index_of_frm1_uv_addr(channel_id);
1421	2505	}
1422	2506
	2507	+ if (stream->to_stop_dma) {
	2508	+ if (stream->dma_en & RKCIF_DMAEN_BY_ISP) {
	2509	+ v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev, "%s %d\n", __func__, __LINE__);
	2510	+ goto stop_dma;
	2511	+ } else {
	2512	+ if (stream->frame_phase == CIF_CSI_FRAME0_READY)
	2513	+ stream->curr_buf = NULL;
	2514	+ else
	2515	+ stream->next_buf = NULL;
	2516	+ v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev, "%s %d\n", __func__, __LINE__);
	2517	+ return -EINVAL;
	2518	+ }
	2519	+ }
	2520	+
1423	2521	spin_lock_irqsave(&stream->vbq_lock, flags);
1424	2522	if (!list_empty(&stream->buf_head)) {
	2523	+
1425	2524	if (!dummy_buf->vaddr &&
1426	2525	stream->curr_buf == stream->next_buf &&
1427	2526	stream->cif_fmt_in->field != V4L2_FIELD_INTERLACED)
1428	2527	ret = -EINVAL;
	2528	+
1429	2529	if (stream->frame_phase == CIF_CSI_FRAME0_READY) {
	2530	+ if (!stream->curr_buf)
	2531	+ ret = -EINVAL;
1430	2532	stream->curr_buf = list_first_entry(&stream->buf_head,
1431	2533	struct rkcif_buffer, queue);
1432	2534	if (stream->curr_buf) {
1433	2535	list_del(&stream->curr_buf->queue);
1434	2536	buffer = stream->curr_buf;
	2537	+ v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev,
	2538	+ "stream[%d] update curr_buf 0x%x, buf idx %d\n",
	2539	+ stream->id, buffer->buff_addr[0], stream->curr_buf->vb.vb2_buf.index);
1435	2540	}
1436	2541	} else if (stream->frame_phase == CIF_CSI_FRAME1_READY) {
	2542	+ if (!stream->next_buf)
	2543	+ ret = -EINVAL;
1437	2544	if (stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED) {
1438	2545	if (stream->next_buf != stream->curr_buf) {
1439	2546	stream->next_buf = stream->curr_buf;
..	..	@@ -1448,14 +2555,17 @@
1448	2555	if (stream->next_buf) {
1449	2556	list_del(&stream->next_buf->queue);
1450	2557	buffer = stream->next_buf;
	2558	+ v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev,
	2559	+ "stream[%d] update next_buf 0x%x, buf idx %d\n",
	2560	+ stream->id, buffer->buff_addr[0], stream->next_buf->vb.vb2_buf.index);
1451	2561	}
1452	2562	}
1453	2563	}
1454		- } else {
	2564	+ } else if (!(stream->dma_en & RKCIF_DMAEN_BY_ISP)) {
1455	2565	buffer = NULL;
1456	2566	if (dummy_buf->vaddr) {
1457	2567	if (stream->frame_phase == CIF_CSI_FRAME0_READY) {
1458		- stream->curr_buf = NULL;
	2568	+ stream->curr_buf = NULL;
1459	2569	} else if (stream->frame_phase == CIF_CSI_FRAME1_READY) {
1460	2570	if (stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED) {
1461	2571	stream->next_buf = stream->curr_buf;
..	..	@@ -1464,7 +2574,8 @@
1464	2574	stream->next_buf = NULL;
1465	2575	}
1466	2576	}
1467		- } else if (stream->curr_buf != stream->next_buf) {
	2577	+ } else if (stream->curr_buf && stream->next_buf &&
	2578	+ stream->curr_buf != stream->next_buf) {
1468	2579	if (stream->frame_phase == CIF_CSI_FRAME0_READY) {
1469	2580	stream->curr_buf = stream->next_buf;
1470	2581	buffer = stream->next_buf;
..	..	@@ -1472,49 +2583,175 @@
1472	2583	stream->next_buf = stream->curr_buf;
1473	2584	buffer = stream->curr_buf;
1474	2585	}
1475		-
	2586	+ if (stream->lack_buf_cnt < 2)
	2587	+ stream->lack_buf_cnt++;
	2588	+ } else {
	2589	+ stream->curr_buf = NULL;
	2590	+ stream->next_buf = NULL;
	2591	+ if (stream->lack_buf_cnt < 2)
	2592	+ stream->lack_buf_cnt++;
1476	2593	}
1477		-
1478	2594	}
1479	2595	stream->frame_phase_cache = stream->frame_phase;
1480		- spin_unlock_irqrestore(&stream->vbq_lock, flags);
1481	2596
1482	2597	if (buffer) {
	2598	+ buff_addr_y = buffer->buff_addr[RKCIF_PLANE_Y];
	2599	+ buff_addr_cbcr = buffer->buff_addr[RKCIF_PLANE_CBCR];
1483	2600	if (stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED &&
1484	2601	stream->frame_phase == CIF_CSI_FRAME1_READY) {
1485		- rkcif_write_register(dev, frm_addr_y,
1486		- buffer->buff_addr[RKCIF_PLANE_Y] + (channel->virtual_width / 2));
1487		- if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
1488		- rkcif_write_register(dev, frm_addr_uv,
1489		- buffer->buff_addr[RKCIF_PLANE_CBCR] + (channel->virtual_width / 2));
	2602	+ if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	2603	+ rkcif_write_buff_addr_multi_dev_combine(stream,
	2604	+ frm_addr_y,
	2605	+ frm_addr_uv,
	2606	+ buff_addr_y,
	2607	+ buff_addr_cbcr,
	2608	+ false);
	2609	+ } else {
	2610	+ rkcif_write_register(dev, frm_addr_y,
	2611	+ buff_addr_y + (channel->virtual_width / 2));
	2612	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	2613	+ rkcif_write_register(dev, frm_addr_uv,
	2614	+ buff_addr_cbcr + (channel->virtual_width / 2));
	2615	+ }
1490	2616	} else {
1491		- rkcif_write_register(dev, frm_addr_y,
1492		- buffer->buff_addr[RKCIF_PLANE_Y]);
1493		- if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
1494		- rkcif_write_register(dev, frm_addr_uv,
1495		- buffer->buff_addr[RKCIF_PLANE_CBCR]);
	2617	+ if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	2618	+ rkcif_write_buff_addr_multi_dev_combine(stream,
	2619	+ frm_addr_y,
	2620	+ frm_addr_uv,
	2621	+ buff_addr_y,
	2622	+ buff_addr_cbcr,
	2623	+ false);
	2624	+ } else {
	2625	+ rkcif_write_register(dev, frm_addr_y, buff_addr_y);
	2626	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	2627	+ rkcif_write_register(dev, frm_addr_uv, buff_addr_cbcr);
	2628	+ }
	2629	+ }
	2630	+ if (stream->dma_en & RKCIF_DMAEN_BY_ISP) {
	2631	+ if (stream->buf_replace_cnt < 2)
	2632	+ stream->buf_replace_cnt++;
	2633	+ if (stream->frame_phase == CIF_CSI_FRAME0_READY &&
	2634	+ stream->next_buf)
	2635	+ dbuf = stream->next_buf->dbuf;
	2636	+ else if (stream->frame_phase == CIF_CSI_FRAME1_READY &&
	2637	+ stream->curr_buf)
	2638	+ dbuf = stream->curr_buf->dbuf;
	2639	+
	2640	+ if (dbuf) {
	2641	+ list_for_each_entry(dbufs, &stream->rx_buf_head_vicap, list) {
	2642	+ if (dbufs->dbuf == dbuf)
	2643	+ break;
	2644	+ }
	2645	+ }
	2646	+ if (dbufs)
	2647	+ rkcif_s_rx_buffer(dev, dbufs);
1496	2648	}
1497	2649	} else {
1498		- if (dummy_buf->vaddr) {
1499		- rkcif_write_register(dev, frm_addr_y, dummy_buf->dma_addr);
1500		- if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
1501		- rkcif_write_register(dev, frm_addr_uv, dummy_buf->dma_addr);
	2650	+ if (stream->dma_en & RKCIF_DMAEN_BY_ISP) {
	2651	+ buff_addr_y = stream->curr_buf_toisp->dummy.dma_addr;
	2652	+ if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE)
	2653	+ rkcif_write_buff_addr_multi_dev_combine(stream,
	2654	+ frm_addr_y, 0,
	2655	+ buff_addr_y, 0, false);
	2656	+ else
	2657	+ rkcif_write_register(dev, frm_addr_y, buff_addr_y);
	2658	+ if (stream->frame_phase == CIF_CSI_FRAME0_READY &&
	2659	+ stream->next_buf)
	2660	+ dbuf = stream->next_buf->dbuf;
	2661	+ else if (stream->frame_phase == CIF_CSI_FRAME1_READY &&
	2662	+ stream->curr_buf)
	2663	+ dbuf = stream->curr_buf->dbuf;
	2664	+
	2665	+ if (dbuf) {
	2666	+ list_for_each_entry(dbufs, &stream->rx_buf_head_vicap, list)
	2667	+ if (dbufs->dbuf == dbuf)
	2668	+ break;
	2669	+ } else {
	2670	+ dbufs = &stream->curr_buf_toisp->dbufs;
	2671	+ }
	2672	+ rkcif_s_rx_buffer(dev, dbufs);
	2673	+ if (stream->curr_buf && stream->frame_phase == CIF_CSI_FRAME0_READY) {
	2674	+ stream->curr_buf = NULL;
	2675	+ if (stream->buf_replace_cnt)
	2676	+ stream->buf_replace_cnt--;
	2677	+ } else if (stream->next_buf && stream->frame_phase == CIF_CSI_FRAME1_READY) {
	2678	+ stream->next_buf = NULL;
	2679	+ if (stream->buf_replace_cnt)
	2680	+ stream->buf_replace_cnt--;
	2681	+ }
	2682	+ } else if (dummy_buf->vaddr) {
	2683	+
	2684	+ if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	2685	+ buff_addr_y = dummy_buf->dma_addr;
	2686	+ buff_addr_cbcr = dummy_buf->dma_addr;
	2687	+ rkcif_write_buff_addr_multi_dev_combine(stream,
	2688	+ frm_addr_y,
	2689	+ frm_addr_uv,
	2690	+ buff_addr_y,
	2691	+ buff_addr_cbcr,
	2692	+ true);
	2693	+ } else {
	2694	+ rkcif_write_register(dev, frm_addr_y, dummy_buf->dma_addr);
	2695	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	2696	+ rkcif_write_register(dev, frm_addr_uv, dummy_buf->dma_addr);
	2697	+ }
	2698	+ dev->err_state \|= (RKCIF_ERR_ID0_NOT_BUF << stream->id);
	2699	+ dev->irq_stats.not_active_buf_cnt[stream->id]++;
	2700	+
1502	2701	} else {
1503	2702	ret = -EINVAL;
	2703	+ stream->curr_buf = NULL;
	2704	+ stream->next_buf = NULL;
	2705	+ dev->err_state \|= (RKCIF_ERR_ID0_NOT_BUF << stream->id);
	2706	+ dev->irq_stats.not_active_buf_cnt[stream->id]++;
1504	2707	}
1505		- v4l2_info(&dev->v4l2_dev,
1506		- "not active buffer, skip current frame, %s stream[%d]\n",
1507		- (mbus_cfg->type == V4L2_MBUS_CSI2 \|\|
1508		- mbus_cfg->type == V4L2_MBUS_CCP2) ? "mipi/lvds" : "dvp",
1509		- stream->id);
1510	2708	}
	2709	+ spin_unlock_irqrestore(&stream->vbq_lock, flags);
1511	2710	return ret;
	2711	+stop_dma:
	2712	+ if (stream->buf_replace_cnt) {
	2713	+ spin_lock_irqsave(&stream->vbq_lock, flags);
	2714	+ buff_addr_y = stream->curr_buf_toisp->dummy.dma_addr;
	2715	+ if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE)
	2716	+ rkcif_write_buff_addr_multi_dev_combine(stream,
	2717	+ frm_addr_y, 0,
	2718	+ buff_addr_y, 0, false);
	2719	+ else
	2720	+ rkcif_write_register(dev, frm_addr_y, buff_addr_y);
	2721	+ if (stream->frame_phase == CIF_CSI_FRAME0_READY &&
	2722	+ stream->next_buf)
	2723	+ dbuf = stream->next_buf->dbuf;
	2724	+ else if (stream->frame_phase == CIF_CSI_FRAME1_READY &&
	2725	+ stream->curr_buf)
	2726	+ dbuf = stream->curr_buf->dbuf;
	2727	+
	2728	+ if (dbuf) {
	2729	+ list_for_each_entry(dbufs, &stream->rx_buf_head_vicap, list)
	2730	+ if (dbufs->dbuf == dbuf)
	2731	+ break;
	2732	+ } else {
	2733	+ dbufs = &stream->curr_buf_toisp->dbufs;
	2734	+ }
	2735	+ if (dbufs)
	2736	+ rkcif_s_rx_buffer(dev, dbufs);
	2737	+
	2738	+ if (stream->frame_phase == CIF_CSI_FRAME0_READY &&
	2739	+ stream->curr_buf) {
	2740	+ stream->curr_buf = NULL;
	2741	+ } else if (stream->frame_phase == CIF_CSI_FRAME1_READY &&
	2742	+ stream->next_buf) {
	2743	+ stream->next_buf = NULL;
	2744	+ }
	2745	+ stream->buf_replace_cnt--;
	2746	+ spin_unlock_irqrestore(&stream->vbq_lock, flags);
	2747	+ }
	2748	+ return -EINVAL;
1512	2749	}
1513	2750
1514	2751	static int rkcif_get_new_buffer_wake_up_mode(struct rkcif_stream *stream)
1515	2752	{
1516	2753	struct rkcif_device *dev = stream->cifdev;
1517		- struct rkcif_dummy_buffer *dummy_buf = &dev->dummy_buf;
	2754	+ struct rkcif_dummy_buffer *dummy_buf = &dev->hw_dev->dummy_buf;
1518	2755	int ret = 0;
1519	2756	unsigned long flags;
1520	2757
..	..	@@ -1535,6 +2772,8 @@
1535	2772	list_del(&stream->next_buf->queue);
1536	2773	}
1537	2774	stream->is_buf_active = true;
	2775	+ if (stream->lack_buf_cnt)
	2776	+ stream->lack_buf_cnt--;
1538	2777	} else {
1539	2778	stream->is_buf_active = false;
1540	2779	if (dummy_buf->vaddr) {
..	..	@@ -1551,8 +2790,15 @@
1551	2790	stream->frame_phase_cache = CIF_CSI_FRAME1_READY;
1552	2791	}
1553	2792	stream->is_buf_active = true;
	2793	+ if (stream->lack_buf_cnt < 2)
	2794	+ stream->lack_buf_cnt++;
1554	2795	} else {
1555		- ret = -EINVAL;
	2796	+ if (dev->chip_id < CHIP_RK3588_CIF)
	2797	+ ret = -EINVAL;
	2798	+ else
	2799	+ ret = 0;
	2800	+ if (stream->lack_buf_cnt < 2)
	2801	+ stream->lack_buf_cnt++;
1556	2802	}
1557	2803	}
1558	2804	spin_unlock_irqrestore(&stream->vbq_lock, flags);
..	..	@@ -1563,15 +2809,18 @@
1563	2809	static int rkcif_update_new_buffer_wake_up_mode(struct rkcif_stream *stream)
1564	2810	{
1565	2811	struct rkcif_device *dev = stream->cifdev;
1566		- struct rkcif_dummy_buffer *dummy_buf = &dev->dummy_buf;
	2812	+ struct rkcif_dummy_buffer *dummy_buf = &dev->hw_dev->dummy_buf;
1567	2813	struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
	2814	+ struct rkmodule_capture_info *capture_info = &dev->channels[stream->id].capture_info;
1568	2815	struct rkcif_buffer *buffer = NULL;
1569	2816	u32 frm_addr_y, frm_addr_uv;
	2817	+ u32 buff_addr_y, buff_addr_cbcr;
1570	2818	int channel_id = stream->id;
1571	2819	int ret = 0;
1572	2820	unsigned long flags;
1573	2821
1574		- if (mbus_cfg->type == V4L2_MBUS_CSI2 \|\|
	2822	+ if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
	2823	+ mbus_cfg->type == V4L2_MBUS_CSI2_CPHY \|\|
1575	2824	mbus_cfg->type == V4L2_MBUS_CCP2) {
1576	2825	frm_addr_y = stream->frame_phase & CIF_CSI_FRAME0_READY ?
1577	2826	get_reg_index_of_frm0_y_addr(channel_id) :
..	..	@@ -1596,25 +2845,122 @@
1596	2845	}
1597	2846	spin_unlock_irqrestore(&stream->vbq_lock, flags);
1598	2847	if (buffer) {
1599		- rkcif_write_register(dev, frm_addr_y,
1600		- buffer->buff_addr[RKCIF_PLANE_Y]);
1601		- if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
1602		- rkcif_write_register(dev, frm_addr_uv,
1603		- buffer->buff_addr[RKCIF_PLANE_CBCR]);
	2848	+ buff_addr_y = buffer->buff_addr[RKCIF_PLANE_Y];
	2849	+ buff_addr_cbcr = buffer->buff_addr[RKCIF_PLANE_CBCR];
	2850	+ if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	2851	+ rkcif_write_buff_addr_multi_dev_combine(stream, frm_addr_y,
	2852	+ frm_addr_uv,
	2853	+ buff_addr_y,
	2854	+ buff_addr_cbcr,
	2855	+ false);
	2856	+ } else {
	2857	+ rkcif_write_register(dev, frm_addr_y, buff_addr_y);
	2858	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	2859	+ rkcif_write_register(dev, frm_addr_uv, buff_addr_cbcr);
	2860	+ }
1604	2861	} else {
1605	2862	if (dummy_buf->vaddr) {
1606		- rkcif_write_register(dev, frm_addr_y, dummy_buf->dma_addr);
1607		- if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
1608		- rkcif_write_register(dev, frm_addr_uv, dummy_buf->dma_addr);
	2863	+ buff_addr_y = dummy_buf->dma_addr;
	2864	+ buff_addr_cbcr = dummy_buf->dma_addr;
	2865	+ if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	2866	+ rkcif_write_buff_addr_multi_dev_combine(stream,
	2867	+ frm_addr_y,
	2868	+ frm_addr_uv,
	2869	+ buff_addr_y,
	2870	+ buff_addr_cbcr,
	2871	+ true);
	2872	+ } else {
	2873	+ rkcif_write_register(dev, frm_addr_y, buff_addr_y);
	2874	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	2875	+ rkcif_write_register(dev, frm_addr_uv, buff_addr_cbcr);
	2876	+ }
	2877	+ } else {
	2878	+ if (dev->chip_id < CHIP_RK3588_CIF)
	2879	+ ret = -EINVAL;
	2880	+ else
	2881	+ ret = 0;
	2882	+ }
	2883	+ dev->err_state \|= (RKCIF_ERR_ID0_NOT_BUF << stream->id);
	2884	+ dev->irq_stats.not_active_buf_cnt[stream->id]++;
	2885	+ }
	2886	+
	2887	+ return ret;
	2888	+}
	2889	+
	2890	+static int rkcif_get_new_buffer_wake_up_mode_rdbk(struct rkcif_stream *stream)
	2891	+{
	2892	+ struct rkcif_rx_buffer *buffer = NULL;
	2893	+ struct rkcif_device *dev = stream->cifdev;
	2894	+ struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
	2895	+ int ret = 0;
	2896	+ unsigned long flags;
	2897	+ u32 frm_addr_y;
	2898	+ int frame_phase = 0;
	2899	+
	2900	+ spin_lock_irqsave(&stream->vbq_lock, flags);
	2901	+ if (!list_empty(&stream->rx_buf_head)) {
	2902	+ if (stream->line_int_cnt % 2) {
	2903	+ buffer = list_first_entry(&stream->rx_buf_head,
	2904	+ struct rkcif_rx_buffer, list);
	2905	+ if (buffer) {
	2906	+ list_del(&buffer->list);
	2907	+ stream->curr_buf_toisp = buffer;
	2908	+ }
	2909	+ frame_phase = CIF_CSI_FRAME0_READY;
	2910	+ } else {
	2911	+ buffer = list_first_entry(&stream->rx_buf_head,
	2912	+ struct rkcif_rx_buffer, list);
	2913	+ if (buffer) {
	2914	+ list_del(&buffer->list);
	2915	+ stream->next_buf_toisp = buffer;
	2916	+ }
	2917	+ frame_phase = CIF_CSI_FRAME1_READY;
	2918	+ }
	2919	+ if (stream->lack_buf_cnt)
	2920	+ stream->lack_buf_cnt--;
	2921	+ } else {
	2922	+ if (stream->lack_buf_cnt < 2)
	2923	+ stream->lack_buf_cnt++;
	2924	+ if (stream->curr_buf_toisp && stream->next_buf_toisp &&
	2925	+ stream->curr_buf_toisp != stream->next_buf_toisp) {
	2926	+ if (stream->line_int_cnt % 2)
	2927	+ stream->curr_buf_toisp = stream->next_buf_toisp;
	2928	+ else
	2929	+ stream->next_buf_toisp = stream->curr_buf_toisp;
	2930	+ buffer = stream->curr_buf_toisp;
	2931	+ ret = 0;
	2932	+ if (stream->cifdev->rdbk_debug)
	2933	+ v4l2_info(&stream->cifdev->v4l2_dev,
	2934	+ "stream[%d] hold buf %x\n",
	2935	+ stream->id,
	2936	+ (u32)stream->next_buf_toisp->dummy.dma_addr);
1609	2937	} else {
1610	2938	ret = -EINVAL;
1611	2939	}
1612		- v4l2_info(&dev->v4l2_dev,
1613		- "not active buffer, skip current frame, %s stream[%d]\n",
1614		- (mbus_cfg->type == V4L2_MBUS_CSI2 \|\|
1615		- mbus_cfg->type == V4L2_MBUS_CCP2) ? "mipi/lvds" : "dvp",
1616		- stream->id);
1617	2940	}
	2941	+ if (buffer) {
	2942	+ if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
	2943	+ mbus_cfg->type == V4L2_MBUS_CSI2_CPHY \|\|
	2944	+ mbus_cfg->type == V4L2_MBUS_CCP2) {
	2945	+ frm_addr_y = frame_phase & CIF_CSI_FRAME0_READY ?
	2946	+ get_reg_index_of_frm0_y_addr(stream->id) :
	2947	+ get_reg_index_of_frm1_y_addr(stream->id);
	2948	+ } else {
	2949	+ frm_addr_y = frame_phase & CIF_CSI_FRAME0_READY ?
	2950	+ get_dvp_reg_index_of_frm0_y_addr(stream->id) :
	2951	+ get_dvp_reg_index_of_frm1_y_addr(stream->id);
	2952	+ }
	2953	+ rkcif_write_register(dev, frm_addr_y,
	2954	+ buffer->dummy.dma_addr);
	2955	+ if (dev->rdbk_debug > 1 &&
	2956	+ stream->frame_idx < 15)
	2957	+ v4l2_info(&dev->v4l2_dev,
	2958	+ "stream[%d] rdbk update, seq %d, reg %x, buf %x\n",
	2959	+ stream->id,
	2960	+ stream->frame_idx - 1,
	2961	+ frm_addr_y, (u32)buffer->dummy.dma_addr);
	2962	+ }
	2963	+ spin_unlock_irqrestore(&stream->vbq_lock, flags);
1618	2964
1619	2965	return ret;
1620	2966	}
..	..	@@ -1623,7 +2969,7 @@
1623	2969	{
1624	2970	struct rkcif_device *dev = stream->cifdev;
1625	2971	struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
1626		- struct rkcif_dummy_buffer *dummy_buf = &dev->dummy_buf;
	2972	+ struct rkcif_dummy_buffer *dummy_buf = &dev->hw_dev->dummy_buf;
1627	2973	unsigned long flags;
1628	2974
1629	2975	spin_lock_irqsave(&stream->vbq_lock, flags);
..	..	@@ -1658,6 +3004,276 @@
1658	3004	rkcif_assign_new_buffer_init(stream, channel_id);
1659	3005	else
1660	3006	ret = rkcif_assign_new_buffer_update(stream, channel_id);
	3007	+ return ret;
	3008	+}
	3009	+
	3010	+static void rkcif_assign_new_buffer_init_rockit(struct rkcif_stream *stream,
	3011	+ int channel_id)
	3012	+{
	3013	+ struct rkcif_device *dev = stream->cifdev;
	3014	+ struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
	3015	+ u32 frm0_addr_y, frm0_addr_uv;
	3016	+ u32 frm1_addr_y, frm1_addr_uv;
	3017	+ unsigned long flags;
	3018	+ struct rkcif_dummy_buffer *dummy_buf = &dev->hw_dev->dummy_buf;
	3019	+ struct csi_channel_info *channel = &dev->channels[channel_id];
	3020	+
	3021	+ if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
	3022	+ mbus_cfg->type == V4L2_MBUS_CSI2_CPHY \|\|
	3023	+ mbus_cfg->type == V4L2_MBUS_CCP2) {
	3024	+ frm0_addr_y = get_reg_index_of_frm0_y_addr(channel_id);
	3025	+ frm0_addr_uv = get_reg_index_of_frm0_uv_addr(channel_id);
	3026	+ frm1_addr_y = get_reg_index_of_frm1_y_addr(channel_id);
	3027	+ frm1_addr_uv = get_reg_index_of_frm1_uv_addr(channel_id);
	3028	+ } else {
	3029	+ frm0_addr_y = get_dvp_reg_index_of_frm0_y_addr(channel_id);
	3030	+ frm0_addr_uv = get_dvp_reg_index_of_frm0_uv_addr(channel_id);
	3031	+ frm1_addr_y = get_dvp_reg_index_of_frm1_y_addr(channel_id);
	3032	+ frm1_addr_uv = get_dvp_reg_index_of_frm1_uv_addr(channel_id);
	3033	+ }
	3034	+
	3035	+ spin_lock_irqsave(&stream->vbq_lock, flags);
	3036	+
	3037	+ if (!stream->curr_buf_rockit) {
	3038	+ if (!list_empty(&stream->rockit_buf_head)) {
	3039	+ stream->curr_buf_rockit = list_first_entry(&stream->rockit_buf_head,
	3040	+ struct rkcif_buffer,
	3041	+ queue);
	3042	+ list_del(&stream->curr_buf_rockit->queue);
	3043	+ }
	3044	+ }
	3045	+
	3046	+ if (stream->curr_buf_rockit) {
	3047	+ rkcif_write_register(dev, frm0_addr_y,
	3048	+ stream->curr_buf_rockit->buff_addr[RKCIF_PLANE_Y]);
	3049	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	3050	+ rkcif_write_register(dev, frm0_addr_uv,
	3051	+ stream->curr_buf_rockit->buff_addr[RKCIF_PLANE_CBCR]);
	3052	+ } else {
	3053	+ if (dummy_buf->vaddr) {
	3054	+ rkcif_write_register(dev, frm0_addr_y, dummy_buf->dma_addr);
	3055	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	3056	+ rkcif_write_register(dev, frm0_addr_uv, dummy_buf->dma_addr);
	3057	+ } else {
	3058	+ if (stream->lack_buf_cnt < 2)
	3059	+ stream->lack_buf_cnt++;
	3060	+ }
	3061	+ }
	3062	+
	3063	+ if (stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED) {
	3064	+ stream->next_buf_rockit = stream->curr_buf_rockit;
	3065	+ if (stream->next_buf_rockit) {
	3066	+ rkcif_write_register(dev, frm1_addr_y,
	3067	+ stream->next_buf_rockit->buff_addr[RKCIF_PLANE_Y] + (channel->virtual_width / 2));
	3068	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	3069	+ rkcif_write_register(dev, frm1_addr_uv,
	3070	+ stream->next_buf_rockit->buff_addr[RKCIF_PLANE_CBCR] + (channel->virtual_width / 2));
	3071	+ }
	3072	+ } else {
	3073	+ if (!stream->next_buf_rockit) {
	3074	+ if (!list_empty(&stream->rockit_buf_head)) {
	3075	+ stream->next_buf_rockit = list_first_entry(&stream->rockit_buf_head,
	3076	+ struct rkcif_buffer, queue);
	3077	+ list_del(&stream->next_buf_rockit->queue);
	3078	+ }
	3079	+ }
	3080	+
	3081	+ if (stream->next_buf_rockit) {
	3082	+ rkcif_write_register(dev, frm1_addr_y,
	3083	+ stream->next_buf_rockit->buff_addr[RKCIF_PLANE_Y]);
	3084	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	3085	+ rkcif_write_register(dev, frm1_addr_uv,
	3086	+ stream->next_buf_rockit->buff_addr[RKCIF_PLANE_CBCR]);
	3087	+ } else {
	3088	+ if (dummy_buf->vaddr) {
	3089	+ rkcif_write_register(dev, frm1_addr_y, dummy_buf->dma_addr);
	3090	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	3091	+ rkcif_write_register(dev, frm1_addr_uv, dummy_buf->dma_addr);
	3092	+ } else {
	3093	+ if (stream->curr_buf_rockit) {
	3094	+ stream->next_buf_rockit = stream->curr_buf_rockit;
	3095	+ rkcif_write_register(dev, frm1_addr_y,
	3096	+ stream->next_buf_rockit->buff_addr[RKCIF_PLANE_Y]);
	3097	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	3098	+ rkcif_write_register(dev, frm1_addr_uv,
	3099	+ stream->next_buf_rockit->buff_addr[RKCIF_PLANE_CBCR]);
	3100	+ }
	3101	+ if (stream->lack_buf_cnt < 2)
	3102	+ stream->lack_buf_cnt++;
	3103	+ }
	3104	+ }
	3105	+ }
	3106	+ spin_unlock_irqrestore(&stream->vbq_lock, flags);
	3107	+
	3108	+ stream->is_dvp_yuv_addr_init = true;
	3109	+
	3110	+ /* for BT.656/BT.1120 multi channels function,
	3111	+ * yuv addr of unused channel must be set
	3112	+ */
	3113	+ if (mbus_cfg->type == V4L2_MBUS_BT656) {
	3114	+ int ch_id;
	3115	+
	3116	+ for (ch_id = 0; ch_id < RKCIF_MAX_STREAM_DVP; ch_id++) {
	3117	+ if (dev->stream[ch_id].is_dvp_yuv_addr_init)
	3118	+ continue;
	3119	+ if (dummy_buf->dma_addr) {
	3120	+ rkcif_write_register(dev,
	3121	+ get_dvp_reg_index_of_frm0_y_addr(ch_id),
	3122	+ dummy_buf->dma_addr);
	3123	+ rkcif_write_register(dev,
	3124	+ get_dvp_reg_index_of_frm0_uv_addr(ch_id),
	3125	+ dummy_buf->dma_addr);
	3126	+ rkcif_write_register(dev,
	3127	+ get_dvp_reg_index_of_frm1_y_addr(ch_id),
	3128	+ dummy_buf->dma_addr);
	3129	+ rkcif_write_register(dev,
	3130	+ get_dvp_reg_index_of_frm1_uv_addr(ch_id),
	3131	+ dummy_buf->dma_addr);
	3132	+ }
	3133	+ }
	3134	+ }
	3135	+ stream->buf_owner = RKCIF_DMAEN_BY_ROCKIT;
	3136	+}
	3137	+
	3138	+static int rkcif_assign_new_buffer_update_rockit(struct rkcif_stream *stream,
	3139	+ int channel_id)
	3140	+{
	3141	+ struct rkcif_device *dev = stream->cifdev;
	3142	+ struct rkcif_dummy_buffer *dummy_buf = &dev->hw_dev->dummy_buf;
	3143	+ struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
	3144	+ struct rkcif_buffer *buffer = NULL;
	3145	+ u32 frm_addr_y, frm_addr_uv;
	3146	+ struct csi_channel_info *channel = &dev->channels[channel_id];
	3147	+ int ret = 0;
	3148	+ unsigned long flags;
	3149	+
	3150	+ if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
	3151	+ mbus_cfg->type == V4L2_MBUS_CSI2_CPHY \|\|
	3152	+ mbus_cfg->type == V4L2_MBUS_CCP2) {
	3153	+ frm_addr_y = stream->frame_phase & CIF_CSI_FRAME0_READY ?
	3154	+ get_reg_index_of_frm0_y_addr(channel_id) :
	3155	+ get_reg_index_of_frm1_y_addr(channel_id);
	3156	+ frm_addr_uv = stream->frame_phase & CIF_CSI_FRAME0_READY ?
	3157	+ get_reg_index_of_frm0_uv_addr(channel_id) :
	3158	+ get_reg_index_of_frm1_uv_addr(channel_id);
	3159	+ } else {
	3160	+ frm_addr_y = stream->frame_phase & CIF_CSI_FRAME0_READY ?
	3161	+ get_dvp_reg_index_of_frm0_y_addr(channel_id) :
	3162	+ get_dvp_reg_index_of_frm1_y_addr(channel_id);
	3163	+ frm_addr_uv = stream->frame_phase & CIF_CSI_FRAME0_READY ?
	3164	+ get_dvp_reg_index_of_frm0_uv_addr(channel_id) :
	3165	+ get_dvp_reg_index_of_frm1_uv_addr(channel_id);
	3166	+ }
	3167	+
	3168	+ spin_lock_irqsave(&stream->vbq_lock, flags);
	3169	+ if (!list_empty(&stream->rockit_buf_head)) {
	3170	+
	3171	+ if (!dummy_buf->vaddr &&
	3172	+ stream->curr_buf_rockit == stream->next_buf_rockit &&
	3173	+ stream->cif_fmt_in->field != V4L2_FIELD_INTERLACED)
	3174	+ ret = -EINVAL;
	3175	+
	3176	+ if (stream->frame_phase == CIF_CSI_FRAME0_READY) {
	3177	+ if (!stream->curr_buf_rockit)
	3178	+ ret = -EINVAL;
	3179	+ stream->curr_buf_rockit = list_first_entry(&stream->rockit_buf_head,
	3180	+ struct rkcif_buffer, queue);
	3181	+ if (stream->curr_buf_rockit) {
	3182	+ list_del(&stream->curr_buf_rockit->queue);
	3183	+ buffer = stream->curr_buf_rockit;
	3184	+ }
	3185	+ } else if (stream->frame_phase == CIF_CSI_FRAME1_READY) {
	3186	+ if (!stream->next_buf_rockit)
	3187	+ ret = -EINVAL;
	3188	+ if (stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED) {
	3189	+ if (stream->next_buf_rockit != stream->curr_buf_rockit) {
	3190	+ stream->next_buf_rockit = stream->curr_buf_rockit;
	3191	+ buffer = stream->next_buf_rockit;
	3192	+ } else {
	3193	+ buffer = NULL;
	3194	+ }
	3195	+
	3196	+ } else {
	3197	+ stream->next_buf_rockit = list_first_entry(&stream->rockit_buf_head,
	3198	+ struct rkcif_buffer, queue);
	3199	+ if (stream->next_buf_rockit) {
	3200	+ list_del(&stream->next_buf_rockit->queue);
	3201	+ buffer = stream->next_buf_rockit;
	3202	+ }
	3203	+ }
	3204	+ }
	3205	+ } else {
	3206	+ buffer = NULL;
	3207	+ if (dummy_buf->vaddr) {
	3208	+ if (stream->frame_phase == CIF_CSI_FRAME0_READY) {
	3209	+ stream->curr_buf_rockit = NULL;
	3210	+ } else if (stream->frame_phase == CIF_CSI_FRAME1_READY) {
	3211	+ if (stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED) {
	3212	+ stream->next_buf_rockit = stream->curr_buf_rockit;
	3213	+ buffer = stream->next_buf_rockit;
	3214	+ } else {
	3215	+ stream->next_buf_rockit = NULL;
	3216	+ }
	3217	+ }
	3218	+ } else if (stream->curr_buf_rockit && stream->next_buf_rockit &&
	3219	+ stream->curr_buf_rockit != stream->next_buf_rockit) {
	3220	+ if (stream->frame_phase == CIF_CSI_FRAME0_READY) {
	3221	+ stream->curr_buf_rockit = stream->next_buf_rockit;
	3222	+ buffer = stream->next_buf_rockit;
	3223	+ } else if (stream->frame_phase == CIF_CSI_FRAME1_READY) {
	3224	+ stream->next_buf_rockit = stream->curr_buf_rockit;
	3225	+ buffer = stream->curr_buf_rockit;
	3226	+ }
	3227	+ if (stream->lack_buf_cnt < 2)
	3228	+ stream->lack_buf_cnt++;
	3229	+ } else {
	3230	+ if (stream->lack_buf_cnt < 2)
	3231	+ stream->lack_buf_cnt++;
	3232	+ }
	3233	+ }
	3234	+ stream->frame_phase_cache = stream->frame_phase;
	3235	+
	3236	+ if (buffer) {
	3237	+ if (stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED &&
	3238	+ stream->frame_phase == CIF_CSI_FRAME1_READY) {
	3239	+ rkcif_write_register(dev, frm_addr_y,
	3240	+ buffer->buff_addr[RKCIF_PLANE_Y] + (channel->virtual_width / 2));
	3241	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	3242	+ rkcif_write_register(dev, frm_addr_uv,
	3243	+ buffer->buff_addr[RKCIF_PLANE_CBCR] + (channel->virtual_width / 2));
	3244	+ } else {
	3245	+ rkcif_write_register(dev, frm_addr_y,
	3246	+ buffer->buff_addr[RKCIF_PLANE_Y]);
	3247	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	3248	+ rkcif_write_register(dev, frm_addr_uv,
	3249	+ buffer->buff_addr[RKCIF_PLANE_CBCR]);
	3250	+ }
	3251	+ } else {
	3252	+ if (dummy_buf->vaddr) {
	3253	+ rkcif_write_register(dev, frm_addr_y, dummy_buf->dma_addr);
	3254	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	3255	+ rkcif_write_register(dev, frm_addr_uv, dummy_buf->dma_addr);
	3256	+ dev->err_state \|= (RKCIF_ERR_ID0_NOT_BUF << stream->id);
	3257	+ dev->irq_stats.not_active_buf_cnt[stream->id]++;
	3258	+ } else {
	3259	+ ret = -EINVAL;
	3260	+ dev->err_state \|= (RKCIF_ERR_ID0_NOT_BUF << stream->id);
	3261	+ dev->irq_stats.not_active_buf_cnt[stream->id]++;
	3262	+ }
	3263	+ }
	3264	+ spin_unlock_irqrestore(&stream->vbq_lock, flags);
	3265	+ return ret;
	3266	+}
	3267	+
	3268	+static int rkcif_assign_new_buffer_pingpong_rockit(struct rkcif_stream *stream,
	3269	+ int init, int channel_id)
	3270	+{
	3271	+ int ret = 0;
	3272	+
	3273	+ if (init)
	3274	+ rkcif_assign_new_buffer_init_rockit(stream, channel_id);
	3275	+ else
	3276	+ ret = rkcif_assign_new_buffer_update_rockit(stream, channel_id);
1661	3277	return ret;
1662	3278	}
1663	3279
..	..	@@ -1709,7 +3325,7 @@
1709	3325	struct rkmodule_lvds_frm_sync_code *odd_sync_code = NULL;
1710	3326	struct rkmodule_lvds_frm_sync_code *even_sync_code = NULL;
1711	3327
1712		- if (dev->hdr.mode == NO_HDR) {
	3328	+ if (dev->hdr.hdr_mode == NO_HDR \|\| dev->hdr.hdr_mode == HDR_COMPR) {
1713	3329	frm_sync_code = &lvds_cfg->frm_sync_code[LVDS_CODE_GRP_LINEAR];
1714	3330	odd_sync_code = &frm_sync_code->odd_sync_code;
1715	3331	even_sync_code = odd_sync_code;
..	..	@@ -1717,12 +3333,12 @@
1717	3333	if (channel->id == RKCIF_STREAM_MIPI_ID0)
1718	3334	frm_sync_code = &lvds_cfg->frm_sync_code[LVDS_CODE_GRP_LONG];
1719	3335
1720		- if (dev->hdr.mode == HDR_X2) {
	3336	+ if (dev->hdr.hdr_mode == HDR_X2) {
1721	3337	if (channel->id == RKCIF_STREAM_MIPI_ID1)
1722	3338	frm_sync_code = &lvds_cfg->frm_sync_code[LVDS_CODE_GRP_SHORT];
1723	3339	else
1724	3340	frm_sync_code = &lvds_cfg->frm_sync_code[LVDS_CODE_GRP_LONG];
1725		- } else if (dev->hdr.mode == HDR_X3) {
	3341	+ } else if (dev->hdr.hdr_mode == HDR_X3) {
1726	3342	if (channel->id == RKCIF_STREAM_MIPI_ID1)
1727	3343	frm_sync_code = &lvds_cfg->frm_sync_code[LVDS_CODE_GRP_MEDIUM];
1728	3344	else if (channel->id == RKCIF_STREAM_MIPI_ID2)
..	..	@@ -1758,12 +3374,44 @@
1758	3374	}
1759	3375	}
1760	3376
	3377	+static unsigned char get_csi_fmt_val(const struct cif_input_fmt *cif_fmt_in,
	3378	+ struct csi_channel_info *csi_info)
	3379	+{
	3380	+ unsigned char csi_fmt_val = 0;
	3381	+
	3382	+ if (cif_fmt_in->mbus_code == MEDIA_BUS_FMT_SPD_2X8 \|\|
	3383	+ cif_fmt_in->mbus_code == MEDIA_BUS_FMT_EBD_1X8) {
	3384	+ switch (csi_info->data_bit) {
	3385	+ case 8:
	3386	+ csi_fmt_val = CSI_WRDDR_TYPE_RAW8;
	3387	+ break;
	3388	+ case 10:
	3389	+ csi_fmt_val = CSI_WRDDR_TYPE_RAW10;
	3390	+ break;
	3391	+ case 12:
	3392	+ csi_fmt_val = CSI_WRDDR_TYPE_RAW12;
	3393	+ break;
	3394	+ default:
	3395	+ csi_fmt_val = CSI_WRDDR_TYPE_RAW12;
	3396	+ break;
	3397	+ }
	3398	+ } else if (cif_fmt_in->csi_fmt_val == CSI_WRDDR_TYPE_RGB888 \|\|
	3399	+ cif_fmt_in->csi_fmt_val == CSI_WRDDR_TYPE_RGB565) {
	3400	+ csi_fmt_val = CSI_WRDDR_TYPE_RAW8;
	3401	+ } else {
	3402	+ csi_fmt_val = cif_fmt_in->csi_fmt_val;
	3403	+ }
	3404	+ return csi_fmt_val;
	3405	+}
	3406	+
1761	3407	static int rkcif_csi_channel_init(struct rkcif_stream *stream,
1762	3408	struct csi_channel_info *channel)
1763	3409	{
1764	3410	struct rkcif_device *dev = stream->cifdev;
	3411	+ struct sditf_priv *priv = dev->sditf[0];
1765	3412	const struct cif_output_fmt *fmt;
1766	3413	u32 fourcc;
	3414	+ int vc = dev->channels[stream->id].vc;
1767	3415
1768	3416	channel->enable = 1;
1769	3417	channel->width = stream->pixm.width;
..	..	@@ -1779,10 +3427,14 @@
1779	3427
1780	3428	if (channel->fmt_val == CSI_WRDDR_TYPE_RGB888)
1781	3429	channel->crop_st_x = 3 * stream->crop[CROP_SRC_ACT].left;
	3430	+ else if (channel->fmt_val == CSI_WRDDR_TYPE_RGB565)
	3431	+ channel->crop_st_x = 2 * stream->crop[CROP_SRC_ACT].left;
1782	3432	else
1783	3433	channel->crop_st_x = stream->crop[CROP_SRC_ACT].left;
1784	3434
1785	3435	channel->crop_st_y = stream->crop[CROP_SRC_ACT].top;
	3436	+ if (priv && priv->is_combine_mode && dev->sditf_cnt <= RKCIF_MAX_SDITF)
	3437	+ channel->crop_st_y *= dev->sditf_cnt;
1786	3438	channel->width = stream->crop[CROP_SRC_ACT].width;
1787	3439	channel->height = stream->crop[CROP_SRC_ACT].height;
1788	3440	} else {
..	..	@@ -1791,13 +3443,18 @@
1791	3443	channel->crop_en = 0;
1792	3444	}
1793	3445
1794		- fmt = find_output_fmt(stream, stream->pixm.pixelformat);
	3446	+ if (priv && priv->is_combine_mode && dev->sditf_cnt <= RKCIF_MAX_SDITF)
	3447	+ channel->height *= dev->sditf_cnt;
	3448	+
	3449	+ fmt = rkcif_find_output_fmt(stream, stream->pixm.pixelformat);
1795	3450	if (!fmt) {
1796	3451	v4l2_err(&dev->v4l2_dev, "can not find output format: 0x%x",
1797	3452	stream->pixm.pixelformat);
1798	3453	return -EINVAL;
1799	3454	}
1800	3455
	3456	+ if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE)
	3457	+ channel->width /= channel->capture_info.multi_dev.dev_num;
1801	3458	/*
1802	3459	* for mipi or lvds, when enable compact, the virtual width of raw10/raw12
1803	3460	* needs aligned with :ALIGN(bits_per_pixel * width / 8, 8), if enable 16bit mode
..	..	@@ -1805,13 +3462,24 @@
1805	3462	* writing of ddr, aliged with 256
1806	3463	*/
1807	3464	if (fmt->fmt_type == CIF_FMT_TYPE_RAW && stream->is_compact &&
1808		- fmt->csi_fmt_val != CSI_WRDDR_TYPE_RGB888) {
1809		- channel->virtual_width = ALIGN(channel->width * fmt->raw_bpp / 8, 256);
	3465	+ fmt->csi_fmt_val != CSI_WRDDR_TYPE_RGB888 &&
	3466	+ fmt->csi_fmt_val != CSI_WRDDR_TYPE_RGB565) {
	3467	+ if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	3468	+ channel->virtual_width = ALIGN(channel->width * 2 * fmt->raw_bpp / 8, 256);
	3469	+ channel->left_virtual_width = channel->width * fmt->raw_bpp / 8;
	3470	+ } else {
	3471	+ channel->virtual_width = ALIGN(channel->width * fmt->raw_bpp / 8, 256);
	3472	+ }
1810	3473	} else {
1811		- channel->virtual_width = ALIGN(channel->width * fmt->bpp[0] / 8, 8);
	3474	+ if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	3475	+ channel->virtual_width = ALIGN(channel->width * 2 * fmt->bpp[0] / 8, 8);
	3476	+ channel->left_virtual_width = ALIGN(channel->width * fmt->bpp[0] / 8, 8);
	3477	+ } else {
	3478	+ channel->virtual_width = ALIGN(channel->width * fmt->bpp[0] / 8, 8);
	3479	+ }
1812	3480	}
1813	3481
1814		- if (channel->fmt_val == CSI_WRDDR_TYPE_RGB888)
	3482	+ if (channel->fmt_val == CSI_WRDDR_TYPE_RGB888 \|\| channel->fmt_val == CSI_WRDDR_TYPE_RGB565)
1815	3483	channel->width = channel->width * fmt->bpp[0] / 8;
1816	3484	/*
1817	3485	* rk cif don't support output yuyv fmt data
..	..	@@ -1819,36 +3487,53 @@
1819	3487	* and the width is double Because the real input fmt is
1820	3488	* yuyv
1821	3489	*/
1822		- fourcc = stream->cif_fmt_out->fourcc;
	3490	+ fourcc = stream->cif_fmt_out->fourcc;
1823	3491	if (fourcc == V4L2_PIX_FMT_YUYV \|\| fourcc == V4L2_PIX_FMT_YVYU \|\|
1824	3492	fourcc == V4L2_PIX_FMT_UYVY \|\| fourcc == V4L2_PIX_FMT_VYUY) {
1825		- channel->fmt_val = CSI_WRDDR_TYPE_RAW8;
1826		- channel->width *= 2;
	3493	+ if (dev->chip_id < CHIP_RK3588_CIF) {
	3494	+ channel->fmt_val = CSI_WRDDR_TYPE_RAW8;
	3495	+ channel->width *= 2;
	3496	+ }
1827	3497	channel->virtual_width *= 2;
	3498	+ if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE)
	3499	+ channel->left_virtual_width *= 2;
1828	3500	}
1829	3501	if (stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED) {
1830	3502	channel->virtual_width *= 2;
1831	3503	channel->height /= 2;
1832	3504	}
	3505	+ if (stream->cif_fmt_in->mbus_code == MEDIA_BUS_FMT_EBD_1X8 \|\|
	3506	+ stream->cif_fmt_in->mbus_code == MEDIA_BUS_FMT_SPD_2X8) {
	3507	+ if (dev->channels[stream->id].data_type)
	3508	+ channel->data_type = dev->channels[stream->id].data_type;
	3509	+ else
	3510	+ channel->data_type = get_data_type(stream->cif_fmt_in->mbus_code,
	3511	+ channel->cmd_mode_en,
	3512	+ channel->dsi_input);
	3513	+ } else {
	3514	+ channel->data_type = get_data_type(stream->cif_fmt_in->mbus_code,
	3515	+ channel->cmd_mode_en,
	3516	+ channel->dsi_input);
	3517	+ }
	3518	+ channel->csi_fmt_val = get_csi_fmt_val(stream->cif_fmt_in,
	3519	+ &dev->channels[stream->id]);
1833	3520
1834		- channel->data_type = get_data_type(stream->cif_fmt_in->mbus_code,
1835		- channel->cmd_mode_en, channel->dsi_input);
1836		-
1837		- if ((dev->hdr.mode == NO_HDR && stream->vc >= 0) \|\|
1838		- (dev->hdr.mode == HDR_X2 && stream->vc > 1) \|\|
1839		- (dev->hdr.mode == HDR_X3 && stream->vc > 2))
1840		- channel->vc = stream->vc;
	3521	+ if (dev->hdr.hdr_mode == NO_HDR \|\|
	3522	+ dev->hdr.hdr_mode == HDR_COMPR \|\|
	3523	+ (dev->hdr.hdr_mode == HDR_X2 && stream->id > 1) \|\|
	3524	+ (dev->hdr.hdr_mode == HDR_X3 && stream->id > 2))
	3525	+ channel->vc = vc < 4 ? vc : channel->id;
1841	3526	else
1842	3527	channel->vc = channel->id;
1843		- v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev,
	3528	+ v4l2_dbg(1, rkcif_debug, &dev->v4l2_dev,
1844	3529	"%s: channel width %d, height %d, virtual_width %d, vc %d\n", __func__,
1845	3530	channel->width, channel->height, channel->virtual_width, channel->vc);
1846	3531	return 0;
1847	3532	}
1848	3533
1849	3534	static int rkcif_csi_channel_set(struct rkcif_stream *stream,
1850		- struct csi_channel_info *channel,
1851		- enum v4l2_mbus_type mbus_type)
	3535	+ struct csi_channel_info *channel,
	3536	+ enum v4l2_mbus_type mbus_type)
1852	3537	{
1853	3538	unsigned int val = 0x0;
1854	3539	struct rkcif_device *dev = stream->cifdev;
..	..	@@ -1869,10 +3554,9 @@
1869	3554	CSI_DMA_END_INTSTAT(channel->id) \|
1870	3555	CSI_LINE_INTSTAT(channel->id)));
1871	3556
1872		- /* enable id0 frame start int for sof(long frame, for hdr) */
1873		- if (channel->id == RKCIF_STREAM_MIPI_ID0)
1874		- rkcif_write_register_or(dev, CIF_REG_MIPI_LVDS_INTEN,
1875		- CSI_START_INTEN(channel->id));
	3557	+ rkcif_write_register_or(dev, CIF_REG_MIPI_LVDS_INTEN,
	3558	+ CSI_START_INTEN(channel->id));
	3559	+
1876	3560	if (detect_stream->is_line_wake_up) {
1877	3561	rkcif_write_register_or(dev, CIF_REG_MIPI_LVDS_INTEN,
1878	3562	CSI_LINE_INTEN(channel->id));
..	..	@@ -1891,15 +3575,15 @@
1891	3575	CIF_MIPI_LVDS_SW_HURRY_VALUE_RK1808(0x3) \|
1892	3576	CIF_MIPI_LVDS_SW_HURRY_ENABLE_RK1808);
1893	3577
1894		- val = CIF_MIPI_LVDS_SW_PRESS_VALUE(0x7) \|
	3578	+ val = CIF_MIPI_LVDS_SW_PRESS_VALUE(0x3) \|
1895	3579	CIF_MIPI_LVDS_SW_PRESS_ENABLE \|
1896		- CIF_MIPI_LVDS_SW_HURRY_VALUE(0x7) \|
	3580	+ CIF_MIPI_LVDS_SW_HURRY_VALUE(0x3) \|
1897	3581	CIF_MIPI_LVDS_SW_HURRY_ENABLE \|
1898	3582	CIF_MIPI_LVDS_SW_WATER_LINE_25 \|
1899	3583	CIF_MIPI_LVDS_SW_WATER_LINE_ENABLE;
1900		- if (mbus_type == V4L2_MBUS_CSI2) {
	3584	+ if (mbus_type == V4L2_MBUS_CSI2_DPHY) {
1901	3585	val &= ~CIF_MIPI_LVDS_SW_SEL_LVDS;
1902		- } else if (mbus_type == V4L2_MBUS_CCP2) {
	3586	+ } else if (mbus_type == V4L2_MBUS_CCP2) {
1903	3587	if (channel->fmt_val == CSI_WRDDR_TYPE_RAW12)
1904	3588	val \|= CIF_MIPI_LVDS_SW_LVDS_WIDTH_12BITS;
1905	3589	else if (channel->fmt_val == CSI_WRDDR_TYPE_RAW10)
..	..	@@ -1934,7 +3618,7 @@
1934	3618	RKCIF_YUV_ADDR_STATE_INIT,
1935	3619	channel->id);
1936	3620
1937		- if (mbus_type == V4L2_MBUS_CSI2) {
	3621	+ if (mbus_type == V4L2_MBUS_CSI2_DPHY) {
1938	3622	//need always enable crop
1939	3623	val = CSI_ENABLE_CAPTURE \| channel->fmt_val \|
1940	3624	channel->cmd_mode_en << 4 \| CSI_ENABLE_CROP \|
..	..	@@ -1946,7 +3630,7 @@
1946	3630
1947	3631	if (stream->cifdev->chip_id >= CHIP_RK3568_CIF)
1948	3632	val \|= stream->cif_fmt_in->csi_yuv_order;
1949		- } else if (mbus_type == V4L2_MBUS_CCP2) {
	3633	+ } else if (mbus_type == V4L2_MBUS_CCP2) {
1950	3634	rkcif_csi_set_lvds_sav_eav(stream, channel);
1951	3635	val = LVDS_ENABLE_CAPTURE \| LVDS_MODE(channel->lvds_cfg.mode) \|
1952	3636	LVDS_MAIN_LANE(0) \| LVDS_FID(0) \|
..	..	@@ -1958,15 +3642,403 @@
1958	3642	val &= ~LVDS_COMPACT;
1959	3643	}
1960	3644	if (stream->is_high_align)
1961		- val \|= CSI_ENABLE_MIPI_HIGH_ALIGN;
	3645	+ val \|= CSI_HIGH_ALIGN;
1962	3646	else
1963		- val &= ~CSI_ENABLE_MIPI_HIGH_ALIGN;
	3647	+ val &= ~CSI_HIGH_ALIGN;
1964	3648	rkcif_write_register(dev, get_reg_index_of_id_ctrl0(channel->id), val);
1965	3649
1966	3650	return 0;
1967	3651	}
1968	3652
1969		-static int rkcif_csi_stream_start(struct rkcif_stream *stream)
	3653	+static int rkcif_dvp_get_input_yuv_order(struct rkcif_stream *stream)
	3654	+{
	3655	+ unsigned int mask;
	3656	+ const struct cif_input_fmt *fmt = stream->cif_fmt_in;
	3657	+
	3658	+ switch (fmt->mbus_code) {
	3659	+ case MEDIA_BUS_FMT_UYVY8_2X8:
	3660	+ mask = CSI_YUV_INPUT_ORDER_UYVY >> 11;
	3661	+ break;
	3662	+ case MEDIA_BUS_FMT_VYUY8_2X8:
	3663	+ mask = CSI_YUV_INPUT_ORDER_VYUY >> 11;
	3664	+ break;
	3665	+ case MEDIA_BUS_FMT_YUYV8_2X8:
	3666	+ mask = CSI_YUV_INPUT_ORDER_YUYV >> 11;
	3667	+ break;
	3668	+ case MEDIA_BUS_FMT_YVYU8_2X8:
	3669	+ mask = CSI_YUV_INPUT_ORDER_YVYU >> 11;
	3670	+ break;
	3671	+ default:
	3672	+ mask = CSI_YUV_INPUT_ORDER_UYVY >> 11;
	3673	+ break;
	3674	+ }
	3675	+ return mask;
	3676	+}
	3677	+
	3678	+static int rkcif_csi_get_output_type_mask(struct rkcif_stream *stream)
	3679	+{
	3680	+ unsigned int mask;
	3681	+ const struct cif_output_fmt *fmt = stream->cif_fmt_out;
	3682	+
	3683	+ switch (fmt->fourcc) {
	3684	+ case V4L2_PIX_FMT_NV16:
	3685	+ mask = CSI_WRDDR_TYPE_YUV422SP_RK3588 \| CSI_YUV_OUTPUT_ORDER_UYVY;
	3686	+ break;
	3687	+ case V4L2_PIX_FMT_NV61:
	3688	+ mask = CSI_WRDDR_TYPE_YUV422SP_RK3588 \| CSI_YUV_OUTPUT_ORDER_VYUY;
	3689	+ break;
	3690	+ case V4L2_PIX_FMT_NV12:
	3691	+ mask = CSI_WRDDR_TYPE_YUV420SP_RK3588 \| CSI_YUV_OUTPUT_ORDER_UYVY;
	3692	+ break;
	3693	+ case V4L2_PIX_FMT_NV21:
	3694	+ mask = CSI_WRDDR_TYPE_YUV420SP_RK3588 \| CSI_YUV_OUTPUT_ORDER_VYUY;
	3695	+ break;
	3696	+ case V4L2_PIX_FMT_YUYV:
	3697	+ mask = CSI_WRDDR_TYPE_YUV_PACKET \| CSI_YUV_OUTPUT_ORDER_YUYV;
	3698	+ break;
	3699	+ case V4L2_PIX_FMT_YVYU:
	3700	+ mask = CSI_WRDDR_TYPE_YUV_PACKET \| CSI_YUV_OUTPUT_ORDER_YVYU;
	3701	+ break;
	3702	+ case V4L2_PIX_FMT_UYVY:
	3703	+ mask = CSI_WRDDR_TYPE_YUV_PACKET \| CSI_YUV_OUTPUT_ORDER_UYVY;
	3704	+ break;
	3705	+ case V4L2_PIX_FMT_VYUY:
	3706	+ mask = CSI_WRDDR_TYPE_YUV_PACKET \| CSI_YUV_OUTPUT_ORDER_VYUY;
	3707	+ break;
	3708	+ case V4L2_PIX_FMT_RGB24:
	3709	+ case V4L2_PIX_FMT_BGR24:
	3710	+ case V4L2_PIX_FMT_RGB565:
	3711	+ case V4L2_PIX_FMT_BGR666:
	3712	+ mask = CSI_WRDDR_TYPE_RAW_COMPACT;
	3713	+ break;
	3714	+ case V4L2_PIX_FMT_SRGGB8:
	3715	+ case V4L2_PIX_FMT_SGRBG8:
	3716	+ case V4L2_PIX_FMT_SGBRG8:
	3717	+ case V4L2_PIX_FMT_SBGGR8:
	3718	+ case V4L2_PIX_FMT_SRGGB10:
	3719	+ case V4L2_PIX_FMT_SGRBG10:
	3720	+ case V4L2_PIX_FMT_SGBRG10:
	3721	+ case V4L2_PIX_FMT_SBGGR10:
	3722	+ case V4L2_PIX_FMT_SRGGB12:
	3723	+ case V4L2_PIX_FMT_SGRBG12:
	3724	+ case V4L2_PIX_FMT_SGBRG12:
	3725	+ case V4L2_PIX_FMT_SBGGR12:
	3726	+ case V4L2_PIX_FMT_GREY:
	3727	+ case V4L2_PIX_FMT_Y10:
	3728	+ case V4L2_PIX_FMT_Y12:
	3729	+ if (stream->is_compact)
	3730	+ mask = CSI_WRDDR_TYPE_RAW_COMPACT;
	3731	+ else
	3732	+ mask = CSI_WRDDR_TYPE_RAW_UNCOMPACT;
	3733	+ break;
	3734	+ case V4L2_PIX_FMT_SBGGR16:
	3735	+ case V4L2_PIX_FMT_SGBRG16:
	3736	+ case V4L2_PIX_FMT_SGRBG16:
	3737	+ case V4L2_PIX_FMT_SRGGB16:
	3738	+ case V4L2_PIX_FMT_Y16:
	3739	+ mask = CSI_WRDDR_TYPE_RAW_UNCOMPACT;
	3740	+ break;
	3741	+ default:
	3742	+ mask = CSI_WRDDR_TYPE_RAW_COMPACT;
	3743	+ break;
	3744	+ }
	3745	+ return mask;
	3746	+}
	3747	+
	3748	+static int rkcif_lvds_get_output_type_mask(struct rkcif_stream *stream)
	3749	+{
	3750	+ unsigned int mask;
	3751	+ const struct cif_output_fmt *fmt = stream->cif_fmt_out;
	3752	+ int wr_type_offset = 0;
	3753	+ int yuvout_offset = 0;
	3754	+
	3755	+ if (stream->cifdev->chip_id == CHIP_RV1106_CIF) {
	3756	+ wr_type_offset = 17;
	3757	+ yuvout_offset = 9;
	3758	+ }
	3759	+
	3760	+ switch (fmt->fourcc) {
	3761	+ case V4L2_PIX_FMT_NV16:
	3762	+ mask = (CSI_WRDDR_TYPE_YUV422SP_RK3588 << wr_type_offset) \|
	3763	+ (CSI_YUV_OUTPUT_ORDER_UYVY << yuvout_offset);
	3764	+ break;
	3765	+ case V4L2_PIX_FMT_NV61:
	3766	+ mask = (CSI_WRDDR_TYPE_YUV422SP_RK3588 << wr_type_offset) \|
	3767	+ (CSI_YUV_OUTPUT_ORDER_VYUY << yuvout_offset);
	3768	+ break;
	3769	+ case V4L2_PIX_FMT_NV12:
	3770	+ mask = (CSI_WRDDR_TYPE_YUV420SP_RK3588 << wr_type_offset) \|
	3771	+ (CSI_YUV_OUTPUT_ORDER_UYVY << yuvout_offset);
	3772	+ break;
	3773	+ case V4L2_PIX_FMT_NV21:
	3774	+ mask = (CSI_WRDDR_TYPE_YUV420SP_RK3588 << wr_type_offset) \|
	3775	+ (CSI_YUV_OUTPUT_ORDER_VYUY << yuvout_offset);
	3776	+ break;
	3777	+ case V4L2_PIX_FMT_YUYV:
	3778	+ mask = (CSI_WRDDR_TYPE_YUV_PACKET << wr_type_offset) \|
	3779	+ (CSI_YUV_OUTPUT_ORDER_YUYV << yuvout_offset);
	3780	+ break;
	3781	+ case V4L2_PIX_FMT_YVYU:
	3782	+ mask = (CSI_WRDDR_TYPE_YUV_PACKET << wr_type_offset) \|
	3783	+ (CSI_YUV_OUTPUT_ORDER_YVYU << yuvout_offset);
	3784	+ break;
	3785	+ case V4L2_PIX_FMT_UYVY:
	3786	+ mask = (CSI_WRDDR_TYPE_YUV_PACKET << wr_type_offset) \|
	3787	+ (CSI_YUV_OUTPUT_ORDER_UYVY << yuvout_offset);
	3788	+ break;
	3789	+ case V4L2_PIX_FMT_VYUY:
	3790	+ mask = (CSI_WRDDR_TYPE_YUV_PACKET << wr_type_offset) \|
	3791	+ (CSI_YUV_OUTPUT_ORDER_VYUY << yuvout_offset);
	3792	+ break;
	3793	+ case V4L2_PIX_FMT_RGB24:
	3794	+ case V4L2_PIX_FMT_BGR24:
	3795	+ case V4L2_PIX_FMT_RGB565:
	3796	+ case V4L2_PIX_FMT_BGR666:
	3797	+ mask = CSI_WRDDR_TYPE_RAW_COMPACT << wr_type_offset;
	3798	+ break;
	3799	+ case V4L2_PIX_FMT_SRGGB8:
	3800	+ case V4L2_PIX_FMT_SGRBG8:
	3801	+ case V4L2_PIX_FMT_SGBRG8:
	3802	+ case V4L2_PIX_FMT_SBGGR8:
	3803	+ case V4L2_PIX_FMT_SRGGB10:
	3804	+ case V4L2_PIX_FMT_SGRBG10:
	3805	+ case V4L2_PIX_FMT_SGBRG10:
	3806	+ case V4L2_PIX_FMT_SBGGR10:
	3807	+ case V4L2_PIX_FMT_SRGGB12:
	3808	+ case V4L2_PIX_FMT_SGRBG12:
	3809	+ case V4L2_PIX_FMT_SGBRG12:
	3810	+ case V4L2_PIX_FMT_SBGGR12:
	3811	+ case V4L2_PIX_FMT_GREY:
	3812	+ case V4L2_PIX_FMT_Y10:
	3813	+ case V4L2_PIX_FMT_Y12:
	3814	+ if (stream->is_compact)
	3815	+ mask = CSI_WRDDR_TYPE_RAW_COMPACT << wr_type_offset;
	3816	+ else
	3817	+ mask = CSI_WRDDR_TYPE_RAW_UNCOMPACT << wr_type_offset;
	3818	+ break;
	3819	+ case V4L2_PIX_FMT_SBGGR16:
	3820	+ case V4L2_PIX_FMT_SGBRG16:
	3821	+ case V4L2_PIX_FMT_SGRBG16:
	3822	+ case V4L2_PIX_FMT_SRGGB16:
	3823	+ case V4L2_PIX_FMT_Y16:
	3824	+ mask = CSI_WRDDR_TYPE_RAW_UNCOMPACT << wr_type_offset;
	3825	+ break;
	3826	+ default:
	3827	+ mask = CSI_WRDDR_TYPE_RAW_COMPACT << wr_type_offset;
	3828	+ break;
	3829	+ }
	3830	+ return mask;
	3831	+}
	3832	+
	3833	+static void rkcif_modify_frame_skip_config(struct rkcif_stream *stream)
	3834	+{
	3835	+ if (stream->skip_info.skip_to_en) {
	3836	+ rkcif_disable_skip_frame(stream);
	3837	+ rkcif_enable_skip_frame(stream,
	3838	+ stream->skip_info.cap_m,
	3839	+ stream->skip_info.skip_n);
	3840	+ stream->skip_info.skip_to_en = false;
	3841	+ } else if (stream->skip_info.skip_to_dis) {
	3842	+ rkcif_disable_skip_frame(stream);
	3843	+ }
	3844	+}
	3845	+
	3846	+/config reg for rk3588/
	3847	+static int rkcif_csi_channel_set_v1(struct rkcif_stream *stream,
	3848	+ struct csi_channel_info *channel,
	3849	+ enum v4l2_mbus_type mbus_type, unsigned int mode,
	3850	+ int index)
	3851	+{
	3852	+ unsigned int val = 0x0;
	3853	+ struct rkcif_device *dev = stream->cifdev;
	3854	+ struct rkcif_stream *detect_stream = &dev->stream[0];
	3855	+ struct sditf_priv *priv = dev->sditf[0];
	3856	+ struct rkmodule_capture_info *capture_info = &channel->capture_info;
	3857	+ unsigned int wait_line = 0x3fff;
	3858	+ unsigned int dma_en = 0;
	3859	+ int offset = 0;
	3860	+
	3861	+ if (channel->id >= 4)
	3862	+ return -EINVAL;
	3863	+
	3864	+ if (!channel->enable) {
	3865	+ rkcif_write_register(dev, get_reg_index_of_id_ctrl0(channel->id),
	3866	+ CSI_DISABLE_CAPTURE);
	3867	+ return 0;
	3868	+ }
	3869	+
	3870	+ rkcif_write_register_and(dev, CIF_REG_MIPI_LVDS_INTSTAT,
	3871	+ ~(CSI_START_INTSTAT(channel->id) \|
	3872	+ CSI_DMA_END_INTSTAT(channel->id) \|
	3873	+ CSI_LINE_INTSTAT_V1(channel->id)));
	3874	+
	3875	+ if (!(capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE &&
	3876	+ index < capture_info->multi_dev.dev_num - 1)) {
	3877	+
	3878	+ rkcif_write_register_or(dev, CIF_REG_MIPI_LVDS_INTEN,
	3879	+ CSI_START_INTEN(channel->id));
	3880	+
	3881	+ if (priv && priv->mode.rdbk_mode && detect_stream->is_line_wake_up) {
	3882	+ rkcif_write_register_or(dev, CIF_REG_MIPI_LVDS_INTEN,
	3883	+ CSI_LINE_INTEN_RK3588(channel->id));
	3884	+ wait_line = dev->wait_line;
	3885	+ }
	3886	+ rkcif_write_register(dev, CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID0_1,
	3887	+ wait_line << 16 \| wait_line);
	3888	+ rkcif_write_register(dev, CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID2_3,
	3889	+ wait_line << 16 \| wait_line);
	3890	+
	3891	+ rkcif_write_register_or(dev, CIF_REG_MIPI_LVDS_INTEN,
	3892	+ CSI_DMA_END_INTEN(channel->id));
	3893	+
	3894	+ rkcif_write_register_or(dev, CIF_REG_MIPI_LVDS_INTEN,
	3895	+ CSI_ALL_ERROR_INTEN_V1);
	3896	+ }
	3897	+ if (stream->cifdev->id_use_cnt == 0) {
	3898	+ val = CIF_MIPI_LVDS_SW_PRESS_VALUE_RK3588(0x3) \|
	3899	+ CIF_MIPI_LVDS_SW_PRESS_ENABLE \|
	3900	+ CIF_MIPI_LVDS_SW_HURRY_VALUE_RK3588(0x3) \|
	3901	+ CIF_MIPI_LVDS_SW_HURRY_ENABLE \|
	3902	+ CIF_MIPI_LVDS_SW_WATER_LINE_25 \|
	3903	+ CIF_MIPI_LVDS_SW_WATER_LINE_ENABLE;
	3904	+ if (mbus_type == V4L2_MBUS_CSI2_DPHY \|\|
	3905	+ mbus_type == V4L2_MBUS_CSI2_CPHY)
	3906	+ val &= ~CIF_MIPI_LVDS_SW_SEL_LVDS_RV1106;
	3907	+ else
	3908	+ val \|= CIF_MIPI_LVDS_SW_SEL_LVDS_RV1106;
	3909	+ rkcif_write_register(dev, CIF_REG_MIPI_LVDS_CTRL, val);
	3910	+ }
	3911	+#if IS_ENABLED(CONFIG_CPU_RV1106)
	3912	+ if (channel->id == 1)
	3913	+ rv1106_sdmmc_get_lock();
	3914	+#endif
	3915	+ if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE &&
	3916	+ priv && priv->mode.rdbk_mode == RKISP_VICAP_ONLINE &&
	3917	+ (dev->hdr.hdr_mode == NO_HDR \|\|
	3918	+ (dev->hdr.hdr_mode == HDR_X2 && stream->id == 1) \|\|
	3919	+ (dev->hdr.hdr_mode == HDR_X3 && stream->id == 2)))
	3920	+ offset = channel->capture_info.multi_dev.pixel_offset;
	3921	+
	3922	+ rkcif_write_register(dev, get_reg_index_of_id_ctrl1(channel->id),
	3923	+ (channel->width + offset) \| (channel->height << 16));
	3924	+
	3925	+#if IS_ENABLED(CONFIG_CPU_RV1106)
	3926	+ if (channel->id == 1)
	3927	+ rv1106_sdmmc_put_lock();
	3928	+#endif
	3929	+
	3930	+ if (channel->crop_en)
	3931	+ rkcif_write_register(dev, get_reg_index_of_id_crop_start(channel->id),
	3932	+ channel->crop_st_y << 16 \| channel->crop_st_x);
	3933	+
	3934	+ if (mode == RKCIF_STREAM_MODE_CAPTURE)
	3935	+ rkcif_assign_new_buffer_pingpong(stream,
	3936	+ RKCIF_YUV_ADDR_STATE_INIT,
	3937	+ channel->id);
	3938	+ else if (mode == RKCIF_STREAM_MODE_TOISP \|\|
	3939	+ mode == RKCIF_STREAM_MODE_TOISP_RDBK)
	3940	+ rkcif_assign_new_buffer_pingpong_toisp(stream,
	3941	+ RKCIF_YUV_ADDR_STATE_INIT,
	3942	+ channel->id);
	3943	+ else if (mode == RKCIF_STREAM_MODE_ROCKIT)
	3944	+ rkcif_assign_new_buffer_pingpong_rockit(stream,
	3945	+ RKCIF_YUV_ADDR_STATE_INIT,
	3946	+ channel->id);
	3947	+
	3948	+ if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE &&
	3949	+ index == (capture_info->multi_dev.dev_num - 1) &&
	3950	+ priv && priv->mode.rdbk_mode != RKISP_VICAP_ONLINE)
	3951	+ rkcif_write_register(dev, get_reg_index_of_id_crop_start(channel->id),
	3952	+ channel->crop_st_y << 16 \|
	3953	+ (channel->crop_st_x + capture_info->multi_dev.pixel_offset));
	3954	+
	3955	+ rkcif_write_register(dev, get_reg_index_of_frm0_y_vlw(channel->id),
	3956	+ channel->virtual_width);
	3957	+
	3958	+ if (stream->lack_buf_cnt == 2)
	3959	+ stream->dma_en = 0;
	3960	+
	3961	+ if (stream->dma_en) {
	3962	+ if (mbus_type == V4L2_MBUS_CSI2_DPHY \|\|
	3963	+ mbus_type == V4L2_MBUS_CSI2_CPHY)
	3964	+ dma_en = CSI_DMA_ENABLE;
	3965	+ else
	3966	+ dma_en = LVDS_DMAEN_RV1106;
	3967	+ }
	3968	+ if (mbus_type == V4L2_MBUS_CSI2_DPHY \|\|
	3969	+ mbus_type == V4L2_MBUS_CSI2_CPHY) {
	3970	+
	3971	+ if (stream->cifdev->hdr.esp.mode == HDR_LINE_CNT \|\|
	3972	+ stream->cifdev->hdr.esp.mode == HDR_ID_CODE)
	3973	+ channel->vc = 0;
	3974	+
	3975	+ val = CSI_ENABLE_CAPTURE \| dma_en \|
	3976	+ channel->cmd_mode_en << 26 \| CSI_ENABLE_CROP_V1 \|
	3977	+ channel->vc << 8 \| channel->data_type << 10 \|
	3978	+ channel->csi_fmt_val;
	3979	+
	3980	+ val \|= stream->cif_fmt_in->csi_yuv_order;
	3981	+ val \|= rkcif_csi_get_output_type_mask(stream);
	3982	+ if (stream->cifdev->hdr.hdr_mode == NO_HDR \|\|
	3983	+ stream->cifdev->hdr.hdr_mode == HDR_COMPR)
	3984	+ val \|= CSI_NO_HDR;
	3985	+ else if (stream->cifdev->hdr.hdr_mode == HDR_X2)
	3986	+ val \|= CSI_HDR2;
	3987	+ else if (stream->cifdev->hdr.hdr_mode == HDR_X3)
	3988	+ val \|= CSI_HDR3;
	3989	+ if (stream->cifdev->hdr.esp.mode == HDR_NORMAL_VC)
	3990	+ val \|= CSI_HDR_MODE_VC;
	3991	+ else if (stream->cifdev->hdr.esp.mode == HDR_LINE_CNT)
	3992	+ val \|= CSI_HDR_MODE_LINE_CNT;
	3993	+ else if (stream->cifdev->hdr.esp.mode == HDR_ID_CODE)
	3994	+ val \|= CSI_HDR_MODE_LINE_INFO;
	3995	+ if (stream->cifdev->hdr.hdr_mode != NO_HDR &&
	3996	+ stream->cifdev->hdr.esp.mode == HDR_NORMAL_VC)
	3997	+ val \|= CSI_HDR_VC_MODE_PROTECT;
	3998	+ if (stream->is_high_align)
	3999	+ val \|= CSI_HIGH_ALIGN_RK3588;
	4000	+ else
	4001	+ val &= ~CSI_HIGH_ALIGN_RK3588;
	4002	+ rkcif_write_register(dev, get_reg_index_of_id_ctrl0(channel->id), val);
	4003	+ rkcif_write_register(dev, CIF_REG_MIPI_EFFECT_CODE_ID0, 0x02410251);
	4004	+ rkcif_write_register(dev, CIF_REG_MIPI_EFFECT_CODE_ID1, 0x02420252);
	4005	+ } else if (mbus_type == V4L2_MBUS_CCP2) {
	4006	+ rkcif_csi_set_lvds_sav_eav(stream, channel);
	4007	+ val = LVDS_ENABLE_CAPTURE_RV1106 \| LVDS_MODE_RV1106(channel->lvds_cfg.mode) \|
	4008	+ LVDS_MAIN_LANE_RV1106(0) \| LVDS_FID_RV1106(0) \|
	4009	+ LVDS_LANES_ENABLED_RV1106(dev->active_sensor->lanes) \|
	4010	+ (channel->csi_fmt_val << 18) \|
	4011	+ rkcif_lvds_get_output_type_mask(stream) \|
	4012	+ (stream->cif_fmt_in->csi_yuv_order << 9) \|
	4013	+ dma_en;
	4014	+ if (stream->cifdev->hdr.hdr_mode == HDR_X3)
	4015	+ val \|= BIT(12);
	4016	+ rkcif_write_register(dev, get_reg_index_of_lvds_id_ctrl0(channel->id), val);
	4017	+ }
	4018	+ if (dev->chip_id >= CHIP_RV1106_CIF)
	4019	+ rkcif_modify_frame_skip_config(stream);
	4020	+ if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	4021	+ if (index == (capture_info->multi_dev.dev_num - 1))
	4022	+ stream->cifdev->id_use_cnt++;
	4023	+ } else {
	4024	+ stream->cifdev->id_use_cnt++;
	4025	+ }
	4026	+ if (!(capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE &&
	4027	+ index < capture_info->multi_dev.dev_num - 1)) {
	4028	+ if (mode == RKCIF_STREAM_MODE_CAPTURE)
	4029	+ rkcif_assign_new_buffer_pingpong(stream,
	4030	+ RKCIF_YUV_ADDR_STATE_INIT,
	4031	+ channel->id);
	4032	+ else if (mode == RKCIF_STREAM_MODE_TOISP \|\|
	4033	+ mode == RKCIF_STREAM_MODE_TOISP_RDBK)
	4034	+ rkcif_assign_new_buffer_pingpong_toisp(stream,
	4035	+ RKCIF_YUV_ADDR_STATE_INIT,
	4036	+ channel->id);
	4037	+ }
	4038	+ return 0;
	4039	+}
	4040	+
	4041	+static int rkcif_csi_stream_start(struct rkcif_stream *stream, unsigned int mode)
1970	4042	{
1971	4043	struct rkcif_device *dev = stream->cifdev;
1972	4044	struct rkcif_sensor_info *active_sensor = dev->active_sensor;
..	..	@@ -1974,23 +4046,22 @@
1974	4046	enum v4l2_mbus_type mbus_type = active_sensor->mbus.type;
1975	4047	struct csi_channel_info *channel;
1976	4048	u32 ret = 0;
	4049	+ int i;
1977	4050
1978		- if (stream->state != RKCIF_STATE_RESET_IN_STREAMING)
	4051	+ if (stream->state < RKCIF_STATE_STREAMING) {
1979	4052	stream->frame_idx = 0;
	4053	+ stream->buf_wake_up_cnt = 0;
	4054	+ stream->frame_phase = 0;
	4055	+ stream->lack_buf_cnt = 0;
	4056	+ stream->is_in_vblank = false;
	4057	+ stream->is_change_toisp = false;
	4058	+ }
1980	4059
1981		- if (mbus_type == V4L2_MBUS_CSI2) {
1982		- rkcif_csi_get_vc_num(dev, flags);
	4060	+ rkcif_csi_get_vc_num(dev, flags);
1983	4061
1984		- channel = &dev->channels[stream->id];
1985		- channel->id = stream->id;
1986		- rkcif_csi_channel_init(stream, channel);
1987		- rkcif_csi_channel_set(stream, channel, V4L2_MBUS_CSI2);
1988		- } else if (mbus_type == V4L2_MBUS_CCP2) {
1989		- rkcif_csi_get_vc_num(dev, flags);
1990		-
1991		- channel = &dev->channels[stream->id];
1992		- channel->id = stream->id;
1993		-
	4062	+ channel = &dev->channels[stream->id];
	4063	+ channel->id = stream->id;
	4064	+ if (mbus_type == V4L2_MBUS_CCP2) {
1994	4065	ret = v4l2_subdev_call(dev->terminal_sensor.sd, core,
1995	4066	ioctl, RKMODULE_GET_LVDS_CFG,
1996	4067	&channel->lvds_cfg);
..	..	@@ -1998,18 +4069,63 @@
1998	4069	v4l2_err(&dev->v4l2_dev, "Err: get lvds config failed!!\n");
1999	4070	return ret;
2000	4071	}
2001		-
2002		- rkcif_csi_channel_init(stream, channel);
2003		- rkcif_csi_channel_set(stream, channel, V4L2_MBUS_CCP2);
2004	4072	}
2005		-
2006		- stream->line_int_cnt = 0;
2007		- if (stream->is_line_wake_up)
2008		- stream->is_can_stop = false;
2009		- else
2010		- stream->is_can_stop = true;
2011		- stream->state = RKCIF_STATE_STREAMING;
2012		- dev->workmode = RKCIF_WORKMODE_PINGPONG;
	4073	+ rkcif_csi_channel_init(stream, channel);
	4074	+ if (stream->state != RKCIF_STATE_STREAMING) {
	4075	+ if (mode == RKCIF_STREAM_MODE_CAPTURE) {
	4076	+ stream->dma_en \|= RKCIF_DMAEN_BY_VICAP;
	4077	+ } else if (mode == RKCIF_STREAM_MODE_TOISP_RDBK) {
	4078	+ stream->dma_en \|= RKCIF_DMAEN_BY_ISP;
	4079	+ } else if (mode == RKCIF_STREAM_MODE_TOISP) {
	4080	+ if (dev->hdr.hdr_mode == HDR_X2 &&
	4081	+ stream->id == 0)
	4082	+ stream->dma_en \|= RKCIF_DMAEN_BY_ISP;
	4083	+ else if (dev->hdr.hdr_mode == HDR_X3 && (stream->id == 0 \|\| stream->id == 1))
	4084	+ stream->dma_en \|= RKCIF_DMAEN_BY_ISP;
	4085	+ } else if (mode == RKCIF_STREAM_MODE_ROCKIT) {
	4086	+ stream->dma_en \|= RKCIF_DMAEN_BY_ROCKIT;
	4087	+ }
	4088	+ if (stream->cifdev->chip_id < CHIP_RK3588_CIF) {
	4089	+ rkcif_csi_channel_set(stream, channel, mbus_type);
	4090	+ } else {
	4091	+ if (channel->capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	4092	+ for (i = 0; i < channel->capture_info.multi_dev.dev_num; i++) {
	4093	+ dev->csi_host_idx = channel->capture_info.multi_dev.dev_idx[i];
	4094	+ rkcif_csi_channel_set_v1(stream, channel, mbus_type, mode, i);
	4095	+ }
	4096	+ } else {
	4097	+ rkcif_csi_channel_set_v1(stream, channel, mbus_type, mode, 0);
	4098	+ }
	4099	+ }
	4100	+ } else {
	4101	+ if (stream->cifdev->chip_id >= CHIP_RK3588_CIF) {
	4102	+ if (mode == RKCIF_STREAM_MODE_CAPTURE) {
	4103	+ stream->to_en_dma = RKCIF_DMAEN_BY_VICAP;
	4104	+ } else if (mode == RKCIF_STREAM_MODE_TOISP_RDBK) {
	4105	+ stream->to_en_dma = RKCIF_DMAEN_BY_ISP;
	4106	+ } else if (mode == RKCIF_STREAM_MODE_TOISP) {
	4107	+ if (dev->hdr.hdr_mode == HDR_X2 &&
	4108	+ stream->id == 0 &&
	4109	+ (!stream->dma_en))
	4110	+ stream->to_en_dma = RKCIF_DMAEN_BY_ISP;
	4111	+ else if (dev->hdr.hdr_mode == HDR_X3 &&
	4112	+ (stream->id == 0 \|\| stream->id == 1) &&
	4113	+ (!stream->dma_en))
	4114	+ stream->to_en_dma = RKCIF_DMAEN_BY_ISP;
	4115	+ } else if (mode == RKCIF_STREAM_MODE_ROCKIT) {
	4116	+ stream->to_en_dma = RKCIF_DMAEN_BY_ROCKIT;
	4117	+ }
	4118	+ }
	4119	+ }
	4120	+ if (stream->state != RKCIF_STATE_STREAMING) {
	4121	+ stream->line_int_cnt = 0;
	4122	+ if (stream->is_line_wake_up)
	4123	+ stream->is_can_stop = false;
	4124	+ else
	4125	+ stream->is_can_stop = true;
	4126	+ stream->state = RKCIF_STATE_STREAMING;
	4127	+ dev->workmode = RKCIF_WORKMODE_PINGPONG;
	4128	+ }
2013	4129
2014	4130	return 0;
2015	4131	}
..	..	@@ -2020,17 +4136,28 @@
2020	4136	struct v4l2_mbus_config *mbus_cfg = &cif_dev->active_sensor->mbus;
2021	4137	u32 val;
2022	4138	int id;
	4139	+ int i = 0;
2023	4140
2024		- if (mbus_cfg->type == V4L2_MBUS_CSI2 \|\|
	4141	+ stream->cifdev->id_use_cnt--;
	4142	+ if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
	4143	+ mbus_cfg->type == V4L2_MBUS_CSI2_CPHY \|\|
2025	4144	mbus_cfg->type == V4L2_MBUS_CCP2) {
2026	4145	id = stream->id;
2027	4146	val = rkcif_read_register(cif_dev, get_reg_index_of_id_ctrl0(id));
2028		- if (mbus_cfg->type == V4L2_MBUS_CSI2)
2029		- val &= ~CSI_ENABLE_CAPTURE;
	4147	+ if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
	4148	+ mbus_cfg->type == V4L2_MBUS_CSI2_CPHY)
	4149	+ val &= ~(CSI_ENABLE_CAPTURE \| CSI_DMA_ENABLE);
2030	4150	else
2031	4151	val &= ~LVDS_ENABLE_CAPTURE;
2032	4152
2033		- rkcif_write_register(cif_dev, get_reg_index_of_id_ctrl0(id), val);
	4153	+ if (cif_dev->channels[id].capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	4154	+ for (i = 0; i < cif_dev->channels[id].capture_info.multi_dev.dev_num; i++) {
	4155	+ cif_dev->csi_host_idx = cif_dev->channels[id].capture_info.multi_dev.dev_idx[i];
	4156	+ rkcif_write_register(cif_dev, get_reg_index_of_id_ctrl0(id), val);
	4157	+ }
	4158	+ } else {
	4159	+ rkcif_write_register(cif_dev, get_reg_index_of_id_ctrl0(id), val);
	4160	+ }
2034	4161
2035	4162	rkcif_write_register_or(cif_dev, CIF_REG_MIPI_LVDS_INTSTAT,
2036	4163	CSI_START_INTSTAT(id) \|
..	..	@@ -2042,8 +4169,25 @@
2042	4169	CSI_DMA_END_INTEN(id) \|
2043	4170	CSI_LINE_INTEN(id)));
2044	4171
2045		- rkcif_write_register_and(cif_dev, CIF_REG_MIPI_LVDS_INTEN,
2046		- ~CSI_ALL_ERROR_INTEN);
	4172	+ if (stream->cifdev->chip_id < CHIP_RK3588_CIF) {
	4173	+ rkcif_write_register_and(cif_dev, CIF_REG_MIPI_LVDS_INTEN,
	4174	+ ~CSI_ALL_ERROR_INTEN);
	4175	+ } else {
	4176	+ if (stream->cifdev->id_use_cnt == 0) {
	4177	+ rkcif_write_register_and(cif_dev, CIF_REG_MIPI_LVDS_INTEN,
	4178	+ ~CSI_ALL_ERROR_INTEN_V1);
	4179	+ if (cif_dev->channels[id].capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	4180	+ for (i = 0; i < cif_dev->channels[id].capture_info.multi_dev.dev_num; i++) {
	4181	+ cif_dev->csi_host_idx = cif_dev->channels[id].capture_info.multi_dev.dev_idx[i];
	4182	+ rkcif_write_register_and(cif_dev, CIF_REG_MIPI_LVDS_CTRL,
	4183	+ ~CSI_ENABLE_CAPTURE);
	4184	+ }
	4185	+ } else {
	4186	+ rkcif_write_register_and(cif_dev, CIF_REG_MIPI_LVDS_CTRL,
	4187	+ ~CSI_ENABLE_CAPTURE);
	4188	+ }
	4189	+ }
	4190	+ }
2047	4191
2048	4192	} else {
2049	4193	if (atomic_read(&cif_dev->pipe.stream_cnt) == 1) {
..	..	@@ -2053,16 +4197,17 @@
2053	4197	rkcif_write_register(cif_dev, CIF_REG_DVP_INTEN, 0x0);
2054	4198	rkcif_write_register(cif_dev, CIF_REG_DVP_INTSTAT, 0x3ff);
2055	4199	rkcif_write_register(cif_dev, CIF_REG_DVP_FRAME_STATUS, 0x0);
	4200	+ if (IS_ENABLED(CONFIG_CPU_RV1106))
	4201	+ rkcif_config_dvp_pin(cif_dev, false);
2056	4202	}
2057		- stream->is_dvp_yuv_addr_init = false;
2058	4203	}
2059		-
2060	4204	stream->state = RKCIF_STATE_READY;
	4205	+ stream->dma_en = 0;
2061	4206	}
2062	4207
2063	4208	static bool rkcif_is_extending_line_for_height(struct rkcif_device *dev,
2064		- struct rkcif_stream *stream,
2065		- const struct cif_input_fmt *fmt)
	4209	+ struct rkcif_stream *stream,
	4210	+ const struct cif_input_fmt *fmt)
2066	4211	{
2067	4212	bool is_extended = false;
2068	4213	struct rkmodule_hdr_cfg hdr_cfg;
..	..	@@ -2076,17 +4221,17 @@
2076	4221	RKMODULE_GET_HDR_CFG,
2077	4222	&hdr_cfg);
2078	4223	if (!ret)
2079		- dev->hdr.mode = hdr_cfg.hdr_mode;
	4224	+ dev->hdr = hdr_cfg;
2080	4225	else
2081		- dev->hdr.mode = NO_HDR;
	4226	+ dev->hdr.hdr_mode = NO_HDR;
2082	4227	}
2083	4228
2084	4229	if (fmt && fmt->fmt_type == CIF_FMT_TYPE_RAW) {
2085		- if ((dev->hdr.mode == HDR_X2 &&
	4230	+ if ((dev->hdr.hdr_mode == HDR_X2 &&
2086	4231	stream->id == RKCIF_STREAM_MIPI_ID1) \|\|
2087		- (dev->hdr.mode == HDR_X3 &&
	4232	+ (dev->hdr.hdr_mode == HDR_X3 &&
2088	4233	stream->id == RKCIF_STREAM_MIPI_ID2) \|\|
2089		- (dev->hdr.mode == NO_HDR)) {
	4234	+ (dev->hdr.hdr_mode == NO_HDR)) {
2090	4235	is_extended = true;
2091	4236	}
2092	4237	}
..	..	@@ -2134,7 +4279,7 @@
2134	4279	plane_fmt = &pixm->plane_fmt[i];
2135	4280	sizes[i] = plane_fmt->sizeimage / height * h;
2136	4281	}
2137		-
	4282	+ stream->total_buf_num = *num_buffers;
2138	4283	v4l2_dbg(1, rkcif_debug, &dev->v4l2_dev, "%s count %d, size %d, extended(%d, %d)\n",
2139	4284	v4l2_type_names[queue->type], *num_buffers, sizes[0],
2140	4285	is_extended, extend_line->is_extended);
..	..	@@ -2143,91 +4288,192 @@
2143	4288	}
2144	4289
2145	4290	static void rkcif_check_buffer_update_pingpong(struct rkcif_stream *stream,
2146		- int channel_id)
	4291	+ int channel_id)
2147	4292	{
2148	4293	struct rkcif_device *dev = stream->cifdev;
2149	4294	struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
2150	4295	struct rkcif_buffer *buffer = NULL;
2151		- struct rkcif_dummy_buffer *dummy_buf = &dev->dummy_buf;
2152		- u32 frm_addr_y, frm_addr_uv;
	4296	+ struct rkcif_dummy_buffer *dummy_buf = &dev->hw_dev->dummy_buf;
	4297	+ u32 frm_addr_y = 0, frm_addr_uv = 0;
	4298	+ u32 frm0_addr_y = 0, frm0_addr_uv = 0;
	4299	+ u32 frm1_addr_y = 0, frm1_addr_uv = 0;
	4300	+ u32 buff_addr_y = 0, buff_addr_cbcr = 0;
	4301	+ struct rkmodule_capture_info *capture_info = &dev->channels[channel_id].capture_info;
2153	4302	unsigned long flags;
	4303	+ int frame_phase = 0;
	4304	+ bool is_dual_update_buf = false;
2154	4305
	4306	+ spin_lock_irqsave(&stream->vbq_lock, flags);
2155	4307	if (stream->state == RKCIF_STATE_STREAMING &&
2156		- stream->curr_buf == stream->next_buf &&
2157		- stream->cif_fmt_in->field != V4L2_FIELD_INTERLACED &&
2158		- (!dummy_buf->vaddr)) {
2159		- if (!stream->is_line_wake_up) {
2160		- if (mbus_cfg->type == V4L2_MBUS_CSI2 \|\|
	4308	+ ((stream->curr_buf == stream->next_buf &&
	4309	+ stream->cif_fmt_in->field != V4L2_FIELD_INTERLACED &&
	4310	+ (!dummy_buf->vaddr)) \|\|
	4311	+ stream->curr_buf == NULL \|\|
	4312	+ stream->next_buf == NULL)) {
	4313	+ frame_phase = stream->frame_phase_cache;
	4314	+ if (!stream->is_line_wake_up \|\|
	4315	+ (stream->is_line_wake_up && stream->frame_idx < 2)) {
	4316	+ if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
	4317	+ mbus_cfg->type == V4L2_MBUS_CSI2_CPHY \|\|
2161	4318	mbus_cfg->type == V4L2_MBUS_CCP2) {
2162		- frm_addr_y = stream->frame_phase_cache & CIF_CSI_FRAME0_READY ?
2163		- get_reg_index_of_frm0_y_addr(channel_id) :
2164		- get_reg_index_of_frm1_y_addr(channel_id);
2165		- frm_addr_uv = stream->frame_phase_cache & CIF_CSI_FRAME0_READY ?
2166		- get_reg_index_of_frm0_uv_addr(channel_id) :
2167		- get_reg_index_of_frm1_uv_addr(channel_id);
	4319	+ frm0_addr_y = get_reg_index_of_frm0_y_addr(channel_id);
	4320	+ frm1_addr_y = get_reg_index_of_frm1_y_addr(channel_id);
	4321	+ frm0_addr_uv = get_reg_index_of_frm0_uv_addr(channel_id);
	4322	+ frm1_addr_uv = get_reg_index_of_frm1_uv_addr(channel_id);
2168	4323	} else {
2169		- frm_addr_y = stream->frame_phase_cache & CIF_CSI_FRAME0_READY ?
2170		- get_dvp_reg_index_of_frm0_y_addr(channel_id) :
2171		- get_dvp_reg_index_of_frm1_y_addr(channel_id);
2172		- frm_addr_uv = stream->frame_phase_cache & CIF_CSI_FRAME0_READY ?
2173		- get_dvp_reg_index_of_frm0_uv_addr(channel_id) :
2174		- get_dvp_reg_index_of_frm1_uv_addr(channel_id);
	4324	+ frm0_addr_y = get_dvp_reg_index_of_frm0_y_addr(channel_id);
	4325	+ frm1_addr_y = get_dvp_reg_index_of_frm1_y_addr(channel_id);
	4326	+ frm0_addr_uv = get_dvp_reg_index_of_frm0_uv_addr(channel_id);
	4327	+ frm1_addr_uv = get_dvp_reg_index_of_frm1_uv_addr(channel_id);
2175	4328	}
2176		- v4l2_dbg(1, rkcif_debug, &stream->cifdev->v4l2_dev,
2177		- "stream[%d] update buf in %s, stream->frame_phase_cache %d\n",
2178		- stream->id, __func__, stream->frame_phase_cache);
2179		- spin_lock_irqsave(&stream->vbq_lock, flags);
	4329	+ if (frame_phase & CIF_CSI_FRAME0_READY) {
	4330	+ frm_addr_y = frm0_addr_y;
	4331	+ frm_addr_uv = frm0_addr_uv;
	4332	+ } else {
	4333	+ frm_addr_y = frm1_addr_y;
	4334	+ frm_addr_uv = frm1_addr_uv;
	4335	+ }
	4336	+ if (!stream->dma_en && stream->curr_buf == NULL && stream->next_buf == NULL)
	4337	+ is_dual_update_buf = true;
2180	4338	if (!list_empty(&stream->buf_head)) {
2181		- if (stream->frame_phase_cache == CIF_CSI_FRAME0_READY) {
	4339	+ if (frame_phase == CIF_CSI_FRAME0_READY) {
2182	4340	stream->curr_buf = list_first_entry(&stream->buf_head,
2183	4341	struct rkcif_buffer, queue);
2184	4342	if (stream->curr_buf) {
2185	4343	list_del(&stream->curr_buf->queue);
2186	4344	buffer = stream->curr_buf;
2187	4345	}
2188		- } else if (stream->frame_phase_cache == CIF_CSI_FRAME1_READY) {
2189		- stream->next_buf = list_first_entry(&stream->buf_head,
	4346	+ if (buffer && is_dual_update_buf)
	4347	+ stream->next_buf = buffer;
	4348	+ } else if (frame_phase == CIF_CSI_FRAME1_READY) {
	4349	+ if (stream->next_buf == NULL &&
	4350	+ stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED) {
	4351	+ stream->next_buf = stream->curr_buf;
	4352	+ } else {
	4353	+ stream->next_buf = list_first_entry(&stream->buf_head,
2190	4354	struct rkcif_buffer, queue);
2191		- if (stream->next_buf) {
2192		- list_del(&stream->next_buf->queue);
2193		- buffer = stream->next_buf;
	4355	+ if (stream->next_buf) {
	4356	+ list_del(&stream->next_buf->queue);
	4357	+ buffer = stream->next_buf;
	4358	+ }
	4359	+ if (buffer && is_dual_update_buf)
	4360	+ stream->curr_buf = buffer;
	4361	+ }
	4362	+ }
	4363	+ } else {
	4364	+ v4l2_info(&dev->v4l2_dev, "%s %d\n", __func__, __LINE__);
	4365	+ }
	4366	+ if (buffer) {
	4367	+ if (is_dual_update_buf) {
	4368	+ buff_addr_y = buffer->buff_addr[RKCIF_PLANE_Y];
	4369	+ buff_addr_cbcr = buffer->buff_addr[RKCIF_PLANE_CBCR];
	4370	+ if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	4371	+ rkcif_write_buff_addr_multi_dev_combine(stream,
	4372	+ frm0_addr_y,
	4373	+ frm0_addr_uv,
	4374	+ buff_addr_y,
	4375	+ buff_addr_cbcr,
	4376	+ false);
	4377	+ rkcif_write_buff_addr_multi_dev_combine(stream,
	4378	+ frm1_addr_y,
	4379	+ frm1_addr_uv,
	4380	+ buff_addr_y,
	4381	+ buff_addr_cbcr,
	4382	+ false);
	4383	+ } else {
	4384	+ rkcif_write_register(dev, frm0_addr_y, buff_addr_y);
	4385	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	4386	+ rkcif_write_register(dev,
	4387	+ frm0_addr_uv,
	4388	+ buff_addr_cbcr);
	4389	+ rkcif_write_register(dev, frm1_addr_y, buff_addr_y);
	4390	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	4391	+ rkcif_write_register(dev,
	4392	+ frm1_addr_uv,
	4393	+ buff_addr_cbcr);
	4394	+ }
	4395	+ } else {
	4396	+
	4397	+ buff_addr_y = buffer->buff_addr[RKCIF_PLANE_Y];
	4398	+ buff_addr_cbcr = buffer->buff_addr[RKCIF_PLANE_CBCR];
	4399	+ if (capture_info->mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	4400	+ rkcif_write_buff_addr_multi_dev_combine(stream,
	4401	+ frm_addr_y,
	4402	+ frm_addr_uv,
	4403	+ buff_addr_y,
	4404	+ buff_addr_cbcr,
	4405	+ false);
	4406	+ } else {
	4407	+ rkcif_write_register(dev, frm_addr_y, buff_addr_y);
	4408	+ if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
	4409	+ rkcif_write_register(dev,
	4410	+ frm_addr_uv,
	4411	+ buff_addr_cbcr);
2194	4412	}
2195	4413	}
2196	4414	}
2197		- spin_unlock_irqrestore(&stream->vbq_lock, flags);
2198		- if (buffer) {
2199		- rkcif_write_register(dev, frm_addr_y,
2200		- buffer->buff_addr[RKCIF_PLANE_Y]);
2201		- if (stream->cif_fmt_out->fmt_type != CIF_FMT_TYPE_RAW)
2202		- rkcif_write_register(dev, frm_addr_uv,
2203		- buffer->buff_addr[RKCIF_PLANE_CBCR]);
2204		- }
2205	4415	} else {
2206		- spin_lock_irqsave(&stream->vbq_lock, flags);
	4416	+ v4l2_dbg(3, rkcif_debug, &stream->cifdev->v4l2_dev,
	4417	+ "%s %d, is_wake_up %d, frame_idx %d\n",
	4418	+ __func__, __LINE__, stream->is_line_wake_up, stream->frame_idx);
2207	4419	if (stream->curr_buf == stream->next_buf) {
2208	4420	if (stream->frame_phase_cache == CIF_CSI_FRAME0_READY) {
2209	4421	stream->curr_buf = list_first_entry(&stream->buf_head,
2210	4422	struct rkcif_buffer, queue);
	4423	+ v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev,
	4424	+ "%s %d, stream[%d] buf idx %d\n",
	4425	+ __func__, __LINE__, stream->id, stream->curr_buf->vb.vb2_buf.index);
2211	4426	if (stream->curr_buf)
2212	4427	list_del(&stream->curr_buf->queue);
2213	4428	} else if (stream->frame_phase_cache == CIF_CSI_FRAME1_READY) {
2214	4429	stream->next_buf = list_first_entry(&stream->buf_head,
2215	4430	struct rkcif_buffer, queue);
	4431	+ v4l2_dbg(4, rkcif_debug, &dev->v4l2_dev,
	4432	+ "%s %d, stream[%d] buf idx %d\n",
	4433	+ __func__, __LINE__, stream->id, stream->next_buf->vb.vb2_buf.index);
2216	4434	if (stream->next_buf)
2217	4435	list_del(&stream->next_buf->queue);
2218	4436	}
2219	4437	stream->is_buf_active = true;
2220	4438	}
2221		- spin_unlock_irqrestore(&stream->vbq_lock, flags);
2222	4439	}
	4440	+ v4l2_dbg(3, rkcif_debug, &stream->cifdev->v4l2_dev,
	4441	+ "%s, stream[%d] update buffer, frame_phase %d, is_stop %s, lack_buf_cnt %d\n",
	4442	+ __func__, stream->id, frame_phase,
	4443	+ (stream->dma_en ? "false" : "true"),
	4444	+ stream->lack_buf_cnt);
	4445	+ if (!stream->dma_en) {
	4446	+ if (stream->to_stop_dma) {
	4447	+ stream->to_stop_dma = 0;
	4448	+ wake_up(&stream->wq_stopped);
	4449	+ } else {
	4450	+ stream->to_en_dma = RKCIF_DMAEN_BY_VICAP;
	4451	+ v4l2_dbg(3, rkcif_debug, &stream->cifdev->v4l2_dev,
	4452	+ "%s stream[%d] start dma capture, frame cnt %d\n",
	4453	+ __func__, stream->id, stream->frame_idx);
	4454	+ }
	4455	+ } else {
	4456	+ v4l2_dbg(3, rkcif_debug, &stream->cifdev->v4l2_dev,
	4457	+ "%s %d, dma_en 0x%x, frame cnt %d\n",
	4458	+ __func__, __LINE__, stream->dma_en, stream->frame_idx);
	4459	+ }
	4460	+ if (stream->lack_buf_cnt)
	4461	+ stream->lack_buf_cnt--;
	4462	+
	4463	+ } else {
	4464	+ v4l2_info(&dev->v4l2_dev, "%s %d, state %d, curr_buf %p, next_buf %p\n",
	4465	+ __func__, __LINE__, stream->state, stream->curr_buf, stream->next_buf);
2223	4466	}
	4467	+ spin_unlock_irqrestore(&stream->vbq_lock, flags);
	4468	+ if (stream->to_en_dma)
	4469	+ rkcif_enable_dma_capture(stream, true);
2224	4470	}
2225	4471
2226	4472	/*
2227	4473	* The vb2_buffer are stored in rkcif_buffer, in order to unify
2228	4474	* mplane buffer and none-mplane buffer.
2229	4475	*/
2230		-static void rkcif_buf_queue(struct vb2_buffer *vb)
	4476	+void rkcif_buf_queue(struct vb2_buffer *vb)
2231	4477	{
2232	4478	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
2233	4479	struct rkcif_buffer *cifbuf = to_rkcif_buffer(vbuf);
..	..	@@ -2236,8 +4482,32 @@
2236	4482	struct v4l2_pix_format_mplane *pixm = &stream->pixm;
2237	4483	const struct cif_output_fmt *fmt = stream->cif_fmt_out;
2238	4484	struct rkcif_hw *hw_dev = stream->cifdev->hw_dev;
	4485	+ struct rkcif_tools_buffer *tools_buf;
	4486	+ struct rkcif_tools_vdev *tools_vdev = stream->tools_vdev;
2239	4487	unsigned long flags;
2240	4488	int i;
	4489	+ bool is_find_tools_buf = false;
	4490	+
	4491	+ if (tools_vdev) {
	4492	+ spin_lock_irqsave(&stream->tools_vdev->vbq_lock, flags);
	4493	+ if (!list_empty(&tools_vdev->src_buf_head)) {
	4494	+ list_for_each_entry(tools_buf, &tools_vdev->src_buf_head, list) {
	4495	+ if (tools_buf->vb == vbuf) {
	4496	+ is_find_tools_buf = true;
	4497	+ break;
	4498	+ }
	4499	+ }
	4500	+ if (is_find_tools_buf) {
	4501	+ if (tools_buf->use_cnt)
	4502	+ tools_buf->use_cnt--;
	4503	+ if (tools_buf->use_cnt) {
	4504	+ spin_unlock_irqrestore(&stream->tools_vdev->vbq_lock, flags);
	4505	+ return;
	4506	+ }
	4507	+ }
	4508	+ }
	4509	+ spin_unlock_irqrestore(&stream->tools_vdev->vbq_lock, flags);
	4510	+ }
2241	4511
2242	4512	memset(cifbuf->buff_addr, 0, sizeof(cifbuf->buff_addr));
2243	4513	/* If mplanes > 1, every c-plane has its own m-plane,
..	..	@@ -2246,7 +4516,7 @@
2246	4516	for (i = 0; i < fmt->mplanes; i++) {
2247	4517	void *addr = vb2_plane_vaddr(vb, i);
2248	4518
2249		- if (hw_dev->iommu_en) {
	4519	+ if (hw_dev->is_dma_sg_ops) {
2250	4520	struct sg_table *sgt = vb2_dma_sg_plane_desc(vb, i);
2251	4521
2252	4522	cifbuf->buff_addr[i] = sg_dma_address(sgt->sgl);
..	..	@@ -2255,7 +4525,7 @@
2255	4525	}
2256	4526	if (rkcif_debug && addr && !hw_dev->iommu_en) {
2257	4527	memset(addr, 0, pixm->plane_fmt[i].sizeimage);
2258		- v4l2_dbg(1, rkcif_debug, &stream->cifdev->v4l2_dev,
	4528	+ v4l2_dbg(3, rkcif_debug, &stream->cifdev->v4l2_dev,
2259	4529	"Clear buffer, size: 0x%08x\n",
2260	4530	pixm->plane_fmt[i].sizeimage);
2261	4531	}
..	..	@@ -2269,40 +4539,240 @@
2269	4539	spin_lock_irqsave(&stream->vbq_lock, flags);
2270	4540	list_add_tail(&cifbuf->queue, &stream->buf_head);
2271	4541	spin_unlock_irqrestore(&stream->vbq_lock, flags);
2272		- if (stream->cifdev->workmode == RKCIF_WORKMODE_PINGPONG)
	4542	+ if (stream->dma_en & RKCIF_DMAEN_BY_ISP && (!cifbuf->dbuf)) {
	4543	+ struct rkisp_rx_buf *dbufs = NULL;
	4544	+
	4545	+ dbufs = kzalloc(sizeof(struct rkisp_rx_buf), GFP_KERNEL);
	4546	+
	4547	+ memset(dbufs, 0, sizeof(struct rkisp_rx_buf));
	4548	+ if (stream->cifdev->hdr.hdr_mode == HDR_X2 && stream->id == 0)
	4549	+ dbufs->type = BUF_MIDDLE;
	4550	+ else if (stream->cifdev->hdr.hdr_mode == HDR_X3 && stream->id == 0)
	4551	+ dbufs->type = BUF_LONG;
	4552	+ else if (stream->cifdev->hdr.hdr_mode == HDR_X3 && stream->id == 1)
	4553	+ dbufs->type = BUF_MIDDLE;
	4554	+ cifbuf->dbuf = hw_dev->mem_ops->get_dmabuf(vb->planes[0].mem_priv, O_RDWR);
	4555	+ if (cifbuf->dbuf)
	4556	+ dbufs->dbuf = cifbuf->dbuf;
	4557	+ list_add_tail(&dbufs->list, &stream->rx_buf_head_vicap);
	4558	+ }
	4559	+ if (stream->cifdev->workmode == RKCIF_WORKMODE_PINGPONG &&
	4560	+ stream->lack_buf_cnt)
2273	4561	rkcif_check_buffer_update_pingpong(stream, stream->id);
	4562	+ v4l2_dbg(3, rkcif_debug, &stream->cifdev->v4l2_dev,
	4563	+ "stream[%d] buf queue, index: %d, dma_addr 0x%x\n",
	4564	+ stream->id, vb->index, cifbuf->buff_addr[0]);
	4565	+ atomic_inc(&stream->buf_cnt);
	4566	+}
	4567	+
	4568	+void rkcif_free_rx_buf(struct rkcif_stream *stream, int buf_num)
	4569	+{
	4570	+ struct rkcif_rx_buffer *buf;
	4571	+ struct rkcif_device *dev = stream->cifdev;
	4572	+ struct sditf_priv *priv = dev->sditf[0];
	4573	+ int i = 0;
	4574	+ unsigned long flags;
	4575	+
	4576	+ if (!priv)
	4577	+ return;
	4578	+
	4579	+ spin_lock_irqsave(&stream->vbq_lock, flags);
	4580	+ stream->curr_buf_toisp = NULL;
	4581	+ stream->next_buf_toisp = NULL;
	4582	+ INIT_LIST_HEAD(&stream->rx_buf_head);
	4583	+ spin_unlock_irqrestore(&stream->vbq_lock, flags);
	4584	+
	4585	+ if (dev->is_thunderboot)
	4586	+ spin_lock_irqsave(&dev->buffree_lock, flags);
	4587	+ for (i = 0; i < buf_num; i++) {
	4588	+ buf = &stream->rx_buf[i];
	4589	+ if (buf->dummy.is_free)
	4590	+ continue;
	4591	+ if (!dev->is_thunderboot)
	4592	+ rkcif_free_buffer(dev, &buf->dummy);
	4593	+ else
	4594	+ list_add_tail(&buf->list_free, &priv->buf_free_list);
	4595	+ atomic_dec(&stream->buf_cnt);
	4596	+ stream->total_buf_num--;
	4597	+ }
	4598	+
	4599	+ if (dev->is_thunderboot) {
	4600	+ spin_unlock_irqrestore(&dev->buffree_lock, flags);
	4601	+ schedule_work(&priv->buffree_work.work);
	4602	+ }
	4603	+ stream->dma_en &= ~RKCIF_DMAEN_BY_ISP;
2274	4604	v4l2_dbg(1, rkcif_debug, &stream->cifdev->v4l2_dev,
2275		- "stream[%d] buf queue, index: %d\n",
2276		- stream->id, vb->index);
	4605	+ "free rx_buf, buf_num %d\n", buf_num);
	4606	+}
	4607	+
	4608	+int rkcif_init_rx_buf(struct rkcif_stream *stream, int buf_num)
	4609	+{
	4610	+ struct rkcif_device *dev = stream->cifdev;
	4611	+ struct v4l2_pix_format_mplane *pixm = &stream->pixm;
	4612	+ struct rkcif_dummy_buffer *dummy;
	4613	+ struct rkcif_rx_buffer *buf;
	4614	+ struct sditf_priv *priv = dev->sditf[0];
	4615	+ int frm_type = 0;
	4616	+ int i = 0;
	4617	+ int ret = 0;
	4618	+
	4619	+ if (!priv)
	4620	+ return -EINVAL;
	4621	+
	4622	+ if (buf_num > RKISP_VICAP_BUF_CNT_MAX)
	4623	+ return -EINVAL;
	4624	+
	4625	+ if (dev->hdr.hdr_mode == NO_HDR) {
	4626	+ if (stream->id == 0)
	4627	+ frm_type = BUF_SHORT;
	4628	+ else
	4629	+ return -EINVAL;
	4630	+ } else if (dev->hdr.hdr_mode == HDR_X2) {
	4631	+ if (stream->id == 0)
	4632	+ frm_type = BUF_MIDDLE;
	4633	+ else if (stream->id == 1)
	4634	+ frm_type = BUF_SHORT;
	4635	+ else
	4636	+ return -EINVAL;
	4637	+ } else if (dev->hdr.hdr_mode == HDR_X3) {
	4638	+ if (stream->id == 0)
	4639	+ frm_type = BUF_LONG;
	4640	+ else if (stream->id == 1)
	4641	+ frm_type = BUF_MIDDLE;
	4642	+ else if (stream->id == 2)
	4643	+ frm_type = BUF_SHORT;
	4644	+ else
	4645	+ return -EINVAL;
	4646	+ }
	4647	+ while (true) {
	4648	+ buf = &stream->rx_buf[i];
	4649	+ memset(buf, 0, sizeof(*buf));
	4650	+ dummy = &buf->dummy;
	4651	+ dummy->size = pixm->plane_fmt[0].sizeimage;
	4652	+ dummy->is_need_vaddr = true;
	4653	+ dummy->is_need_dbuf = true;
	4654	+ if (dev->is_thunderboot) {
	4655	+ buf->buf_idx = i;
	4656	+ ret = rkcif_alloc_reserved_mem_buf(dev, buf);
	4657	+ if (ret) {
	4658	+ priv->buf_num = i;
	4659	+ v4l2_info(&dev->v4l2_dev,
	4660	+ "reserved mem support alloc buf num %d, require buf num %d\n",
	4661	+ i, buf_num);
	4662	+ break;
	4663	+ }
	4664	+ if (dev->rdbk_debug)
	4665	+ v4l2_info(&dev->v4l2_dev,
	4666	+ "stream[%d] buf addr 0x%llx\n",
	4667	+ stream->id, (u64)dummy->dma_addr);
	4668	+ } else {
	4669	+ ret = rkcif_alloc_buffer(dev, dummy);
	4670	+ if (ret) {
	4671	+ priv->buf_num = i;
	4672	+ v4l2_info(&dev->v4l2_dev,
	4673	+ "alloc buf num %d, require buf num %d\n",
	4674	+ i, buf_num);
	4675	+ break;
	4676	+ }
	4677	+ buf->dbufs.dbuf = dummy->dbuf;
	4678	+ }
	4679	+ buf->dbufs.is_init = false;
	4680	+ buf->dbufs.type = frm_type;
	4681	+ list_add_tail(&buf->list, &stream->rx_buf_head);
	4682	+ dummy->is_free = false;
	4683	+ if (stream->is_compact)
	4684	+ buf->dbufs.is_uncompact = false;
	4685	+ else
	4686	+ buf->dbufs.is_uncompact = true;
	4687	+ if (priv && priv->mode.rdbk_mode == RKISP_VICAP_ONLINE && i == 0) {
	4688	+ buf->dbufs.is_first = true;
	4689	+ rkcif_s_rx_buffer(dev, &buf->dbufs);
	4690	+ }
	4691	+ i++;
	4692	+ if (!dev->is_thunderboot && i >= buf_num) {
	4693	+ break;
	4694	+ } else if (i >= RKISP_VICAP_BUF_CNT_MAX) {
	4695	+ priv->buf_num = i;
	4696	+ v4l2_info(&dev->v4l2_dev,
	4697	+ "reserved mem alloc buf num %d\n", i);
	4698	+ break;
	4699	+ }
	4700	+ v4l2_dbg(1, rkcif_debug, &dev->v4l2_dev,
	4701	+ "init rx_buf,dma_addr 0x%llx size: 0x%x\n",
	4702	+ (u64)dummy->dma_addr, pixm->plane_fmt[0].sizeimage);
	4703	+ }
	4704	+ if (priv->buf_num) {
	4705	+ stream->total_buf_num = priv->buf_num;
	4706	+ atomic_set(&stream->buf_cnt, priv->buf_num);
	4707	+ return 0;
	4708	+ } else {
	4709	+ return -EINVAL;
	4710	+ }
2277	4711	}
2278	4712
2279	4713	static int rkcif_create_dummy_buf(struct rkcif_stream *stream)
2280	4714	{
2281		- u32 fourcc;
2282	4715	struct rkcif_device *dev = stream->cifdev;
2283		- struct rkcif_dummy_buffer *dummy_buf = &dev->dummy_buf;
2284		- struct rkcif_hw *hw_dev = dev->hw_dev;
	4716	+ struct rkcif_hw *hw = dev->hw_dev;
	4717	+ struct rkcif_dummy_buffer *dummy_buf = &hw->dummy_buf;
	4718	+ struct rkcif_device *tmp_dev = NULL;
	4719	+ struct v4l2_subdev_frame_interval_enum fie;
	4720	+ struct v4l2_subdev_format fmt;
	4721	+ u32 max_size = 0;
	4722	+ u32 size = 0;
	4723	+ int ret = 0;
	4724	+ int i, j;
2285	4725
2286		- /* get a maximum plane size */
2287		- dummy_buf->size = max3(stream->pixm.plane_fmt[0].bytesperline *
2288		- stream->pixm.height,
2289		- stream->pixm.plane_fmt[1].sizeimage,
2290		- stream->pixm.plane_fmt[2].sizeimage);
2291		- /*
2292		- * rk cif don't support output yuyv fmt data
2293		- * if user request yuyv fmt, the input mode must be RAW8
2294		- * and the width is double Because the real input fmt is
2295		- * yuyv
2296		- */
2297		- fourcc = stream->cif_fmt_out->fourcc;
2298		- if (fourcc == V4L2_PIX_FMT_YUYV \|\| fourcc == V4L2_PIX_FMT_YVYU \|\|
2299		- fourcc == V4L2_PIX_FMT_UYVY \|\| fourcc == V4L2_PIX_FMT_VYUY)
2300		- dummy_buf->size *= 2;
	4726	+ for (i = 0; i < hw->dev_num; i++) {
	4727	+ tmp_dev = hw->cif_dev[i];
	4728	+ if (tmp_dev->terminal_sensor.sd) {
	4729	+ for (j = 0; j < 32; j++) {
	4730	+ memset(&fie, 0, sizeof(fie));
	4731	+ fie.index = j;
	4732	+ fie.pad = 0;
	4733	+ fie.which = V4L2_SUBDEV_FORMAT_ACTIVE;
	4734	+ ret = v4l2_subdev_call(tmp_dev->terminal_sensor.sd,
	4735	+ pad, enum_frame_interval,
	4736	+ NULL, &fie);
	4737	+ if (!ret) {
	4738	+ if (fie.code == MEDIA_BUS_FMT_RGB888_1X24)
	4739	+ size = fie.width * fie.height * 3;
	4740	+ else
	4741	+ size = fie.width * fie.height * 2;
	4742	+ v4l2_dbg(1, rkcif_debug, &dev->v4l2_dev,
	4743	+ "%s enum fmt, width %d, height %d\n",
	4744	+ __func__, fie.width, fie.height);
	4745	+ } else {
	4746	+ break;
	4747	+ }
	4748	+ if (size > max_size)
	4749	+ max_size = size;
	4750	+ }
	4751	+ } else {
	4752	+ continue;
	4753	+ }
	4754	+ }
2301	4755
2302		- dummy_buf->vaddr = dma_alloc_coherent(hw_dev->dev, dummy_buf->size,
2303		- &dummy_buf->dma_addr,
2304		- GFP_KERNEL);
2305		- if (!dummy_buf->vaddr) {
	4756	+ if (max_size == 0 && dev->terminal_sensor.sd) {
	4757	+ fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
	4758	+ ret = v4l2_subdev_call(dev->terminal_sensor.sd,
	4759	+ pad, get_fmt, NULL, &fmt);
	4760	+ if (!ret) {
	4761	+ if (fmt.format.code == MEDIA_BUS_FMT_RGB888_1X24)
	4762	+ size = fmt.format.width * fmt.format.height * 3;
	4763	+ else
	4764	+ size = fmt.format.width * fmt.format.height * 2;
	4765	+ if (size > max_size)
	4766	+ max_size = size;
	4767	+ }
	4768	+ }
	4769	+
	4770	+ dummy_buf->size = max_size;
	4771	+
	4772	+ dummy_buf->is_need_vaddr = true;
	4773	+ dummy_buf->is_need_dbuf = true;
	4774	+ ret = rkcif_alloc_buffer(dev, dummy_buf);
	4775	+ if (ret) {
2306	4776	v4l2_err(&dev->v4l2_dev,
2307	4777	"Failed to allocate the memory for dummy buffer\n");
2308	4778	return -ENOMEM;
..	..	@@ -2311,18 +4781,16 @@
2311	4781	v4l2_info(&dev->v4l2_dev, "Allocate dummy buffer, size: 0x%08x\n",
2312	4782	dummy_buf->size);
2313	4783
2314		- return 0;
	4784	+ return ret;
2315	4785	}
2316	4786
2317	4787	static void rkcif_destroy_dummy_buf(struct rkcif_stream *stream)
2318	4788	{
2319	4789	struct rkcif_device *dev = stream->cifdev;
2320		- struct rkcif_dummy_buffer *dummy_buf = &dev->dummy_buf;
2321		- struct rkcif_hw *hw_dev = dev->hw_dev;
	4790	+ struct rkcif_dummy_buffer *dummy_buf = &dev->hw_dev->dummy_buf;
2322	4791
2323	4792	if (dummy_buf->vaddr)
2324		- dma_free_coherent(hw_dev->dev, dummy_buf->size,
2325		- dummy_buf->vaddr, dummy_buf->dma_addr);
	4793	+ rkcif_free_buffer(dev, dummy_buf);
2326	4794	dummy_buf->dma_addr = 0;
2327	4795	dummy_buf->vaddr = NULL;
2328	4796	}
..	..	@@ -2336,7 +4804,7 @@
2336	4804	if (dev->luma_vdev.enable)
2337	4805	rkcif_stop_luma(&dev->luma_vdev);
2338	4806
2339		- if (dev->hdr.mode != NO_HDR) {
	4807	+ if (dev->hdr.hdr_mode != NO_HDR) {
2340	4808	if (dev->chip_id == CHIP_RK1808_CIF) {
2341	4809	val = rkcif_read_register(dev, CIF_REG_MIPI_WATER_LINE);
2342	4810	val \|= CIF_MIPI_LVDS_SW_DMA_IDLE_RK1808;
..	..	@@ -2360,14 +4828,22 @@
2360	4828	reset_control_deassert(cif_hw->cif_rst[i]);
2361	4829
2362	4830	if (cif_hw->iommu_en) {
2363		- struct iommu_domain *domain;
2364		-
2365		- domain = iommu_get_domain_for_dev(cif_hw->dev);
2366		- if (domain) {
2367		- iommu_detach_device(domain, cif_hw->dev);
2368		- iommu_attach_device(domain, cif_hw->dev);
2369		- }
	4831	+ rockchip_iommu_disable(cif_hw->dev);
	4832	+ rockchip_iommu_enable(cif_hw->dev);
2370	4833	}
	4834	+}
	4835	+
	4836	+void rkcif_do_soft_reset(struct rkcif_device *dev)
	4837	+{
	4838	+ if (dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_DPHY \|\|
	4839	+ dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_CPHY \|\|
	4840	+ dev->active_sensor->mbus.type == V4L2_MBUS_CCP2)
	4841	+ rkcif_write_register_or(dev, CIF_REG_MIPI_LVDS_CTRL, 0x000A0000);
	4842	+ else
	4843	+ rkcif_write_register_or(dev, CIF_REG_DVP_CTRL, 0x000A0000);
	4844	+ usleep_range(10, 20);
	4845	+ v4l2_dbg(1, rkcif_debug, &dev->v4l2_dev,
	4846	+ "vicap do soft reset 0x%x\n", 0x000A0000);
2371	4847	}
2372	4848
2373	4849	static void rkcif_release_rdbk_buf(struct rkcif_stream *stream)
..	..	@@ -2412,9 +4888,52 @@
2412	4888
2413	4889	}
2414	4890
2415		-static void rkcif_stop_streaming(struct vb2_queue *queue)
	4891	+static void rkcif_detach_sync_mode(struct rkcif_device *cif_dev)
2416	4892	{
2417		- struct rkcif_stream *stream = queue->drv_priv;
	4893	+ int i = 0;
	4894	+ struct rkcif_hw *hw = cif_dev->hw_dev;
	4895	+ struct rkcif_device *tmp_dev;
	4896	+ struct rkcif_multi_sync_config *sync_config;
	4897	+
	4898	+ if ((!cif_dev->sync_cfg.type) \|\|
	4899	+ (atomic_read(&cif_dev->pipe.stream_cnt) != 0))
	4900	+ return;
	4901	+ mutex_lock(&hw->dev_lock);
	4902	+ memset(&cif_dev->sync_cfg, 0, sizeof(cif_dev->sync_cfg));
	4903	+ sync_config = &hw->sync_config[cif_dev->sync_cfg.group];
	4904	+ sync_config->streaming_cnt--;
	4905	+ if (cif_dev->sync_cfg.type == EXTERNAL_MASTER_MODE) {
	4906	+ for (i = 0; i < sync_config->ext_master.count; i++) {
	4907	+ tmp_dev = sync_config->ext_master.cif_dev[i];
	4908	+ if (tmp_dev == cif_dev) {
	4909	+ sync_config->ext_master.is_streaming[i] = false;
	4910	+ break;
	4911	+ }
	4912	+ }
	4913	+ }
	4914	+ if (cif_dev->sync_cfg.type == INTERNAL_MASTER_MODE)
	4915	+ sync_config->int_master.is_streaming[0] = false;
	4916	+ if (cif_dev->sync_cfg.type == SLAVE_MODE) {
	4917	+ for (i = 0; i < sync_config->slave.count; i++) {
	4918	+ tmp_dev = sync_config->slave.cif_dev[i];
	4919	+ if (tmp_dev == cif_dev) {
	4920	+ sync_config->slave.is_streaming[i] = false;
	4921	+ break;
	4922	+ }
	4923	+ }
	4924	+ }
	4925	+
	4926	+ if (!sync_config->streaming_cnt && sync_config->is_attach) {
	4927	+ sync_config->is_attach = false;
	4928	+ sync_config->mode = RKCIF_NOSYNC_MODE;
	4929	+ sync_config->dev_cnt = 0;
	4930	+ }
	4931	+ mutex_unlock(&hw->dev_lock);
	4932	+}
	4933	+
	4934	+void rkcif_do_stop_stream(struct rkcif_stream *stream,
	4935	+ unsigned int mode)
	4936	+{
2418	4937	struct rkcif_vdev_node *node = &stream->vnode;
2419	4938	struct rkcif_device *dev = stream->cifdev;
2420	4939	struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
..	..	@@ -2424,95 +4943,170 @@
2424	4943	bool can_reset = true;
2425	4944	int i;
2426	4945	unsigned long flags;
	4946	+ u32 vblank = 0;
	4947	+ u32 frame_time_ns = 0;
	4948	+ u64 cur_time = 0;
	4949	+ u64 fs_time = 0;
2427	4950
2428	4951	mutex_lock(&dev->stream_lock);
2429	4952
2430		- v4l2_info(&dev->v4l2_dev, "stream[%d] start stopping\n", stream->id);
	4953	+ v4l2_info(&dev->v4l2_dev, "stream[%d] start stopping, total mode 0x%x, cur 0x%x\n",
	4954	+ stream->id, stream->cur_stream_mode, mode);
2431	4955
2432		- stream->stopping = true;
	4956	+ if (mode == stream->cur_stream_mode) {
	4957	+ if (stream->dma_en) {
	4958	+ if (!dev->sensor_linetime)
	4959	+ dev->sensor_linetime = rkcif_get_linetime(stream);
	4960	+ vblank = rkcif_get_sensor_vblank(dev);
	4961	+ if (vblank) {
	4962	+ frame_time_ns = (vblank + dev->terminal_sensor.raw_rect.height) *
	4963	+ dev->sensor_linetime;
	4964	+ spin_lock_irqsave(&stream->fps_lock, flags);
	4965	+ fs_time = stream->readout.fs_timestamp;
	4966	+ spin_unlock_irqrestore(&stream->fps_lock, flags);
	4967	+ cur_time = ktime_get_ns();
	4968	+ if (cur_time > fs_time &&
	4969	+ cur_time - fs_time < (frame_time_ns - 10000000)) {
	4970	+ spin_lock_irqsave(&stream->vbq_lock, flags);
	4971	+ if (stream->dma_en & RKCIF_DMAEN_BY_VICAP)
	4972	+ stream->to_stop_dma = RKCIF_DMAEN_BY_VICAP;
	4973	+ else if (stream->dma_en & RKCIF_DMAEN_BY_ISP)
	4974	+ stream->to_stop_dma = RKCIF_DMAEN_BY_ISP;
	4975	+ stream->is_stop_capture = true;
	4976	+ rkcif_stop_dma_capture(stream);
	4977	+ spin_unlock_irqrestore(&stream->vbq_lock, flags);
	4978	+ }
	4979	+ }
	4980	+ }
	4981	+ stream->stopping = true;
	4982	+ ret = wait_event_timeout(stream->wq_stopped,
	4983	+ stream->state != RKCIF_STATE_STREAMING,
	4984	+ msecs_to_jiffies(500));
	4985	+ if (!ret) {
	4986	+ rkcif_stream_stop(stream);
	4987	+ stream->stopping = false;
	4988	+ }
2433	4989
2434		- ret = wait_event_timeout(stream->wq_stopped,
2435		- stream->state != RKCIF_STATE_STREAMING,
2436		- msecs_to_jiffies(1000));
2437		- if (!ret) {
2438		- rkcif_stream_stop(stream);
2439		- stream->stopping = false;
	4990	+ media_pipeline_stop(&node->vdev.entity);
	4991	+ ret = dev->pipe.set_stream(&dev->pipe, false);
	4992	+ if (ret < 0)
	4993	+ v4l2_err(v4l2_dev, "pipeline stream-off failed error:%d\n",
	4994	+ ret);
	4995	+
	4996	+ dev->is_start_hdr = false;
	4997	+ stream->is_dvp_yuv_addr_init = false;
	4998	+ if (stream->skip_info.skip_en) {
	4999	+ stream->skip_info.skip_en = false;
	5000	+ stream->skip_info.skip_to_en = true;
	5001	+ }
	5002	+ } else if (mode == RKCIF_STREAM_MODE_CAPTURE && stream->dma_en & RKCIF_DMAEN_BY_VICAP) {
	5003	+ //only stop dma
	5004	+ stream->to_stop_dma = RKCIF_DMAEN_BY_VICAP;
	5005	+ stream->is_wait_dma_stop = true;
	5006	+ wait_event_timeout(stream->wq_stopped,
	5007	+ !stream->is_wait_dma_stop,
	5008	+ msecs_to_jiffies(1000));
	5009	+ } else if (mode == RKCIF_STREAM_MODE_TOISP && stream->dma_en & RKCIF_DMAEN_BY_VICAP) {
	5010	+ //only stop dma
	5011	+ stream->to_stop_dma = RKCIF_DMAEN_BY_ISP;
	5012	+ stream->is_wait_dma_stop = true;
	5013	+ wait_event_timeout(stream->wq_stopped,
	5014	+ !stream->is_wait_dma_stop,
	5015	+ msecs_to_jiffies(1000));
	5016	+ }
	5017	+ if ((mode & RKCIF_STREAM_MODE_CAPTURE) == RKCIF_STREAM_MODE_CAPTURE) {
	5018	+ /* release buffers */
	5019	+ spin_lock_irqsave(&stream->vbq_lock, flags);
	5020	+ if (stream->curr_buf)
	5021	+ list_add_tail(&stream->curr_buf->queue, &stream->buf_head);
	5022	+ if (stream->next_buf &&
	5023	+ stream->next_buf != stream->curr_buf)
	5024	+ list_add_tail(&stream->next_buf->queue, &stream->buf_head);
	5025	+ spin_unlock_irqrestore(&stream->vbq_lock, flags);
	5026	+
	5027	+ stream->curr_buf = NULL;
	5028	+ stream->next_buf = NULL;
	5029	+
	5030	+ if (dev->hdr.hdr_mode == HDR_X2 \|\|
	5031	+ dev->hdr.hdr_mode == HDR_X3)
	5032	+ rkcif_release_rdbk_buf(stream);
	5033	+
	5034	+ rkcif_rx_buffer_free(stream);
	5035	+ list_for_each_entry(buf, &stream->buf_head, queue) {
	5036	+ v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev,
	5037	+ "stream[%d] buf return addr 0x%x\n",
	5038	+ stream->id, buf->buff_addr[0]);
	5039	+ vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
	5040	+ }
	5041	+ INIT_LIST_HEAD(&stream->buf_head);
	5042	+ while (!list_empty(&stream->vb_done_list)) {
	5043	+ buf = list_first_entry(&stream->vb_done_list,
	5044	+ struct rkcif_buffer, queue);
	5045	+ if (buf) {
	5046	+ list_del(&buf->queue);
	5047	+ vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
	5048	+ }
	5049	+ }
	5050	+ stream->total_buf_num = 0;
	5051	+ atomic_set(&stream->buf_cnt, 0);
	5052	+ stream->lack_buf_cnt = 0;
	5053	+ stream->dma_en &= ~RKCIF_DMAEN_BY_VICAP;
2440	5054	}
2441	5055
2442		- media_pipeline_stop(&node->vdev.entity);
2443		- ret = dev->pipe.set_stream(&dev->pipe, false);
2444		- if (ret < 0)
2445		- v4l2_err(v4l2_dev, "pipeline stream-off failed error:%d\n",
2446		- ret);
2447		-
2448		- dev->is_start_hdr = false;
2449		- stream->is_dvp_yuv_addr_init = false;
2450		-
2451		- /* release buffers */
2452		- if (stream->curr_buf)
2453		- list_add_tail(&stream->curr_buf->queue, &stream->buf_head);
2454		-
2455		- if (stream->next_buf &&
2456		- stream->next_buf != stream->curr_buf)
2457		- list_add_tail(&stream->next_buf->queue, &stream->buf_head);
2458		-
2459		- if (dev->hdr.mode != NO_HDR)
2460		- rkcif_release_rdbk_buf(stream);
2461		-
2462		- stream->curr_buf = NULL;
2463		- stream->next_buf = NULL;
2464		-
2465		- while (!list_empty(&stream->buf_head)) {
2466		- buf = list_first_entry(&stream->buf_head,
2467		- struct rkcif_buffer, queue);
2468		- list_del(&buf->queue);
2469		- vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
2470		- }
2471		-
2472		- ret = dev->pipe.close(&dev->pipe);
2473		- if (ret < 0)
2474		- v4l2_err(v4l2_dev, "pipeline close failed error:%d\n", ret);
2475		-
2476		- if (dev->hdr.mode == HDR_X2) {
2477		- if (dev->stream[RKCIF_STREAM_MIPI_ID0].state == RKCIF_STATE_READY &&
2478		- dev->stream[RKCIF_STREAM_MIPI_ID1].state == RKCIF_STATE_READY) {
	5056	+ if (mode == stream->cur_stream_mode) {
	5057	+ ret = dev->pipe.close(&dev->pipe);
	5058	+ if (ret < 0)
	5059	+ v4l2_err(v4l2_dev, "pipeline close failed error:%d\n", ret);
	5060	+ if (dev->hdr.hdr_mode == HDR_X2) {
	5061	+ if (dev->stream[RKCIF_STREAM_MIPI_ID0].state == RKCIF_STATE_READY &&
	5062	+ dev->stream[RKCIF_STREAM_MIPI_ID1].state == RKCIF_STATE_READY) {
	5063	+ dev->can_be_reset = true;
	5064	+ }
	5065	+ } else if (dev->hdr.hdr_mode == HDR_X3) {
	5066	+ if (dev->stream[RKCIF_STREAM_MIPI_ID0].state == RKCIF_STATE_READY &&
	5067	+ dev->stream[RKCIF_STREAM_MIPI_ID1].state == RKCIF_STATE_READY &&
	5068	+ dev->stream[RKCIF_STREAM_MIPI_ID2].state == RKCIF_STATE_READY) {
	5069	+ dev->can_be_reset = true;
	5070	+ }
	5071	+ } else {
2479	5072	dev->can_be_reset = true;
2480	5073	}
2481		- } else if (dev->hdr.mode == HDR_X3) {
2482		- if (dev->stream[RKCIF_STREAM_MIPI_ID0].state == RKCIF_STATE_READY &&
2483		- dev->stream[RKCIF_STREAM_MIPI_ID1].state == RKCIF_STATE_READY &&
2484		- dev->stream[RKCIF_STREAM_MIPI_ID2].state == RKCIF_STATE_READY) {
2485		- dev->can_be_reset = true;
	5074	+ mutex_lock(&hw_dev->dev_lock);
	5075	+ for (i = 0; i < hw_dev->dev_num; i++) {
	5076	+ if (atomic_read(&hw_dev->cif_dev[i]->pipe.stream_cnt) != 0) {
	5077	+ can_reset = false;
	5078	+ break;
	5079	+ }
2486	5080	}
2487		- } else {
2488		- dev->can_be_reset = true;
2489		- }
2490		-
2491		- spin_lock_irqsave(&hw_dev->hw_timer.timer_lock, flags);
2492		- for (i = 0; i < hw_dev->dev_num; i++) {
2493		- if (atomic_read(&hw_dev->cif_dev[i]->pipe.stream_cnt) != 0) {
2494		- can_reset = false;
2495		- break;
	5081	+ mutex_unlock(&hw_dev->dev_lock);
	5082	+ if (dev->can_be_reset && dev->chip_id >= CHIP_RK3588_CIF)
	5083	+ rkcif_do_soft_reset(dev);
	5084	+ if (dev->can_be_reset && can_reset) {
	5085	+ dev->can_be_reset = false;
	5086	+ dev->reset_work_cancel = true;
	5087	+ dev->early_line = 0;
	5088	+ dev->sensor_linetime = 0;
	5089	+ dev->wait_line = 0;
	5090	+ stream->is_line_wake_up = false;
2496	5091	}
	5092	+ if (can_reset && hw_dev->dummy_buf.vaddr)
	5093	+ rkcif_destroy_dummy_buf(stream);
2497	5094	}
	5095	+ if (mode == RKCIF_STREAM_MODE_CAPTURE)
	5096	+ tasklet_disable(&stream->vb_done_tasklet);
2498	5097
2499		- if (dev->can_be_reset && can_reset) {
2500		- rkcif_do_cru_reset(dev);
2501		- dev->can_be_reset = false;
2502		- dev->reset_work_cancel = true;
2503		- hw_dev->hw_timer.is_running = false;
2504		- hw_dev->reset_info.is_need_reset = 0;
2505		- }
2506		- spin_unlock_irqrestore(&hw_dev->hw_timer.timer_lock, flags);
2507		-
2508		- pm_runtime_put_sync(dev->dev);
2509		-
2510		- if (!atomic_read(&dev->pipe.stream_cnt) && dev->dummy_buf.vaddr)
2511		- rkcif_destroy_dummy_buf(stream);
2512		-
2513		- v4l2_info(&dev->v4l2_dev, "stream[%d] stopping finished\n", stream->id);
2514		-
	5098	+ stream->cur_stream_mode &= ~mode;
	5099	+ INIT_LIST_HEAD(&stream->vb_done_list);
	5100	+ v4l2_info(&dev->v4l2_dev, "stream[%d] stopping finished, dma_en 0x%x\n", stream->id, stream->dma_en);
2515	5101	mutex_unlock(&dev->stream_lock);
	5102	+ rkcif_detach_sync_mode(dev);
	5103	+}
	5104	+
	5105	+static void rkcif_stop_streaming(struct vb2_queue *queue)
	5106	+{
	5107	+ struct rkcif_stream *stream = queue->drv_priv;
	5108	+
	5109	+ rkcif_do_stop_stream(stream, RKCIF_STREAM_MODE_CAPTURE);
2516	5110	}
2517	5111
2518	5112	/*
..	..	@@ -2588,6 +5182,70 @@
2588	5182	return mode;
2589	5183	}
2590	5184
	5185	+static u32 rkcif_determine_input_mode_rk3588(struct rkcif_stream *stream)
	5186	+{
	5187	+ struct rkcif_device *dev = stream->cifdev;
	5188	+ struct rkcif_sensor_info *sensor_info = dev->active_sensor;
	5189	+ struct rkcif_sensor_info *terminal_sensor = &dev->terminal_sensor;
	5190	+ __u32 intf = BT656_STD_RAW;
	5191	+ u32 mode = INPUT_MODE_YUV;
	5192	+ v4l2_std_id std;
	5193	+ int ret;
	5194	+
	5195	+ ret = v4l2_subdev_call(sensor_info->sd, video, querystd, &std);
	5196	+ if (ret == 0) {
	5197	+ /* retrieve std from sensor if exist */
	5198	+ switch (std) {
	5199	+ case V4L2_STD_NTSC:
	5200	+ case V4L2_STD_PAL:
	5201	+ mode = INPUT_BT656_YUV422;
	5202	+ break;
	5203	+ case V4L2_STD_ATSC:
	5204	+ mode = INPUT_BT1120_YUV422;
	5205	+ break;
	5206	+ default:
	5207	+ v4l2_err(&dev->v4l2_dev,
	5208	+ "std: %lld is not supported", std);
	5209	+ }
	5210	+ mode \|= CSI_WRDDR_TYPE_RAW8 << 6;
	5211	+ } else {
	5212	+ /* determine input mode by mbus_code (fmt_type) */
	5213	+ switch (stream->cif_fmt_in->fmt_type) {
	5214	+ case CIF_FMT_TYPE_YUV:
	5215	+ if (sensor_info->mbus.type == V4L2_MBUS_BT656) {
	5216	+ if ((sensor_info->mbus.flags & CIF_DVP_PCLK_DUAL_EDGE) == CIF_DVP_PCLK_DUAL_EDGE)
	5217	+ mode = INPUT_BT1120_YUV422;
	5218	+ else
	5219	+ mode = INPUT_BT656_YUV422;
	5220	+ } else {
	5221	+ mode = INPUT_BT601_YUV422;
	5222	+ }
	5223	+ mode \|= CSI_WRDDR_TYPE_RAW8 << 6;
	5224	+ break;
	5225	+ case CIF_FMT_TYPE_RAW:
	5226	+ ret = v4l2_subdev_call(terminal_sensor->sd,
	5227	+ core, ioctl,
	5228	+ RKMODULE_GET_BT656_INTF_TYPE,
	5229	+ &intf);
	5230	+ if (!ret) {
	5231	+ if (intf == BT656_SONY_RAW)
	5232	+ mode = INPUT_SONY_RAW;
	5233	+ else
	5234	+ mode = INPUT_BT601_RAW;
	5235	+ } else {
	5236	+ mode = INPUT_BT601_RAW;
	5237	+ }
	5238	+ mode \|= stream->cif_fmt_in->csi_fmt_val << 6;
	5239	+ break;
	5240	+ }
	5241	+ }
	5242	+ if (stream->cif_fmt_in->field == V4L2_FIELD_NONE)
	5243	+ mode \|= TRANSMIT_PROGRESS_RK3588;
	5244	+ else
	5245	+ mode \|= TRANSMIT_INTERFACE_RK3588;
	5246	+ return mode;
	5247	+}
	5248	+
2591	5249	static inline u32 rkcif_scl_ctl(struct rkcif_stream *stream)
2592	5250	{
2593	5251	u32 fmt_type = stream->cif_fmt_in->fmt_type;
..	..	@@ -2612,15 +5270,21 @@
2612	5270	case V4L2_PIX_FMT_NV61:
2613	5271	case V4L2_PIX_FMT_NV12:
2614	5272	case V4L2_PIX_FMT_NV21:
2615		- case V4L2_PIX_FMT_YUYV:
2616		- case V4L2_PIX_FMT_YVYU:
2617		- case V4L2_PIX_FMT_UYVY:
2618		- case V4L2_PIX_FMT_VYUY:
2619	5273	case V4L2_PIX_FMT_GREY:
2620	5274	case V4L2_PIX_FMT_Y16:
2621	5275	bpp = fmt->bpp[plane_index];
2622	5276	break;
	5277	+ case V4L2_PIX_FMT_YUYV:
	5278	+ case V4L2_PIX_FMT_YVYU:
	5279	+ case V4L2_PIX_FMT_UYVY:
	5280	+ case V4L2_PIX_FMT_VYUY:
	5281	+ if (stream->cifdev->chip_id < CHIP_RK3588_CIF)
	5282	+ bpp = fmt->bpp[plane_index];
	5283	+ else
	5284	+ bpp = fmt->bpp[plane_index + 1];
	5285	+ break;
2623	5286	case V4L2_PIX_FMT_RGB24:
	5287	+ case V4L2_PIX_FMT_BGR24:
2624	5288	case V4L2_PIX_FMT_RGB565:
2625	5289	case V4L2_PIX_FMT_BGR666:
2626	5290	case V4L2_PIX_FMT_SRGGB8:
..	..	@@ -2636,8 +5300,13 @@
2636	5300	case V4L2_PIX_FMT_SGBRG12:
2637	5301	case V4L2_PIX_FMT_SBGGR12:
2638	5302	case V4L2_PIX_FMT_SBGGR16:
	5303	+ case V4L2_PIX_FMT_SGBRG16:
	5304	+ case V4L2_PIX_FMT_SGRBG16:
	5305	+ case V4L2_PIX_FMT_SRGGB16:
2639	5306	case V4l2_PIX_FMT_SPD16:
2640	5307	case V4l2_PIX_FMT_EBD8:
	5308	+ case V4L2_PIX_FMT_Y10:
	5309	+ case V4L2_PIX_FMT_Y12:
2641	5310	if (stream->cifdev->chip_id < CHIP_RV1126_CIF) {
2642	5311	bpp = max(fmt->bpp[plane_index], (u8)CIF_RAW_STORED_BIT_WIDTH);
2643	5312	cal = CIF_RAW_STORED_BIT_WIDTH;
..	..	@@ -2653,7 +5322,8 @@
2653	5322	}
2654	5323	break;
2655	5324	default:
2656		- pr_err("fourcc: %d is not supported!\n", fmt->fourcc);
	5325	+ v4l2_err(&stream->cifdev->v4l2_dev, "fourcc: %d is not supported!\n",
	5326	+ fmt->fourcc);
2657	5327	break;
2658	5328	}
2659	5329	}
..	..	@@ -2687,7 +5357,8 @@
2687	5357
2688	5358	if (dev->terminal_sensor.sd) {
2689	5359	input_sel.target = V4L2_SEL_TGT_CROP_BOUNDS;
2690		-
	5360	+ input_sel.which = V4L2_SUBDEV_FORMAT_ACTIVE;
	5361	+ input_sel.pad = 0;
2691	5362	ret = v4l2_subdev_call(dev->terminal_sensor.sd,
2692	5363	pad, get_selection, NULL,
2693	5364	&input_sel);
..	..	@@ -2697,6 +5368,7 @@
2697	5368	stream->crop_mask \|= CROP_SRC_SENSOR_MASK;
2698	5369	dev->terminal_sensor.selection = input_sel;
2699	5370	} else {
	5371	+ stream->crop_mask &= ~CROP_SRC_SENSOR_MASK;
2700	5372	dev->terminal_sensor.selection.r = dev->terminal_sensor.raw_rect;
2701	5373	}
2702	5374	}
..	..	@@ -2717,8 +5389,10 @@
2717	5389	stream->crop[CROP_SRC_ACT].top = stream->crop[CROP_SRC_USR].top +
2718	5390	stream->crop[CROP_SRC_SENSOR].top;
2719	5391	}
2720		- } else {
	5392	+ } else if (stream->crop_mask & CROP_SRC_SENSOR_MASK) {
2721	5393	stream->crop[CROP_SRC_ACT] = stream->crop[CROP_SRC_SENSOR];
	5394	+ } else {
	5395	+ stream->crop[CROP_SRC_ACT] = dev->terminal_sensor.raw_rect;
2722	5396	}
2723	5397	}
2724	5398
..	..	@@ -2732,11 +5406,11 @@
2732	5406	struct rkcif_device *dev = stream->cifdev;
2733	5407	struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
2734	5408	struct v4l2_rect input, *crop;
2735		- int vc;
2736	5409
2737	5410	if (dev->terminal_sensor.sd) {
2738		- stream->cif_fmt_in = get_input_fmt(dev->terminal_sensor.sd,
2739		- &input, stream->id, &vc);
	5411	+ stream->cif_fmt_in = rkcif_get_input_fmt(dev,
	5412	+ &input, stream->id,
	5413	+ &dev->channels[stream->id]);
2740	5414	if (!stream->cif_fmt_in) {
2741	5415	v4l2_err(v4l2_dev, "Input fmt is invalid\n");
2742	5416	return -EINVAL;
..	..	@@ -2746,7 +5420,6 @@
2746	5420	return -EINVAL;
2747	5421	}
2748	5422
2749		- stream->vc = vc;
2750	5423	if (stream->cif_fmt_in->mbus_code == MEDIA_BUS_FMT_EBD_1X8 \|\|
2751	5424	stream->cif_fmt_in->mbus_code == MEDIA_BUS_FMT_SPD_2X8) {
2752	5425	stream->crop_enable = false;
..	..	@@ -2764,7 +5437,9 @@
2764	5437	return -EINVAL;
2765	5438	}
2766	5439
2767		- if (dev->active_sensor->mbus.type == V4L2_MBUS_CSI2) {
	5440	+ if (dev->active_sensor &&
	5441	+ (dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_DPHY \|\|
	5442	+ dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_CPHY)) {
2768	5443	if (crop->left > 0) {
2769	5444	int align_x = get_csi_crop_align(stream->cif_fmt_in);
2770	5445
..	..	@@ -2775,7 +5450,7 @@
2775	5450	return -EINVAL;
2776	5451	}
2777	5452	}
2778		- } else if (dev->active_sensor->mbus.type == V4L2_MBUS_CCP2) {
	5453	+ } else if (dev->active_sensor && dev->active_sensor->mbus.type == V4L2_MBUS_CCP2) {
2779	5454	if (crop->left % 4 != 0 && crop->width % 4 != 0) {
2780	5455	v4l2_err(v4l2_dev,
2781	5456	"ERROR: lvds crop left and width must align %d\n", 4);
..	..	@@ -2807,8 +5482,8 @@
2807	5482	__func__, stream->id);
2808	5483	return -ENODEV;
2809	5484	}
2810		- ret = v4l2_subdev_call(sensor->sd, video, g_mbus_config,
2811		- &sensor->mbus);
	5485	+ ret = v4l2_subdev_call(sensor->sd, pad, get_mbus_config,
	5486	+ 0, &sensor->mbus);
2812	5487	if (ret && ret != -ENOIOCTLCMD) {
2813	5488	v4l2_err(&stream->cifdev->v4l2_dev,
2814	5489	"%s: get remote %s mbus failed!\n", __func__, sensor->sd->name);
..	..	@@ -2820,24 +5495,38 @@
2820	5495	terminal_sensor = &stream->cifdev->terminal_sensor;
2821	5496	get_remote_terminal_sensor(stream, &terminal_sensor->sd);
2822	5497	if (terminal_sensor->sd) {
2823		- ret = v4l2_subdev_call(terminal_sensor->sd, video, g_mbus_config,
2824		- &terminal_sensor->mbus);
	5498	+ ret = v4l2_subdev_call(terminal_sensor->sd, pad, get_mbus_config,
	5499	+ 0, &terminal_sensor->mbus);
2825	5500	if (ret && ret != -ENOIOCTLCMD) {
2826	5501	v4l2_err(&stream->cifdev->v4l2_dev,
2827	5502	"%s: get terminal %s mbus failed!\n",
2828	5503	__func__, terminal_sensor->sd->name);
2829	5504	return ret;
2830	5505	}
2831		- if (v4l2_subdev_call(terminal_sensor->sd, core, ioctl, RKMODULE_GET_CSI_DSI_INFO,
2832		- &terminal_sensor->dsi_input_en)) {
2833		- v4l2_dbg(1, rkcif_debug, &stream->cifdev->v4l2_dev,
2834		- "%s: get terminal %s CSI/DSI sel failed, default csi input!\n",
	5506	+ ret = v4l2_subdev_call(terminal_sensor->sd, video,
	5507	+ g_frame_interval, &terminal_sensor->fi);
	5508	+ if (ret) {
	5509	+ v4l2_err(&stream->cifdev->v4l2_dev,
	5510	+ "%s: get terminal %s g_frame_interval failed!\n",
2835	5511	__func__, terminal_sensor->sd->name);
	5512	+ return ret;
	5513	+ }
	5514	+ if (v4l2_subdev_call(terminal_sensor->sd, core, ioctl, RKMODULE_GET_CSI_DSI_INFO,
	5515	+ &terminal_sensor->dsi_input_en)) {
	5516	+ v4l2_dbg(1, rkcif_debug, &stream->cifdev->v4l2_dev,
	5517	+ "%s: get terminal %s CSI/DSI sel failed, default csi input!\n",
	5518	+ __func__, terminal_sensor->sd->name);
2836	5519	terminal_sensor->dsi_input_en = 0;
2837	5520	}
	5521	+ } else {
	5522	+ v4l2_err(&stream->cifdev->v4l2_dev,
	5523	+ "%s: stream[%d] get remote terminal sensor failed!\n",
	5524	+ __func__, stream->id);
	5525	+ return -ENODEV;
2838	5526	}
2839	5527
2840		- if (terminal_sensor->mbus.type == V4L2_MBUS_CSI2 \|\|
	5528	+ if (terminal_sensor->mbus.type == V4L2_MBUS_CSI2_DPHY \|\|
	5529	+ terminal_sensor->mbus.type == V4L2_MBUS_CSI2_CPHY \|\|
2841	5530	terminal_sensor->mbus.type == V4L2_MBUS_CCP2) {
2842	5531	switch (terminal_sensor->mbus.flags & V4L2_MBUS_CSI2_LANES) {
2843	5532	case V4L2_MBUS_CSI2_1_LANE:
..	..	@@ -2864,7 +5553,85 @@
2864	5553	return ret;
2865	5554	}
2866	5555
2867		-static int rkcif_stream_start(struct rkcif_stream *stream)
	5556	+static int rkcif_dvp_get_output_type_mask(struct rkcif_stream *stream)
	5557	+{
	5558	+ unsigned int mask;
	5559	+ const struct cif_output_fmt *fmt = stream->cif_fmt_out;
	5560	+
	5561	+ switch (fmt->fourcc) {
	5562	+ case V4L2_PIX_FMT_NV16:
	5563	+ mask = (CSI_WRDDR_TYPE_YUV422SP_RK3588 << 11) \|
	5564	+ (CSI_YUV_OUTPUT_ORDER_UYVY << 1);
	5565	+ break;
	5566	+ case V4L2_PIX_FMT_NV61:
	5567	+ mask = (CSI_WRDDR_TYPE_YUV422SP_RK3588 << 11) \|
	5568	+ (CSI_YUV_OUTPUT_ORDER_VYUY << 1);
	5569	+ break;
	5570	+ case V4L2_PIX_FMT_NV12:
	5571	+ mask = (CSI_WRDDR_TYPE_YUV420SP_RK3588 << 11) \|
	5572	+ (CSI_YUV_OUTPUT_ORDER_UYVY << 1);
	5573	+ break;
	5574	+ case V4L2_PIX_FMT_NV21:
	5575	+ mask = (CSI_WRDDR_TYPE_YUV420SP_RK3588 << 11) \|
	5576	+ (CSI_YUV_OUTPUT_ORDER_VYUY << 1);
	5577	+ break;
	5578	+ case V4L2_PIX_FMT_YUYV:
	5579	+ mask = (CSI_WRDDR_TYPE_YUV_PACKET << 11) \|
	5580	+ (CSI_YUV_OUTPUT_ORDER_YUYV << 1);
	5581	+ break;
	5582	+ case V4L2_PIX_FMT_YVYU:
	5583	+ mask = (CSI_WRDDR_TYPE_YUV_PACKET << 11) \|
	5584	+ (CSI_YUV_OUTPUT_ORDER_YVYU << 1);
	5585	+ break;
	5586	+ case V4L2_PIX_FMT_UYVY:
	5587	+ mask = (CSI_WRDDR_TYPE_YUV_PACKET << 11) \|
	5588	+ (CSI_YUV_OUTPUT_ORDER_UYVY << 1);
	5589	+ break;
	5590	+ case V4L2_PIX_FMT_VYUY:
	5591	+ mask = (CSI_WRDDR_TYPE_YUV_PACKET << 11) \|
	5592	+ (CSI_YUV_OUTPUT_ORDER_VYUY << 1);
	5593	+ break;
	5594	+ case V4L2_PIX_FMT_RGB24:
	5595	+ case V4L2_PIX_FMT_BGR24:
	5596	+ case V4L2_PIX_FMT_RGB565:
	5597	+ case V4L2_PIX_FMT_BGR666:
	5598	+ mask = CSI_WRDDR_TYPE_RAW_COMPACT << 11;
	5599	+ break;
	5600	+ case V4L2_PIX_FMT_SRGGB8:
	5601	+ case V4L2_PIX_FMT_SGRBG8:
	5602	+ case V4L2_PIX_FMT_SGBRG8:
	5603	+ case V4L2_PIX_FMT_SBGGR8:
	5604	+ case V4L2_PIX_FMT_SRGGB10:
	5605	+ case V4L2_PIX_FMT_SGRBG10:
	5606	+ case V4L2_PIX_FMT_SGBRG10:
	5607	+ case V4L2_PIX_FMT_SBGGR10:
	5608	+ case V4L2_PIX_FMT_SRGGB12:
	5609	+ case V4L2_PIX_FMT_SGRBG12:
	5610	+ case V4L2_PIX_FMT_SGBRG12:
	5611	+ case V4L2_PIX_FMT_SBGGR12:
	5612	+ case V4L2_PIX_FMT_GREY:
	5613	+ case V4L2_PIX_FMT_Y10:
	5614	+ case V4L2_PIX_FMT_Y12:
	5615	+ if (stream->is_compact)
	5616	+ mask = CSI_WRDDR_TYPE_RAW_COMPACT << 11;
	5617	+ else
	5618	+ mask = CSI_WRDDR_TYPE_RAW_UNCOMPACT << 11;
	5619	+ break;
	5620	+ case V4L2_PIX_FMT_SBGGR16:
	5621	+ case V4L2_PIX_FMT_SGBRG16:
	5622	+ case V4L2_PIX_FMT_SGRBG16:
	5623	+ case V4L2_PIX_FMT_SRGGB16:
	5624	+ case V4L2_PIX_FMT_Y16:
	5625	+ mask = CSI_WRDDR_TYPE_RAW_UNCOMPACT << 11;
	5626	+ break;
	5627	+ default:
	5628	+ mask = CSI_WRDDR_TYPE_RAW_COMPACT << 11;
	5629	+ break;
	5630	+ }
	5631	+ return mask;
	5632	+}
	5633	+
	5634	+static int rkcif_stream_start(struct rkcif_stream *stream, unsigned int mode)
2868	5635	{
2869	5636	u32 val, mbus_flags, href_pol, vsync_pol,
2870	5637	xfer_mode = 0, yc_swap = 0, inputmode = 0,
..	..	@@ -2873,20 +5640,66 @@
2873	5640	multi_id_mode = BT656_1120_MULTI_ID_MODE_1,
2874	5641	multi_id_sel = BT656_1120_MULTI_ID_SEL_LSB,
2875	5642	bt1120_edge_mode = BT1120_CLOCK_SINGLE_EDGES,
2876		- bt1120_flags = 0;
	5643	+ bt1120_flags = 0,
	5644	+ out_fmt_mask = 0,
	5645	+ in_fmt_yuv_order = 0;
2877	5646	struct rkmodule_bt656_mbus_info bt1120_info;
2878	5647	struct rkcif_device *dev = stream->cifdev;
2879	5648	struct rkcif_sensor_info *sensor_info;
2880	5649	struct v4l2_mbus_config *mbus;
2881	5650	struct rkcif_dvp_sof_subdev *sof_sd = &dev->dvp_sof_subdev;
2882	5651	const struct cif_output_fmt *fmt;
	5652	+ unsigned int dma_en = 0;
	5653	+ unsigned int dma_state = 0;
	5654	+ int i = 0;
	5655	+ u32 sav_detect = BT656_DETECT_SAV;
	5656	+ u32 reserved = 0;
2883	5657
2884		- if (stream->state != RKCIF_STATE_RESET_IN_STREAMING)
	5658	+ if (stream->state < RKCIF_STATE_STREAMING) {
2885	5659	stream->frame_idx = 0;
	5660	+ stream->buf_wake_up_cnt = 0;
	5661	+ stream->lack_buf_cnt = 0;
	5662	+ stream->frame_phase = 0;
	5663	+ stream->is_in_vblank = false;
	5664	+ stream->is_change_toisp = false;
	5665	+ }
2886	5666
2887	5667	sensor_info = dev->active_sensor;
2888	5668	mbus = &sensor_info->mbus;
2889	5669
	5670	+ dma_state = stream->dma_en;
	5671	+ if ((mode & RKCIF_STREAM_MODE_CAPTURE) == RKCIF_STREAM_MODE_CAPTURE)
	5672	+ stream->dma_en \|= RKCIF_DMAEN_BY_VICAP;
	5673	+ else if ((mode & RKCIF_STREAM_MODE_TOISP_RDBK) == RKCIF_STREAM_MODE_TOISP_RDBK)
	5674	+ stream->dma_en \|= RKCIF_DMAEN_BY_ISP;
	5675	+ else if ((mode & RKCIF_STREAM_MODE_ROCKIT) == RKCIF_STREAM_MODE_ROCKIT)
	5676	+ stream->dma_en \|= RKCIF_DMAEN_BY_ROCKIT;
	5677	+
	5678	+ if (dma_state)
	5679	+ return 0;
	5680	+
	5681	+ mbus_flags = mbus->flags;
	5682	+ if ((mbus_flags & CIF_DVP_PCLK_DUAL_EDGE) == CIF_DVP_PCLK_DUAL_EDGE) {
	5683	+ bt1120_edge_mode = (dev->chip_id < CHIP_RK3588_CIF ?
	5684	+ BT1120_CLOCK_DOUBLE_EDGES : BT1120_CLOCK_DOUBLE_EDGES_RK3588);
	5685	+ rkcif_enable_dvp_clk_dual_edge(dev, true);
	5686	+ } else {
	5687	+ bt1120_edge_mode = dev->chip_id < CHIP_RK3588_CIF ?
	5688	+ BT1120_CLOCK_SINGLE_EDGES : BT1120_CLOCK_SINGLE_EDGES_RK3588;
	5689	+ rkcif_enable_dvp_clk_dual_edge(dev, false);
	5690	+ }
	5691	+
	5692	+ if (IS_ENABLED(CONFIG_CPU_RV1106))
	5693	+ rkcif_config_dvp_pin(dev, true);
	5694	+
	5695	+ if (mbus_flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
	5696	+ rkcif_config_dvp_clk_sampling_edge(dev, RKCIF_CLK_RISING);
	5697	+ else
	5698	+ rkcif_config_dvp_clk_sampling_edge(dev, RKCIF_CLK_FALLING);
	5699	+
	5700	+#if IS_ENABLED(CONFIG_CPU_RV1106)
	5701	+ rv1106_sdmmc_get_lock();
	5702	+#endif
2890	5703	if (sensor_info->sd && mbus->type == V4L2_MBUS_BT656) {
2891	5704	int ret;
2892	5705
..	..	@@ -2910,32 +5723,21 @@
2910	5723	multi_id_mode = BT656_1120_MULTI_ID_MODE_4;
2911	5724	else if (((bt1120_flags & RKMODULE_CAMERA_BT656_CHANNELS) >> 2) > 1)
2912	5725	multi_id_mode = BT656_1120_MULTI_ID_MODE_2;
2913		-
2914		- multi_id = DVP_SW_MULTI_ID(stream->id, stream->id, bt1120_info.id_en_bits);
	5726	+ for (i = 0; i < 4; i++)
	5727	+ multi_id \|= DVP_SW_MULTI_ID(i, i, bt1120_info.id_en_bits);
2915	5728	rkcif_write_register_or(dev, CIF_REG_DVP_MULTI_ID, multi_id);
2916	5729	}
2917	5730	}
2918		-
2919		- mbus_flags = mbus->flags;
2920		- if ((mbus_flags & CIF_DVP_PCLK_DUAL_EDGE) == CIF_DVP_PCLK_DUAL_EDGE) {
2921		- bt1120_edge_mode = BT1120_CLOCK_DOUBLE_EDGES;
2922		- rkcif_enable_dvp_clk_dual_edge(dev, true);
2923		- } else {
2924		- bt1120_edge_mode = BT1120_CLOCK_SINGLE_EDGES;
2925		- rkcif_enable_dvp_clk_dual_edge(dev, false);
2926		- }
2927		-
2928		- if (mbus_flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
2929		- rkcif_config_dvp_clk_sampling_edge(dev, RKCIF_CLK_RISING);
2930		- else
2931		- rkcif_config_dvp_clk_sampling_edge(dev, RKCIF_CLK_FALLING);
2932	5731
2933	5732	href_pol = (mbus_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) ?
2934	5733	HSY_HIGH_ACTIVE : HSY_LOW_ACTIVE;
2935	5734	vsync_pol = (mbus_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) ?
2936	5735	VSY_HIGH_ACTIVE : VSY_LOW_ACTIVE;
2937	5736
2938		- inputmode = rkcif_determine_input_mode(stream);
	5737	+ if (dev->chip_id < CHIP_RK3588_CIF)
	5738	+ inputmode = rkcif_determine_input_mode(stream);
	5739	+ else
	5740	+ inputmode = rkcif_determine_input_mode_rk3588(stream);
2939	5741	if (dev->chip_id <= CHIP_RK1808_CIF) {
2940	5742	if (inputmode == INPUT_MODE_BT1120) {
2941	5743	if (stream->cif_fmt_in->field == V4L2_FIELD_NONE)
..	..	@@ -2945,7 +5747,7 @@
2945	5747	if (CIF_FETCH_IS_Y_FIRST(stream->cif_fmt_in->dvp_fmt_val))
2946	5748	yc_swap = BT1120_YC_SWAP;
2947	5749	}
2948		- } else {
	5750	+ } else if (dev->chip_id < CHIP_RK3588_CIF) {
2949	5751	if (sensor_info->mbus.type == V4L2_MBUS_BT656) {
2950	5752	if (stream->cif_fmt_in->field == V4L2_FIELD_NONE)
2951	5753	xfer_mode = BT1120_TRANSMIT_PROGRESS;
..	..	@@ -2957,9 +5759,14 @@
2957	5759	if (CIF_FETCH_IS_Y_FIRST(stream->cif_fmt_in->dvp_fmt_val))
2958	5760	yc_swap = BT1120_YC_SWAP;
2959	5761	}
	5762	+ } else {
	5763	+ if ((inputmode & INPUT_BT1120_YUV422) == INPUT_BT1120_YUV422)
	5764	+ if (CIF_FETCH_IS_Y_FIRST(stream->cif_fmt_in->dvp_fmt_val))
	5765	+ yc_swap = BT1120_YC_SWAP_RK3588;
2960	5766	}
2961	5767
2962		- if (dev->active_sensor->mbus.type == V4L2_MBUS_CSI2) {
	5768	+ if (dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_DPHY \|\|
	5769	+ dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_CPHY) {
2963	5770	inputmode = INPUT_MODE_MIPI;
2964	5771
2965	5772	/* if cif is linked with mipi,
..	..	@@ -2977,33 +5784,43 @@
2977	5784	mipimode = MIPI_MODE_32BITS_BYPASS;
2978	5785	}
2979	5786
2980		- val = vsync_pol \| href_pol \| inputmode \| mipimode
2981		- \| stream->cif_fmt_out->fmt_val
2982		- \| stream->cif_fmt_in->dvp_fmt_val
2983		- \| xfer_mode \| yc_swap \| multi_id_en
2984		- \| multi_id_sel \| multi_id_mode \| bt1120_edge_mode;
2985		-
2986		- if (stream->is_high_align)
2987		- val \|= CIF_HIGH_ALIGN;
2988		- else
2989		- val &= ~CIF_HIGH_ALIGN;
	5787	+ if (dev->chip_id < CHIP_RK3588_CIF) {
	5788	+ val = vsync_pol \| href_pol \| inputmode \| mipimode
	5789	+ \| stream->cif_fmt_out->fmt_val
	5790	+ \| stream->cif_fmt_in->dvp_fmt_val
	5791	+ \| xfer_mode \| yc_swap \| multi_id_en
	5792	+ \| multi_id_sel \| multi_id_mode \| bt1120_edge_mode;
	5793	+ if (stream->is_high_align)
	5794	+ val \|= CIF_HIGH_ALIGN;
	5795	+ else
	5796	+ val &= ~CIF_HIGH_ALIGN;
	5797	+ } else {
	5798	+ out_fmt_mask = rkcif_dvp_get_output_type_mask(stream);
	5799	+ in_fmt_yuv_order = rkcif_dvp_get_input_yuv_order(stream);
	5800	+ val = vsync_pol \| href_pol \| inputmode
	5801	+ \| yc_swap
	5802	+ \| out_fmt_mask
	5803	+ \| in_fmt_yuv_order
	5804	+ \| multi_id_en
	5805	+ \| sav_detect
	5806	+ \| multi_id_sel \| multi_id_mode \| bt1120_edge_mode;
	5807	+ if (stream->is_high_align)
	5808	+ val \|= CIF_HIGH_ALIGN_RK3588;
	5809	+ else
	5810	+ val &= ~CIF_HIGH_ALIGN_RK3588;
	5811	+ }
2990	5812	rkcif_write_register(dev, CIF_REG_DVP_FOR, val);
2991	5813
2992		- val = stream->pixm.width;
2993		- if (stream->cif_fmt_in->fmt_type == CIF_FMT_TYPE_RAW) {
2994		- fmt = find_output_fmt(stream, stream->pixm.pixelformat);
2995		- if (fmt->fourcc == V4L2_PIX_FMT_GREY \|\|
2996		- fmt->fourcc == V4L2_PIX_FMT_SRGGB8 \|\|
2997		- fmt->fourcc == V4L2_PIX_FMT_SGRBG8 \|\|
2998		- fmt->fourcc == V4L2_PIX_FMT_SGBRG8 \|\|
2999		- fmt->fourcc == V4L2_PIX_FMT_SBGGR8)
	5814	+ if (dev->chip_id >= CHIP_RK3588_CIF) {
	5815	+ val = stream->pixm.plane_fmt[0].bytesperline;
	5816	+ } else {
	5817	+ fmt = rkcif_find_output_fmt(stream, stream->pixm.pixelformat);
	5818	+ if (fmt->fmt_type == CIF_FMT_TYPE_RAW &&
	5819	+ fmt->csi_fmt_val == CSI_WRDDR_TYPE_RAW8)
3000	5820	val = ALIGN(stream->pixm.width * fmt->raw_bpp / 8, 256);
3001	5821	else
3002	5822	val = stream->pixm.width * rkcif_cal_raw_vir_line_ratio(stream, fmt);
3003	5823	}
3004		- rkcif_write_register(dev, CIF_REG_DVP_VIR_LINE_WIDTH, val);
3005		- rkcif_write_register(dev, CIF_REG_DVP_SET_SIZE,
3006		- stream->pixm.width \| (stream->pixm.height << 16));
3007	5824
3008	5825	if (stream->crop_enable) {
3009	5826	dev->channels[stream->id].crop_en = 1;
..	..	@@ -3019,6 +5836,10 @@
3019	5836	dev->channels[stream->id].crop_en = 0;
3020	5837	}
3021	5838
	5839	+ rkcif_write_register(dev, CIF_REG_DVP_VIR_LINE_WIDTH, val);
	5840	+ rkcif_write_register(dev, CIF_REG_DVP_SET_SIZE,
	5841	+ dev->channels[stream->id].width \|
	5842	+ (dev->channels[stream->id].height << 16));
3022	5843	rkcif_write_register(dev, CIF_REG_DVP_CROP,
3023	5844	dev->channels[stream->id].crop_st_y << CIF_CROP_Y_SHIFT \|
3024	5845	dev->channels[stream->id].crop_st_x);
..	..	@@ -3026,17 +5847,44 @@
3026	5847	if (atomic_read(&dev->pipe.stream_cnt) <= 1)
3027	5848	rkcif_write_register(dev, CIF_REG_DVP_FRAME_STATUS, FRAME_STAT_CLS);
3028	5849
3029		- rkcif_write_register(dev, CIF_REG_DVP_INTSTAT, INTSTAT_CLS);
3030		- rkcif_write_register(dev, CIF_REG_DVP_SCL_CTRL, rkcif_scl_ctl(stream));
	5850	+ if (dev->chip_id < CHIP_RK3588_CIF) {
	5851	+ rkcif_write_register(dev, CIF_REG_DVP_INTSTAT, INTSTAT_CLS);
	5852	+ rkcif_write_register(dev, CIF_REG_DVP_SCL_CTRL, rkcif_scl_ctl(stream));
	5853	+ rkcif_write_register_or(dev, CIF_REG_DVP_INTEN,
	5854	+ DVP_DMA_END_INTSTAT(stream->id) \|
	5855	+ INTSTAT_ERR \| PST_INF_FRAME_END);
	5856	+ /* enable line int for sof */
	5857	+ rkcif_write_register(dev, CIF_REG_DVP_LINE_INT_NUM, 0x1);
	5858	+ rkcif_write_register_or(dev, CIF_REG_DVP_INTEN, LINE_INT_EN);
	5859	+ } else {
	5860	+ if (dev->chip_id == CHIP_RV1106_CIF)
	5861	+ reserved = 0xfc3c0000;
	5862	+ else
	5863	+ reserved = 0;
	5864	+ rkcif_write_register(dev, CIF_REG_DVP_INTSTAT, 0x3c3ffff \| reserved);
	5865	+ rkcif_write_register_or(dev, CIF_REG_DVP_INTEN, 0x033ffff);//0x3c3ffff
	5866	+ }
3031	5867
3032		- if (dev->chip_id < CHIP_RK1808_CIF)
3033		- rkcif_assign_new_buffer_oneframe(stream,
3034		- RKCIF_YUV_ADDR_STATE_INIT);
3035		- else
3036		- rkcif_assign_new_buffer_pingpong(stream,
	5868	+ if (stream->dma_en) {
	5869	+ if (dev->chip_id < CHIP_RK1808_CIF) {
	5870	+ rkcif_assign_new_buffer_oneframe(stream,
	5871	+ RKCIF_YUV_ADDR_STATE_INIT);
	5872	+ } else {
	5873	+ if (mode == RKCIF_STREAM_MODE_CAPTURE)
	5874	+ rkcif_assign_new_buffer_pingpong(stream,
3037	5875	RKCIF_YUV_ADDR_STATE_INIT,
3038	5876	stream->id);
3039		-
	5877	+ else if (mode == RKCIF_STREAM_MODE_TOISP \|\|
	5878	+ mode == RKCIF_STREAM_MODE_TOISP_RDBK)
	5879	+ rkcif_assign_new_buffer_pingpong_toisp(stream,
	5880	+ RKCIF_YUV_ADDR_STATE_INIT,
	5881	+ stream->id);
	5882	+ else if (mode == RKCIF_STREAM_MODE_ROCKIT)
	5883	+ rkcif_assign_new_buffer_pingpong_rockit(stream,
	5884	+ RKCIF_YUV_ADDR_STATE_INIT,
	5885	+ stream->id);
	5886	+ }
	5887	+ }
3040	5888	rkcif_write_register_or(dev, CIF_REG_DVP_INTEN,
3041	5889	DVP_DMA_END_INTSTAT(stream->id) \|
3042	5890	INTSTAT_ERR \| PST_INF_FRAME_END);
..	..	@@ -3052,14 +5900,47 @@
3052	5900	else
3053	5901	workmode = MODE_LINELOOP;
3054	5902
3055		- if (inputmode == INPUT_MODE_BT1120) {
	5903	+ if ((inputmode & INPUT_MODE_BT1120) == INPUT_MODE_BT1120) {
3056	5904	workmode = MODE_PINGPONG;
3057	5905	dev->workmode = RKCIF_WORKMODE_PINGPONG;
3058	5906	}
3059	5907
3060		- rkcif_write_register(dev, CIF_REG_DVP_CTRL,
3061		- AXI_BURST_16 \| workmode \| ENABLE_CAPTURE);
3062		-
	5908	+ if (dev->chip_id == CHIP_RK3588_CIF) {
	5909	+ if (stream->dma_en)
	5910	+ dma_en = DVP_DMA_EN;
	5911	+ if (stream->lack_buf_cnt == 2)
	5912	+ dma_en = 0;
	5913	+ rkcif_write_register(dev, CIF_REG_DVP_CTRL,
	5914	+ DVP_SW_WATER_LINE_25
	5915	+ \| dma_en
	5916	+ \| DVP_PRESS_EN
	5917	+ \| DVP_HURRY_EN
	5918	+ \| DVP_SW_WATER_LINE_25
	5919	+ \| DVP_SW_PRESS_VALUE(3)
	5920	+ \| DVP_SW_HURRY_VALUE(3)
	5921	+ \| ENABLE_CAPTURE);
	5922	+ } else if (dev->chip_id == CHIP_RV1106_CIF) {
	5923	+ if (stream->dma_en)
	5924	+ dma_en = DVP_SW_DMA_EN(stream->id);
	5925	+ if (stream->lack_buf_cnt == 2)
	5926	+ dma_en = 0;
	5927	+ rkcif_write_register(dev, CIF_REG_DVP_CTRL,
	5928	+ DVP_SW_WATER_LINE_25
	5929	+ \| DVP_PRESS_EN
	5930	+ \| DVP_HURRY_EN
	5931	+ \| DVP_SW_WATER_LINE_25
	5932	+ \| DVP_SW_PRESS_VALUE(3)
	5933	+ \| DVP_SW_HURRY_VALUE(3)
	5934	+ \| DVP_SW_CAP_EN(stream->id)
	5935	+ \| dma_en
	5936	+ \| ENABLE_CAPTURE);
	5937	+ } else {
	5938	+ rkcif_write_register(dev, CIF_REG_DVP_CTRL,
	5939	+ AXI_BURST_16 \| workmode \| ENABLE_CAPTURE);
	5940	+ }
	5941	+#if IS_ENABLED(CONFIG_CPU_RV1106)
	5942	+ rv1106_sdmmc_put_lock();
	5943	+#endif
3063	5944	atomic_set(&sof_sd->frm_sync_seq, 0);
3064	5945	stream->state = RKCIF_STATE_STREAMING;
3065	5946	stream->cifdev->dvp_sof_in_oneframe = 0;
..	..	@@ -3067,34 +5948,198 @@
3067	5948	return 0;
3068	5949	}
3069	5950
3070		-static int rkcif_start_streaming(struct vb2_queue *queue, unsigned int count)
	5951	+static void rkcif_attach_sync_mode(struct rkcif_device *cifdev)
3071	5952	{
3072		- struct rkcif_stream *stream = queue->drv_priv;
	5953	+ struct rkcif_hw *hw = cifdev->hw_dev;
	5954	+ struct rkcif_device *dev;
	5955	+ struct sditf_priv *priv;
	5956	+ int i = 0, j = 0;
	5957	+ int ret = 0;
	5958	+ int count = 0;
	5959	+ int sync_type = NO_SYNC_MODE;
	5960	+ int sync_group = 0;
	5961	+ struct rkcif_sync_cfg sync_cfg;
	5962	+ struct rkcif_multi_sync_config *sync_config;
	5963	+
	5964	+ mutex_lock(&hw->dev_lock);
	5965	+ if (cifdev->sditf_cnt <= 1) {
	5966	+ ret = v4l2_subdev_call(cifdev->terminal_sensor.sd,
	5967	+ core, ioctl,
	5968	+ RKMODULE_GET_SYNC_MODE,
	5969	+ &sync_type);
	5970	+ if (!ret)
	5971	+ sync_cfg.type = sync_type;
	5972	+ else
	5973	+ sync_cfg.type = NO_SYNC_MODE;
	5974	+ ret = v4l2_subdev_call(cifdev->terminal_sensor.sd,
	5975	+ core, ioctl,
	5976	+ RKMODULE_GET_GROUP_ID,
	5977	+ &sync_group);
	5978	+ if (!ret && sync_group < RKCIF_MAX_GROUP)
	5979	+ sync_cfg.group = sync_group;
	5980	+ else
	5981	+ sync_cfg.group = 0;
	5982	+ } else {
	5983	+ for (j = 0; j < cifdev->sditf_cnt; j++) {
	5984	+ ret \|= v4l2_subdev_call(cifdev->sditf[j]->sensor_sd,
	5985	+ core, ioctl,
	5986	+ RKMODULE_GET_SYNC_MODE,
	5987	+ &sync_type);
	5988	+ if (!ret && sync_type)
	5989	+ break;
	5990	+ }
	5991	+ if (!ret)
	5992	+ sync_cfg.type = sync_type;
	5993	+ else
	5994	+ sync_cfg.type = NO_SYNC_MODE;
	5995	+ ret = v4l2_subdev_call(cifdev->sditf[j]->sensor_sd,
	5996	+ core, ioctl,
	5997	+ RKMODULE_GET_GROUP_ID,
	5998	+ &sync_group);
	5999	+ if (!ret && sync_group < RKCIF_MAX_GROUP)
	6000	+ sync_cfg.group = sync_group;
	6001	+ else
	6002	+ sync_cfg.group = 0;
	6003	+ }
	6004	+ cifdev->sync_cfg = sync_cfg;
	6005	+ if (sync_cfg.type == NO_SYNC_MODE \|\|
	6006	+ hw->sync_config[sync_cfg.group].is_attach) {
	6007	+ mutex_unlock(&hw->dev_lock);
	6008	+ return;
	6009	+ }
	6010	+
	6011	+ sync_config = &hw->sync_config[sync_cfg.group];
	6012	+ memset(sync_config, 0, sizeof(struct rkcif_multi_sync_config));
	6013	+ for (i = 0; i < hw->dev_num; i++) {
	6014	+ dev = hw->cif_dev[i];
	6015	+ if (dev->sditf_cnt <= 1) {
	6016	+ ret = v4l2_subdev_call(dev->terminal_sensor.sd,
	6017	+ core, ioctl,
	6018	+ RKMODULE_GET_SYNC_MODE,
	6019	+ &sync_type);
	6020	+ if (!ret)
	6021	+ sync_cfg.type = sync_type;
	6022	+ else
	6023	+ sync_cfg.type = NO_SYNC_MODE;
	6024	+ ret = v4l2_subdev_call(dev->terminal_sensor.sd,
	6025	+ core, ioctl,
	6026	+ RKMODULE_GET_GROUP_ID,
	6027	+ &sync_group);
	6028	+ if (!ret && sync_group < RKCIF_MAX_GROUP)
	6029	+ sync_cfg.group = sync_group;
	6030	+ else
	6031	+ sync_cfg.group = 0;
	6032	+ } else {
	6033	+ priv = dev->sditf[0];
	6034	+ if (priv && priv->is_combine_mode && dev->sditf_cnt <= RKCIF_MAX_SDITF) {
	6035	+ for (j = 0; j < dev->sditf_cnt; j++) {
	6036	+ ret \|= v4l2_subdev_call(dev->sditf[j]->sensor_sd,
	6037	+ core, ioctl,
	6038	+ RKMODULE_GET_SYNC_MODE,
	6039	+ &sync_type);
	6040	+ if (!ret && sync_type) {
	6041	+ priv = dev->sditf[j];
	6042	+ break;
	6043	+ }
	6044	+ }
	6045	+ if (!ret)
	6046	+ sync_cfg.type = sync_type;
	6047	+ else
	6048	+ sync_cfg.type = NO_SYNC_MODE;
	6049	+ ret = v4l2_subdev_call(priv->sensor_sd,
	6050	+ core, ioctl,
	6051	+ RKMODULE_GET_GROUP_ID,
	6052	+ &sync_group);
	6053	+ if (!ret && sync_group < RKCIF_MAX_GROUP)
	6054	+ sync_cfg.group = sync_group;
	6055	+ else
	6056	+ sync_cfg.group = 0;
	6057	+ }
	6058	+ }
	6059	+ if (sync_cfg.group == cifdev->sync_cfg.group) {
	6060	+ if (sync_cfg.type == EXTERNAL_MASTER_MODE) {
	6061	+ count = sync_config->ext_master.count;
	6062	+ sync_config->ext_master.cif_dev[count] = dev;
	6063	+ sync_config->ext_master.count++;
	6064	+ sync_config->dev_cnt++;
	6065	+ sync_config->sync_mask \|= BIT(dev->csi_host_idx);
	6066	+ } else if (sync_cfg.type == INTERNAL_MASTER_MODE) {
	6067	+ count = sync_config->int_master.count;
	6068	+ sync_config->int_master.cif_dev[count] = dev;
	6069	+ sync_config->int_master.count++;
	6070	+ sync_config->dev_cnt++;
	6071	+ sync_config->sync_mask \|= BIT(dev->csi_host_idx);
	6072	+ } else if (sync_cfg.type == SLAVE_MODE) {
	6073	+ count = sync_config->slave.count;
	6074	+ sync_config->slave.cif_dev[count] = dev;
	6075	+ sync_config->slave.count++;
	6076	+ sync_config->dev_cnt++;
	6077	+ sync_config->sync_mask \|= BIT(dev->csi_host_idx);
	6078	+ }
	6079	+ dev->sync_cfg = sync_cfg;
	6080	+ } else {
	6081	+ ret = v4l2_subdev_call(dev->terminal_sensor.sd,
	6082	+ core, ioctl,
	6083	+ RKMODULE_GET_SYNC_MODE,
	6084	+ &sync_type);
	6085	+ }
	6086	+ }
	6087	+ if (sync_config->int_master.count == 1) {
	6088	+ if (sync_config->ext_master.count) {
	6089	+ sync_config->mode = RKCIF_MASTER_MASTER;
	6090	+ sync_config->is_attach = true;
	6091	+ } else if (sync_config->slave.count) {
	6092	+ sync_config->mode = RKCIF_MASTER_SLAVE;
	6093	+ sync_config->is_attach = true;
	6094	+ } else {
	6095	+ dev_info(hw->dev,
	6096	+ "Missing slave device, do not use sync mode\n");
	6097	+ }
	6098	+ if (sync_config->is_attach)
	6099	+ dev_info(hw->dev,
	6100	+ "group %d, int_master %d, ext_master %d, slave %d\n",
	6101	+ i,
	6102	+ sync_config->int_master.count,
	6103	+ sync_config->ext_master.count,
	6104	+ sync_config->slave.count);
	6105	+ }
	6106	+ mutex_unlock(&hw->dev_lock);
	6107	+}
	6108	+
	6109	+static void rkcif_monitor_reset_event(struct rkcif_device *dev);
	6110	+
	6111	+int rkcif_do_start_stream(struct rkcif_stream *stream, unsigned int mode)
	6112	+{
3073	6113	struct rkcif_vdev_node *node = &stream->vnode;
3074	6114	struct rkcif_device *dev = stream->cifdev;
	6115	+ struct rkcif_hw *hw_dev = dev->hw_dev;
3075	6116	struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
3076	6117	struct rkcif_sensor_info *sensor_info = dev->active_sensor;
3077		- struct rkcif_sensor_info *terminal_sensor = &dev->terminal_sensor;
	6118	+ struct rkcif_sensor_info *terminal_sensor = NULL;
3078	6119	struct rkmodule_hdr_cfg hdr_cfg;
	6120	+ struct rkcif_csi_info csi_info = {0};
3079	6121	int rkmodule_stream_seq = RKMODULE_START_STREAM_DEFAULT;
3080	6122	int ret;
	6123	+ int i = 0;
3081	6124
3082	6125	v4l2_info(&dev->v4l2_dev, "stream[%d] start streaming\n", stream->id);
3083	6126
	6127	+ rkcif_attach_sync_mode(dev);
3084	6128	mutex_lock(&dev->stream_lock);
3085	6129
3086		- if (WARN_ON(stream->state != RKCIF_STATE_READY)) {
	6130	+ if ((stream->cur_stream_mode & RKCIF_STREAM_MODE_CAPTURE) == mode) {
3087	6131	ret = -EBUSY;
3088	6132	v4l2_err(v4l2_dev, "stream in busy state\n");
3089	6133	goto destroy_buf;
3090	6134	}
	6135	+ if (stream->dma_en == 0)
	6136	+ stream->fs_cnt_in_single_frame = 0;
3091	6137	if (stream->is_line_wake_up)
3092	6138	stream->is_line_inten = true;
3093	6139	else
3094	6140	stream->is_line_inten = false;
3095		- stream->fs_cnt_in_single_frame = 0;
3096	6141
3097		- if (dev->active_sensor) {
	6142	+ if (!dev->active_sensor) {
3098	6143	ret = rkcif_update_sensor_info(stream);
3099	6144	if (ret < 0) {
3100	6145	v4l2_err(v4l2_dev,
..	..	@@ -3103,16 +6148,16 @@
3103	6148	goto out;
3104	6149	}
3105	6150	}
3106		-
	6151	+ terminal_sensor = &dev->terminal_sensor;
3107	6152	if (terminal_sensor->sd) {
3108	6153	ret = v4l2_subdev_call(terminal_sensor->sd,
3109	6154	core, ioctl,
3110	6155	RKMODULE_GET_HDR_CFG,
3111	6156	&hdr_cfg);
3112	6157	if (!ret)
3113		- dev->hdr.mode = hdr_cfg.hdr_mode;
	6158	+ dev->hdr = hdr_cfg;
3114	6159	else
3115		- dev->hdr.mode = NO_HDR;
	6160	+ dev->hdr.hdr_mode = NO_HDR;
3116	6161
3117	6162	ret = v4l2_subdev_call(terminal_sensor->sd,
3118	6163	video, g_frame_interval, &terminal_sensor->fi);
..	..	@@ -3133,109 +6178,149 @@
3133	6178	if (ret < 0)
3134	6179	goto destroy_buf;
3135	6180
	6181	+ mutex_lock(&hw_dev->dev_lock);
	6182	+ if (atomic_read(&dev->pipe.stream_cnt) == 0 &&
	6183	+ dev->active_sensor &&
	6184	+ (dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_DPHY \|\|
	6185	+ dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_CPHY \|\|
	6186	+ dev->active_sensor->mbus.type == V4L2_MBUS_CCP2)) {
	6187	+ if (dev->channels[0].capture_info.mode == RKMODULE_MULTI_DEV_COMBINE_ONE) {
	6188	+ csi_info.csi_num = dev->channels[0].capture_info.multi_dev.dev_num;
	6189	+ if (csi_info.csi_num > RKCIF_MAX_CSI_NUM) {
	6190	+ v4l2_err(v4l2_dev,
	6191	+ "csi num %d, max %d\n",
	6192	+ csi_info.csi_num, RKCIF_MAX_CSI_NUM);
	6193	+ goto out;
	6194	+ }
	6195	+ for (i = 0; i < csi_info.csi_num; i++) {
	6196	+ csi_info.csi_idx[i] = dev->channels[0].capture_info.multi_dev.dev_idx[i];
	6197	+ if (dev->hw_dev->is_rk3588s2)
	6198	+ v4l2_info(v4l2_dev, "rk3588s2 combine mode attach to mipi%d\n",
	6199	+ csi_info.csi_idx[i]);
	6200	+ }
	6201	+ } else {
	6202	+ csi_info.csi_num = 1;
	6203	+ dev->csi_host_idx = dev->csi_host_idx_def;
	6204	+ csi_info.csi_idx[0] = dev->csi_host_idx;
	6205	+ }
	6206	+ ret = v4l2_subdev_call(dev->active_sensor->sd,
	6207	+ core, ioctl,
	6208	+ RKCIF_CMD_SET_CSI_IDX,
	6209	+ &csi_info);
	6210	+ if (ret)
	6211	+ v4l2_err(&dev->v4l2_dev, "set csi idx %d fail\n", dev->csi_host_idx);
	6212	+
	6213	+ }
	6214	+
3136	6215	if (((dev->active_sensor && dev->active_sensor->mbus.type == V4L2_MBUS_BT656) \|\|
3137	6216	dev->is_use_dummybuf) &&
3138		- (!dev->dummy_buf.vaddr)) {
	6217	+ (!dev->hw_dev->dummy_buf.vaddr) &&
	6218	+ mode == RKCIF_STREAM_MODE_CAPTURE) {
3139	6219	ret = rkcif_create_dummy_buf(stream);
3140	6220	if (ret < 0) {
	6221	+ mutex_unlock(&hw_dev->dev_lock);
3141	6222	v4l2_err(v4l2_dev, "Failed to create dummy_buf, %d\n", ret);
3142	6223	goto destroy_buf;
3143	6224	}
3144	6225	}
	6226	+ mutex_unlock(&hw_dev->dev_lock);
3145	6227
3146		- /* enable clocks/power-domains */
3147		- ret = pm_runtime_get_sync(dev->dev);
3148		- if (ret < 0) {
3149		- v4l2_err(v4l2_dev, "Failed to get runtime pm, %d\n",
3150		- ret);
3151		- goto destroy_buf;
	6228	+ if (mode == RKCIF_STREAM_MODE_CAPTURE)
	6229	+ tasklet_enable(&stream->vb_done_tasklet);
	6230	+
	6231	+ if (stream->cur_stream_mode == RKCIF_STREAM_MODE_NONE) {
	6232	+ ret = dev->pipe.open(&dev->pipe, &node->vdev.entity, true);
	6233	+ if (ret < 0) {
	6234	+ v4l2_err(v4l2_dev, "open cif pipeline failed %d\n",
	6235	+ ret);
	6236	+ goto destroy_buf;
	6237	+ }
	6238	+
	6239	+ /*
	6240	+ * start sub-devices
	6241	+ * When use bt601, the sampling edge of cif is random,
	6242	+ * can be rising or fallling after powering on cif.
	6243	+ * To keep the coherence of edge, open sensor in advance.
	6244	+ */
	6245	+ if (sensor_info->mbus.type == V4L2_MBUS_PARALLEL \|\|
	6246	+ rkmodule_stream_seq == RKMODULE_START_STREAM_FRONT) {
	6247	+ ret = dev->pipe.set_stream(&dev->pipe, true);
	6248	+ if (ret < 0)
	6249	+ goto destroy_buf;
	6250	+ }
3152	6251	}
3153		-
3154		- ret = dev->pipe.open(&dev->pipe, &node->vdev.entity, true);
3155		- if (ret < 0) {
3156		- v4l2_err(v4l2_dev, "open cif pipeline failed %d\n",
3157		- ret);
3158		- goto destroy_buf;
3159		- }
3160		-
3161		- /*
3162		- * start sub-devices
3163		- * When use bt601, the sampling edge of cif is random,
3164		- * can be rising or fallling after powering on cif.
3165		- * To keep the coherence of edge, open sensor in advance.
3166		- */
3167		- if (sensor_info->mbus.type == V4L2_MBUS_PARALLEL \|\|
3168		- rkmodule_stream_seq == RKMODULE_START_STREAM_FRONT) {
3169		- ret = dev->pipe.set_stream(&dev->pipe, true);
3170		- if (ret < 0)
3171		- goto runtime_put;
3172		- }
3173		-
3174	6252	if (dev->chip_id >= CHIP_RK1808_CIF) {
3175		- if (dev->active_sensor->mbus.type == V4L2_MBUS_CSI2 \|\|
3176		- dev->active_sensor->mbus.type == V4L2_MBUS_CCP2)
3177		- ret = rkcif_csi_stream_start(stream);
	6253	+ if (dev->active_sensor &&
	6254	+ (dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_DPHY \|\|
	6255	+ dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_CPHY \|\|
	6256	+ dev->active_sensor->mbus.type == V4L2_MBUS_CCP2))
	6257	+ ret = rkcif_csi_stream_start(stream, mode);
3178	6258	else
3179		- ret = rkcif_stream_start(stream);
	6259	+ ret = rkcif_stream_start(stream, mode);
3180	6260	} else {
3181		- ret = rkcif_stream_start(stream);
	6261	+ ret = rkcif_stream_start(stream, mode);
3182	6262	}
3183	6263
3184	6264	if (ret < 0)
3185		- goto runtime_put;
	6265	+ goto destroy_buf;
3186	6266
3187		- ret = media_pipeline_start(&node->vdev.entity, &dev->pipe.pipe);
3188		- if (ret < 0) {
3189		- v4l2_err(&dev->v4l2_dev, "start pipeline failed %d\n",
3190		- ret);
3191		- goto pipe_stream_off;
	6267	+ if (stream->cur_stream_mode == RKCIF_STREAM_MODE_NONE) {
	6268	+ ret = media_pipeline_start(&node->vdev.entity, &dev->pipe.pipe);
	6269	+ if (ret < 0) {
	6270	+ v4l2_err(&dev->v4l2_dev, "start pipeline failed %d\n",
	6271	+ ret);
	6272	+ goto pipe_stream_off;
	6273	+ }
	6274	+
	6275	+ if (sensor_info->mbus.type != V4L2_MBUS_PARALLEL &&
	6276	+ rkmodule_stream_seq != RKMODULE_START_STREAM_FRONT) {
	6277	+ ret = dev->pipe.set_stream(&dev->pipe, true);
	6278	+ if (ret < 0)
	6279	+ goto stop_stream;
	6280	+ }
3192	6281	}
3193		-
3194		- if (sensor_info->mbus.type != V4L2_MBUS_PARALLEL &&
3195		- rkmodule_stream_seq != RKMODULE_START_STREAM_FRONT) {
3196		- ret = dev->pipe.set_stream(&dev->pipe, true);
3197		- if (ret < 0)
3198		- goto stop_stream;
3199		- }
3200		-
3201		- if (dev->hdr.mode == NO_HDR) {
3202		- if (dev->stream[RKCIF_STREAM_MIPI_ID0].state == RKCIF_STATE_STREAMING) {
3203		- rkcif_start_luma(&dev->luma_vdev,
	6282	+ if (dev->chip_id == CHIP_RV1126_CIF \|\|
	6283	+ dev->chip_id == CHIP_RV1126_CIF_LITE \|\|
	6284	+ dev->chip_id == CHIP_RK3568_CIF) {
	6285	+ if (dev->hdr.hdr_mode == NO_HDR) {
	6286	+ if (dev->stream[RKCIF_STREAM_MIPI_ID0].state == RKCIF_STATE_STREAMING)
	6287	+ rkcif_start_luma(&dev->luma_vdev,
	6288	+ dev->stream[RKCIF_STREAM_MIPI_ID0].cif_fmt_in);
	6289	+ } else if (dev->hdr.hdr_mode == HDR_X2) {
	6290	+ if (dev->stream[RKCIF_STREAM_MIPI_ID0].state == RKCIF_STATE_STREAMING &&
	6291	+ dev->stream[RKCIF_STREAM_MIPI_ID1].state == RKCIF_STATE_STREAMING)
	6292	+ rkcif_start_luma(&dev->luma_vdev,
	6293	+ dev->stream[RKCIF_STREAM_MIPI_ID0].cif_fmt_in);
	6294	+ } else if (dev->hdr.hdr_mode == HDR_X3) {
	6295	+ if (dev->stream[RKCIF_STREAM_MIPI_ID0].state == RKCIF_STATE_STREAMING &&
	6296	+ dev->stream[RKCIF_STREAM_MIPI_ID1].state == RKCIF_STATE_STREAMING &&
	6297	+ dev->stream[RKCIF_STREAM_MIPI_ID2].state == RKCIF_STATE_STREAMING)
	6298	+ rkcif_start_luma(&dev->luma_vdev,
3204	6299	dev->stream[RKCIF_STREAM_MIPI_ID0].cif_fmt_in);
3205	6300	}
3206		- } else if (dev->hdr.mode == HDR_X2) {
3207		- if (dev->stream[RKCIF_STREAM_MIPI_ID0].state == RKCIF_STATE_STREAMING &&
3208		- dev->stream[RKCIF_STREAM_MIPI_ID1].state == RKCIF_STATE_STREAMING) {
3209		- rkcif_start_luma(&dev->luma_vdev,
3210		- dev->stream[RKCIF_STREAM_MIPI_ID0].cif_fmt_in);
3211		- }
3212		- } else if (dev->hdr.mode == HDR_X3) {
3213		- if (dev->stream[RKCIF_STREAM_MIPI_ID0].state == RKCIF_STATE_STREAMING &&
3214		- dev->stream[RKCIF_STREAM_MIPI_ID1].state == RKCIF_STATE_STREAMING &&
3215		- dev->stream[RKCIF_STREAM_MIPI_ID2].state == RKCIF_STATE_STREAMING) {
3216		- rkcif_start_luma(&dev->luma_vdev,
3217		- dev->stream[RKCIF_STREAM_MIPI_ID0].cif_fmt_in);
3218		- }
3219	6301	}
3220		-
3221	6302	dev->reset_work_cancel = false;
3222		- if (dev->hdr.mode == NO_HDR)
3223		- stream->streamon_timestamp = ktime_get_ns();
	6303	+ stream->cur_stream_mode \|= mode;
	6304	+ rkcif_monitor_reset_event(dev);
3224	6305	goto out;
3225	6306
3226	6307	stop_stream:
3227	6308	rkcif_stream_stop(stream);
3228	6309	pipe_stream_off:
3229	6310	dev->pipe.set_stream(&dev->pipe, false);
3230		-runtime_put:
3231		- pm_runtime_put_sync(dev->dev);
	6311	+
3232	6312	destroy_buf:
3233		- if (stream->next_buf)
3234		- vb2_buffer_done(&stream->next_buf->vb.vb2_buf,
3235		- VB2_BUF_STATE_QUEUED);
	6313	+ if (mode == RKCIF_STREAM_MODE_CAPTURE)
	6314	+ tasklet_disable(&stream->vb_done_tasklet);
3236	6315	if (stream->curr_buf)
3237		- vb2_buffer_done(&stream->curr_buf->vb.vb2_buf,
3238		- VB2_BUF_STATE_QUEUED);
	6316	+ list_add_tail(&stream->curr_buf->queue, &stream->buf_head);
	6317	+ if (stream->next_buf &&
	6318	+ stream->next_buf != stream->curr_buf)
	6319	+ list_add_tail(&stream->next_buf->queue, &stream->buf_head);
	6320	+
	6321	+ stream->curr_buf = NULL;
	6322	+ stream->next_buf = NULL;
	6323	+ atomic_set(&stream->buf_cnt, 0);
3239	6324	while (!list_empty(&stream->buf_head)) {
3240	6325	struct rkcif_buffer *buf;
3241	6326
..	..	@@ -3247,6 +6332,15 @@
3247	6332
3248	6333	out:
3249	6334	mutex_unlock(&dev->stream_lock);
	6335	+ return ret;
	6336	+}
	6337	+
	6338	+static int rkcif_start_streaming(struct vb2_queue *queue, unsigned int count)
	6339	+{
	6340	+ struct rkcif_stream *stream = queue->drv_priv;
	6341	+ int ret = 0;
	6342	+
	6343	+ ret = rkcif_do_start_stream(stream, RKCIF_STREAM_MODE_CAPTURE);
3250	6344	return ret;
3251	6345	}
3252	6346
..	..	@@ -3269,10 +6363,7 @@
3269	6363	q->io_modes = VB2_MMAP \| VB2_DMABUF;
3270	6364	q->drv_priv = stream;
3271	6365	q->ops = &rkcif_vb2_ops;
3272		- if (hw_dev->iommu_en)
3273		- q->mem_ops = &vb2_dma_sg_memops;
3274		- else
3275		- q->mem_ops = &vb2_dma_contig_memops;
	6366	+ q->mem_ops = hw_dev->mem_ops;
3276	6367	q->buf_struct_size = sizeof(struct rkcif_buffer);
3277	6368	if (stream->cifdev->is_use_dummybuf)
3278	6369	q->min_buffers_needed = 1;
..	..	@@ -3284,14 +6375,17 @@
3284	6375	q->allow_cache_hints = 1;
3285	6376	q->bidirectional = 1;
3286	6377	q->gfp_flags = GFP_DMA32;
	6378	+ if (hw_dev->is_dma_contig)
	6379	+ q->dma_attrs = DMA_ATTR_FORCE_CONTIGUOUS;
3287	6380	return vb2_queue_init(q);
3288	6381	}
3289	6382
3290		-static void rkcif_set_fmt(struct rkcif_stream *stream,
3291		- struct v4l2_pix_format_mplane *pixm,
3292		- bool try)
	6383	+int rkcif_set_fmt(struct rkcif_stream *stream,
	6384	+ struct v4l2_pix_format_mplane *pixm,
	6385	+ bool try)
3293	6386	{
3294	6387	struct rkcif_device *dev = stream->cifdev;
	6388	+ struct sditf_priv *priv = dev->sditf[0];
3295	6389	const struct cif_output_fmt *fmt;
3296	6390	const struct cif_input_fmt *cif_fmt_in = NULL;
3297	6391	struct v4l2_rect input_rect;
..	..	@@ -3299,9 +6393,13 @@
3299	6393	u32 xsubs = 1, ysubs = 1, i;
3300	6394	struct rkmodule_hdr_cfg hdr_cfg;
3301	6395	struct rkcif_extend_info *extend_line = &stream->extend_line;
3302		- int ret, vc;
	6396	+ struct csi_channel_info *channel_info = &dev->channels[stream->id];
	6397	+ int ret;
3303	6398
3304		- fmt = find_output_fmt(stream, pixm->pixelformat);
	6399	+ for (i = 0; i < RKCIF_MAX_PLANE; i++)
	6400	+ memset(&pixm->plane_fmt[i], 0, sizeof(struct v4l2_plane_pix_format));
	6401	+
	6402	+ fmt = rkcif_find_output_fmt(stream, pixm->pixelformat);
3305	6403	if (!fmt)
3306	6404	fmt = &out_fmts[0];
3307	6405
..	..	@@ -3309,10 +6407,19 @@
3309	6407	input_rect.height = RKCIF_DEFAULT_HEIGHT;
3310	6408
3311	6409	if (dev->terminal_sensor.sd) {
3312		- cif_fmt_in = get_input_fmt(dev->terminal_sensor.sd,
3313		- &input_rect, stream->id, &vc);
	6410	+ cif_fmt_in = rkcif_get_input_fmt(dev,
	6411	+ &input_rect, stream->id,
	6412	+ channel_info);
3314	6413	stream->cif_fmt_in = cif_fmt_in;
	6414	+ } else {
	6415	+ v4l2_err(&stream->cifdev->v4l2_dev,
	6416	+ "terminal subdev does not exist\n");
	6417	+ return -EINVAL;
3315	6418	}
	6419	+
	6420	+ ret = rkcif_output_fmt_check(stream, fmt);
	6421	+ if (ret)
	6422	+ return -EINVAL;
3316	6423
3317	6424	if (dev->terminal_sensor.sd) {
3318	6425	ret = v4l2_subdev_call(dev->terminal_sensor.sd,
..	..	@@ -3320,9 +6427,9 @@
3320	6427	RKMODULE_GET_HDR_CFG,
3321	6428	&hdr_cfg);
3322	6429	if (!ret)
3323		- dev->hdr.mode = hdr_cfg.hdr_mode;
	6430	+ dev->hdr = hdr_cfg;
3324	6431	else
3325		- dev->hdr.mode = NO_HDR;
	6432	+ dev->hdr.hdr_mode = NO_HDR;
3326	6433
3327	6434	dev->terminal_sensor.raw_rect = input_rect;
3328	6435	}
..	..	@@ -3343,6 +6450,11 @@
3343	6450	fcc_xysubs(fmt->fourcc, &xsubs, &ysubs);
3344	6451
3345	6452	planes = fmt->cplanes ? fmt->cplanes : fmt->mplanes;
	6453	+
	6454	+ if (cif_fmt_in &&
	6455	+ (cif_fmt_in->mbus_code == MEDIA_BUS_FMT_SPD_2X8 \|\|
	6456	+ cif_fmt_in->mbus_code == MEDIA_BUS_FMT_EBD_1X8))
	6457	+ stream->crop_enable = false;
3346	6458
3347	6459	for (i = 0; i < planes; i++) {
3348	6460	struct v4l2_plane_pix_format *plane_fmt;
..	..	@@ -3366,6 +6478,9 @@
3366	6478	}
3367	6479	}
3368	6480
	6481	+ if (priv && priv->is_combine_mode && dev->sditf_cnt <= RKCIF_MAX_SDITF)
	6482	+ height *= dev->sditf_cnt;
	6483	+
3369	6484	extend_line->pixm.height = height + RKMODULE_EXTEND_LINE;
3370	6485
3371	6486	/* compact mode need bytesperline 4bytes align,
..	..	@@ -3373,25 +6488,29 @@
3373	6488	* to optimize reading and writing of ddr, aliged with 256.
3374	6489	*/
3375	6490	if (fmt->fmt_type == CIF_FMT_TYPE_RAW &&
3376		- (stream->cif_fmt_in->mbus_code == MEDIA_BUS_FMT_EBD_1X8 \|\|
3377		- stream->cif_fmt_in->mbus_code == MEDIA_BUS_FMT_SPD_2X8)) {
	6491	+ cif_fmt_in &&
	6492	+ (cif_fmt_in->mbus_code == MEDIA_BUS_FMT_EBD_1X8 \|\|
	6493	+ cif_fmt_in->mbus_code == MEDIA_BUS_FMT_SPD_2X8)) {
3378	6494	stream->is_compact = false;
3379	6495	}
3380	6496
3381	6497	if (fmt->fmt_type == CIF_FMT_TYPE_RAW && stream->is_compact &&
3382		- (dev->active_sensor->mbus.type == V4L2_MBUS_CSI2 \|\|
	6498	+ (dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_DPHY \|\|
	6499	+ dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_CPHY \|\|
3383	6500	dev->active_sensor->mbus.type == V4L2_MBUS_CCP2) &&
3384		- fmt->csi_fmt_val != CSI_WRDDR_TYPE_RGB888) {
3385		- bpl = ALIGN(width * fmt->raw_bpp / 8, 256);
3386		- } else if (fmt->fourcc == V4L2_PIX_FMT_GREY \|\|
3387		- fmt->fourcc == V4L2_PIX_FMT_SRGGB8 \|\|
3388		- fmt->fourcc == V4L2_PIX_FMT_SGRBG8 \|\|
3389		- fmt->fourcc == V4L2_PIX_FMT_SGBRG8 \|\|
3390		- fmt->fourcc == V4L2_PIX_FMT_SBGGR8) {
	6501	+ fmt->csi_fmt_val != CSI_WRDDR_TYPE_RGB888 &&
	6502	+ fmt->csi_fmt_val != CSI_WRDDR_TYPE_RGB565) {
3391	6503	bpl = ALIGN(width * fmt->raw_bpp / 8, 256);
3392	6504	} else {
3393		- bpp = rkcif_align_bits_per_pixel(stream, fmt, i);
3394		- bpl = width * bpp / CIF_YUV_STORED_BIT_WIDTH;
	6505	+ if (fmt->fmt_type == CIF_FMT_TYPE_RAW && stream->is_compact &&
	6506	+ fmt->csi_fmt_val != CSI_WRDDR_TYPE_RGB888 &&
	6507	+ fmt->csi_fmt_val != CSI_WRDDR_TYPE_RGB565 &&
	6508	+ dev->chip_id >= CHIP_RK3588_CIF) {
	6509	+ bpl = ALIGN(width * fmt->raw_bpp / 8, 256);
	6510	+ } else {
	6511	+ bpp = rkcif_align_bits_per_pixel(stream, fmt, i);
	6512	+ bpl = width * bpp / CIF_YUV_STORED_BIT_WIDTH;
	6513	+ }
3395	6514	}
3396	6515	size = bpl * height;
3397	6516	imagesize += size;
..	..	@@ -3431,6 +6550,7 @@
3431	6550	pixm->width, pixm->height,
3432	6551	stream->pixm.width, stream->pixm.height);
3433	6552	}
	6553	+ return 0;
3434	6554	}
3435	6555
3436	6556	void rkcif_stream_init(struct rkcif_device *dev, u32 id)
..	..	@@ -3445,6 +6565,9 @@
3445	6565	stream->cifdev = dev;
3446	6566
3447	6567	INIT_LIST_HEAD(&stream->buf_head);
	6568	+ INIT_LIST_HEAD(&stream->rx_buf_head);
	6569	+ INIT_LIST_HEAD(&stream->rx_buf_head_vicap);
	6570	+ INIT_LIST_HEAD(&stream->rockit_buf_head);
3448	6571	spin_lock_init(&stream->vbq_lock);
3449	6572	spin_lock_init(&stream->fps_lock);
3450	6573	stream->state = RKCIF_STATE_READY;
..	..	@@ -3480,6 +6603,8 @@
3480	6603	}
3481	6604
3482	6605	stream->is_high_align = false;
	6606	+ stream->is_finish_stop_dma = false;
	6607	+ stream->is_wait_dma_stop = false;
3483	6608
3484	6609	if (dev->chip_id == CHIP_RV1126_CIF \|\|
3485	6610	dev->chip_id == CHIP_RV1126_CIF_LITE)
..	..	@@ -3499,7 +6624,15 @@
3499	6624	dev->wait_line_cache = 0;
3500	6625	dev->wait_line_bak = 0;
3501	6626	}
3502		-
	6627	+ stream->cur_stream_mode = 0;
	6628	+ stream->dma_en = 0;
	6629	+ stream->to_en_dma = 0;
	6630	+ stream->to_stop_dma = 0;
	6631	+ stream->to_en_scale = false;
	6632	+ stream->buf_owner = 0;
	6633	+ stream->buf_replace_cnt = 0;
	6634	+ stream->is_stop_capture = false;
	6635	+ atomic_set(&stream->buf_cnt, 0);
3503	6636	}
3504	6637
3505	6638	static int rkcif_fh_open(struct file *filp)
..	..	@@ -3509,6 +6642,7 @@
3509	6642	struct rkcif_stream *stream = to_rkcif_stream(vnode);
3510	6643	struct rkcif_device *cifdev = stream->cifdev;
3511	6644	int ret;
	6645	+ int i = 0;
3512	6646
3513	6647	ret = rkcif_attach_hw(cifdev);
3514	6648	if (ret)
..	..	@@ -3524,31 +6658,35 @@
3524	6658	return ret;
3525	6659	}
3526	6660
3527		- /*
3528		- * Soft reset via CRU.
3529		- * Because CRU would reset iommu too, so there's not chance
3530		- * to reset cif once we hold buffers after buf queued
3531		- */
3532		- if (cifdev->chip_id == CHIP_RK1808_CIF \|\|
3533		- cifdev->chip_id == CHIP_RV1126_CIF \|\|
3534		- cifdev->chip_id == CHIP_RV1126_CIF_LITE \|\|
3535		- cifdev->chip_id == CHIP_RK3568_CIF) {
3536		- mutex_lock(&cifdev->stream_lock);
3537		- if (!atomic_read(&cifdev->fh_cnt))
3538		- rkcif_soft_reset(cifdev, true);
3539		- atomic_inc(&cifdev->fh_cnt);
3540		- mutex_unlock(&cifdev->stream_lock);
3541		- } else {
3542		- rkcif_soft_reset(cifdev, true);
	6661	+ ret = pm_runtime_resume_and_get(cifdev->dev);
	6662	+ if (ret < 0) {
	6663	+ v4l2_err(vdev, "Failed to get runtime pm, %d\n",
	6664	+ ret);
	6665	+ return ret;
3543	6666	}
3544	6667
3545	6668	ret = v4l2_fh_open(filp);
3546	6669	if (!ret) {
3547		- ret = v4l2_pipeline_pm_use(&vnode->vdev.entity, 1);
	6670	+ mutex_lock(&cifdev->stream_lock);
	6671	+ ret = v4l2_pipeline_pm_get(&vnode->vdev.entity);
	6672	+ v4l2_info(vdev, "open video, entity use_countt %d\n",
	6673	+ vnode->vdev.entity.use_count);
	6674	+ mutex_unlock(&cifdev->stream_lock);
3548	6675	if (ret < 0)
3549	6676	vb2_fop_release(filp);
3550	6677	}
3551		-
	6678	+ if (cifdev->sditf_cnt > 1) {
	6679	+ for (i = 0; i < cifdev->sditf_cnt; i++) {
	6680	+ if (cifdev->sditf[i]->sensor_sd)
	6681	+ ret \|= v4l2_subdev_call(cifdev->sditf[i]->sensor_sd,
	6682	+ core,
	6683	+ s_power,
	6684	+ 1);
	6685	+ }
	6686	+ if (ret < 0)
	6687	+ v4l2_err(vdev, "set sensor power on fail, ret %d\n",
	6688	+ ret);
	6689	+ }
3552	6690	return ret;
3553	6691	}
3554	6692
..	..	@@ -3559,22 +6697,30 @@
3559	6697	struct rkcif_stream *stream = to_rkcif_stream(vnode);
3560	6698	struct rkcif_device *cifdev = stream->cifdev;
3561	6699	int ret = 0;
	6700	+ int i = 0;
3562	6701
3563	6702	ret = vb2_fop_release(filp);
3564	6703	if (!ret) {
3565		- ret = v4l2_pipeline_pm_use(&vnode->vdev.entity, 0);
3566		- if (ret < 0)
3567		- v4l2_err(&cifdev->v4l2_dev,
3568		- "set pipeline power failed %d\n", ret);
	6704	+ mutex_lock(&cifdev->stream_lock);
	6705	+ v4l2_pipeline_pm_put(&vnode->vdev.entity);
	6706	+ v4l2_info(vdev, "close video, entity use_count %d\n",
	6707	+ vnode->vdev.entity.use_count);
	6708	+ mutex_unlock(&cifdev->stream_lock);
3569	6709	}
3570	6710
3571		- mutex_lock(&cifdev->stream_lock);
3572		- if (!atomic_dec_return(&cifdev->fh_cnt))
3573		- rkcif_soft_reset(cifdev, true);
3574		- else if (atomic_read(&cifdev->fh_cnt) < 0)
3575		- atomic_set(&cifdev->fh_cnt, 0);
3576		- mutex_unlock(&cifdev->stream_lock);
3577		-
	6711	+ pm_runtime_put_sync(cifdev->dev);
	6712	+ if (cifdev->sditf_cnt > 1) {
	6713	+ for (i = 0; i < cifdev->sditf_cnt; i++) {
	6714	+ if (cifdev->sditf[i]->sensor_sd)
	6715	+ ret \|= v4l2_subdev_call(cifdev->sditf[i]->sensor_sd,
	6716	+ core,
	6717	+ s_power,
	6718	+ 0);
	6719	+ }
	6720	+ if (ret < 0)
	6721	+ v4l2_err(vdev, "set sensor power on fail, ret %d\n",
	6722	+ ret);
	6723	+ }
3578	6724	return ret;
3579	6725	}
3580	6726
..	..	@@ -3584,6 +6730,9 @@
3584	6730	.unlocked_ioctl = video_ioctl2,
3585	6731	.poll = vb2_fop_poll,
3586	6732	.mmap = vb2_fop_mmap,
	6733	+#ifdef CONFIG_COMPAT
	6734	+ .compat_ioctl32 = video_ioctl2,
	6735	+#endif
3587	6736	};
3588	6737
3589	6738	static int rkcif_enum_input(struct file file, void priv,
..	..	@@ -3602,41 +6751,50 @@
3602	6751	struct v4l2_format *f)
3603	6752	{
3604	6753	struct rkcif_stream *stream = video_drvdata(file);
	6754	+ int ret = 0;
3605	6755
3606		- rkcif_set_fmt(stream, &f->fmt.pix_mp, true);
	6756	+ ret = rkcif_set_fmt(stream, &f->fmt.pix_mp, true);
3607	6757
3608		- return 0;
	6758	+ return ret;
3609	6759	}
3610	6760
3611	6761	static int rkcif_enum_framesizes(struct file file, void prov,
3612	6762	struct v4l2_frmsizeenum *fsize)
3613	6763	{
	6764	+ struct v4l2_frmsize_discrete *d = &fsize->discrete;
3614	6765	struct v4l2_frmsize_stepwise *s = &fsize->stepwise;
3615	6766	struct rkcif_stream *stream = video_drvdata(file);
3616	6767	struct rkcif_device *dev = stream->cifdev;
3617	6768	struct v4l2_rect input_rect;
3618		- int vc;
	6769	+ struct csi_channel_info csi_info;
3619	6770
3620	6771	if (fsize->index != 0)
3621	6772	return -EINVAL;
3622	6773
3623		- if (!find_output_fmt(stream, fsize->pixel_format))
	6774	+ if (!rkcif_find_output_fmt(stream, fsize->pixel_format))
3624	6775	return -EINVAL;
3625	6776
3626	6777	input_rect.width = RKCIF_DEFAULT_WIDTH;
3627	6778	input_rect.height = RKCIF_DEFAULT_HEIGHT;
3628	6779
3629	6780	if (dev->terminal_sensor.sd)
3630		- get_input_fmt(dev->terminal_sensor.sd,
3631		- &input_rect, stream->id, &vc);
	6781	+ rkcif_get_input_fmt(dev,
	6782	+ &input_rect, stream->id,
	6783	+ &csi_info);
3632	6784
3633		- fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE;
3634		- s->min_width = CIF_MIN_WIDTH;
3635		- s->min_height = CIF_MIN_HEIGHT;
3636		- s->max_width = input_rect.width;
3637		- s->max_height = input_rect.height;
3638		- s->step_width = OUTPUT_STEP_WISE;
3639		- s->step_height = OUTPUT_STEP_WISE;
	6785	+ if (dev->hw_dev->adapt_to_usbcamerahal) {
	6786	+ fsize->type = V4L2_FRMSIZE_TYPE_DISCRETE;
	6787	+ d->width = input_rect.width;
	6788	+ d->height = input_rect.height;
	6789	+ } else {
	6790	+ fsize->type = V4L2_FRMSIZE_TYPE_STEPWISE;
	6791	+ s->min_width = CIF_MIN_WIDTH;
	6792	+ s->min_height = CIF_MIN_HEIGHT;
	6793	+ s->max_width = input_rect.width;
	6794	+ s->max_height = input_rect.height;
	6795	+ s->step_width = OUTPUT_STEP_WISE;
	6796	+ s->step_height = OUTPUT_STEP_WISE;
	6797	+ }
3640	6798
3641	6799	return 0;
3642	6800	}
..	..	@@ -3668,13 +6826,19 @@
3668	6826	fi.interval.denominator = 30;
3669	6827	}
3670	6828
3671		- fival->type = V4L2_FRMIVAL_TYPE_CONTINUOUS;
3672		- fival->stepwise.step.numerator = 1;
3673		- fival->stepwise.step.denominator = 1;
3674		- fival->stepwise.max.numerator = 1;
3675		- fival->stepwise.max.denominator = 1;
3676		- fival->stepwise.min.numerator = fi.interval.numerator;
3677		- fival->stepwise.min.denominator = fi.interval.denominator;
	6829	+ if (dev->hw_dev->adapt_to_usbcamerahal) {
	6830	+ fival->type = V4L2_FRMIVAL_TYPE_DISCRETE;
	6831	+ fival->discrete.numerator = fi.interval.numerator;
	6832	+ fival->discrete.denominator = fi.interval.denominator;
	6833	+ } else {
	6834	+ fival->type = V4L2_FRMIVAL_TYPE_CONTINUOUS;
	6835	+ fival->stepwise.step.numerator = 1;
	6836	+ fival->stepwise.step.denominator = 1;
	6837	+ fival->stepwise.max.numerator = 1;
	6838	+ fival->stepwise.max.denominator = 1;
	6839	+ fival->stepwise.min.numerator = fi.interval.numerator;
	6840	+ fival->stepwise.min.denominator = fi.interval.denominator;
	6841	+ }
3678	6842
3679	6843	return 0;
3680	6844	}
..	..	@@ -3683,13 +6847,57 @@
3683	6847	struct v4l2_fmtdesc *f)
3684	6848	{
3685	6849	const struct cif_output_fmt *fmt = NULL;
	6850	+ struct rkcif_stream *stream = video_drvdata(file);
	6851	+ struct rkcif_device *dev = stream->cifdev;
	6852	+ const struct cif_input_fmt *cif_fmt_in = NULL;
	6853	+ struct v4l2_rect input_rect;
	6854	+ int i = 0;
	6855	+ int ret = 0;
	6856	+ int fource_idx = 0;
3686	6857
3687	6858	if (f->index >= ARRAY_SIZE(out_fmts))
3688	6859	return -EINVAL;
3689	6860
3690		- fmt = &out_fmts[f->index];
3691		- f->pixelformat = fmt->fourcc;
	6861	+ if (dev->terminal_sensor.sd) {
	6862	+ cif_fmt_in = rkcif_get_input_fmt(dev,
	6863	+ &input_rect, stream->id,
	6864	+ &dev->channels[stream->id]);
	6865	+ stream->cif_fmt_in = cif_fmt_in;
	6866	+ } else {
	6867	+ v4l2_err(&stream->cifdev->v4l2_dev,
	6868	+ "terminal subdev does not exist\n");
	6869	+ return -EINVAL;
	6870	+ }
3692	6871
	6872	+ if (f->index != 0)
	6873	+ fource_idx = stream->new_fource_idx;
	6874	+
	6875	+ for (i = fource_idx; i < ARRAY_SIZE(out_fmts); i++) {
	6876	+ fmt = &out_fmts[i];
	6877	+ ret = rkcif_output_fmt_check(stream, fmt);
	6878	+ if (!ret) {
	6879	+ f->pixelformat = fmt->fourcc;
	6880	+ stream->new_fource_idx = i + 1;
	6881	+ break;
	6882	+ }
	6883	+ }
	6884	+ if (i == ARRAY_SIZE(out_fmts))
	6885	+ return -EINVAL;
	6886	+
	6887	+ switch (f->pixelformat) {
	6888	+ case V4l2_PIX_FMT_EBD8:
	6889	+ strscpy(f->description,
	6890	+ "Embedded data 8-bit",
	6891	+ sizeof(f->description));
	6892	+ break;
	6893	+ case V4l2_PIX_FMT_SPD16:
	6894	+ strscpy(f->description,
	6895	+ "Shield pix data 16-bit",
	6896	+ sizeof(f->description));
	6897	+ break;
	6898	+ default:
	6899	+ break;
	6900	+ }
3693	6901	return 0;
3694	6902	}
3695	6903
..	..	@@ -3698,15 +6906,16 @@
3698	6906	{
3699	6907	struct rkcif_stream *stream = video_drvdata(file);
3700	6908	struct rkcif_device *dev = stream->cifdev;
	6909	+ int ret = 0;
3701	6910
3702	6911	if (vb2_is_busy(&stream->vnode.buf_queue)) {
3703	6912	v4l2_err(&dev->v4l2_dev, "%s queue busy\n", __func__);
3704	6913	return -EBUSY;
3705	6914	}
3706	6915
3707		- rkcif_set_fmt(stream, &f->fmt.pix_mp, false);
	6916	+ ret = rkcif_set_fmt(stream, &f->fmt.pix_mp, false);
3708	6917
3709		- return 0;
	6918	+ return ret;
3710	6919	}
3711	6920
3712	6921	static int rkcif_g_fmt_vid_cap_mplane(struct file file, void fh,
..	..	@@ -3733,8 +6942,8 @@
3733	6942	return 0;
3734	6943	}
3735	6944
3736		-static int rkcif_cropcap(struct file file, void fh,
3737		- struct v4l2_cropcap *cap)
	6945	+static __maybe_unused int rkcif_cropcap(struct file file, void fh,
	6946	+ struct v4l2_cropcap *cap)
3738	6947	{
3739	6948	struct rkcif_stream *stream = video_drvdata(file);
3740	6949	struct rkcif_device *dev = stream->cifdev;
..	..	@@ -3760,78 +6969,16 @@
3760	6969	return ret;
3761	6970	}
3762	6971
3763		-static int rkcif_s_crop(struct file file, void fh, const struct v4l2_crop *a)
3764		-{
3765		- struct rkcif_stream *stream = video_drvdata(file);
3766		- struct rkcif_device *dev = stream->cifdev;
3767		- const struct v4l2_rect *rect = &a->c;
3768		- struct v4l2_rect sensor_crop;
3769		- struct v4l2_rect *raw_rect = &dev->terminal_sensor.raw_rect;
3770		- int ret;
3771		-
3772		- ret = rkcif_sanity_check_fmt(stream, rect);
3773		- if (ret) {
3774		- v4l2_err(&dev->v4l2_dev, "set crop failed\n");
3775		- return ret;
3776		- }
3777		-
3778		- if (stream->crop_mask & CROP_SRC_SENSOR) {
3779		- sensor_crop = stream->crop[CROP_SRC_SENSOR];
3780		- if (rect->left + rect->width > sensor_crop.width \|\|
3781		- rect->top + rect->height > sensor_crop.height) {
3782		- v4l2_err(&dev->v4l2_dev,
3783		- "crop size is bigger than sensor input:left:%d, top:%d, width:%d, height:%d\n",
3784		- sensor_crop.left, sensor_crop.top, sensor_crop.width, sensor_crop.height);
3785		- return -EINVAL;
3786		- }
3787		- } else {
3788		- if (rect->left + rect->width > raw_rect->width \|\|
3789		- rect->top + rect->height > raw_rect->height) {
3790		- v4l2_err(&dev->v4l2_dev,
3791		- "crop size is bigger than sensor raw input:left:%d, top:%d, width:%d, height:%d\n",
3792		- raw_rect->left, raw_rect->top, raw_rect->width, raw_rect->height);
3793		- return -EINVAL;
3794		- }
3795		- }
3796		-
3797		- stream->crop[CROP_SRC_USR] = *rect;
3798		- stream->crop_enable = true;
3799		- stream->crop_mask \|= CROP_SRC_USR_MASK;
3800		- stream->crop[CROP_SRC_ACT] = stream->crop[CROP_SRC_USR];
3801		- if (stream->crop_mask & CROP_SRC_SENSOR) {
3802		- stream->crop[CROP_SRC_ACT].left = sensor_crop.left + stream->crop[CROP_SRC_USR].left;
3803		- stream->crop[CROP_SRC_ACT].top = sensor_crop.top + stream->crop[CROP_SRC_USR].top;
3804		- }
3805		-
3806		- if (stream->state == RKCIF_STATE_STREAMING) {
3807		- stream->crop_dyn_en = true;
3808		-
3809		- v4l2_info(&dev->v4l2_dev, "enable dynamic crop, S_CROP(%ux%u@%u:%u) type: %d\n",
3810		- rect->width, rect->height, rect->left, rect->top, a->type);
3811		- } else {
3812		- v4l2_info(&dev->v4l2_dev, "static crop, S_CROP(%ux%u@%u:%u) type: %d\n",
3813		- rect->width, rect->height, rect->left, rect->top, a->type);
3814		- }
3815		-
3816		- return ret;
3817		-}
3818		-
3819		-static int rkcif_g_crop(struct file file, void fh, struct v4l2_crop *a)
3820		-{
3821		- struct rkcif_stream *stream = video_drvdata(file);
3822		-
3823		- a->c = stream->crop[CROP_SRC_ACT];
3824		-
3825		- return 0;
3826		-}
3827		-
3828	6972	static int rkcif_s_selection(struct file file, void fh,
3829		- struct v4l2_selection *s)
	6973	+ struct v4l2_selection *s)
3830	6974	{
3831	6975	struct rkcif_stream *stream = video_drvdata(file);
3832	6976	struct rkcif_device *dev = stream->cifdev;
3833	6977	struct v4l2_subdev *sensor_sd;
3834	6978	struct v4l2_subdev_selection sd_sel;
	6979	+ const struct v4l2_rect *rect = &s->r;
	6980	+ struct v4l2_rect sensor_crop;
	6981	+ struct v4l2_rect *raw_rect = &dev->terminal_sensor.raw_rect;
3835	6982	u16 pad = 0;
3836	6983	int ret = 0;
3837	6984
..	..	@@ -3840,18 +6987,69 @@
3840	6987	goto err;
3841	6988	}
3842	6989
3843		- sensor_sd = get_remote_sensor(stream, &pad);
	6990	+ if (s->target == V4L2_SEL_TGT_CROP_BOUNDS) {
	6991	+ sensor_sd = get_remote_sensor(stream, &pad);
3844	6992
3845		- sd_sel.r = s->r;
3846		- sd_sel.pad = pad;
3847		- sd_sel.target = s->target;
3848		- sd_sel.which = V4L2_SUBDEV_FORMAT_ACTIVE;
	6993	+ sd_sel.r = s->r;
	6994	+ sd_sel.pad = pad;
	6995	+ sd_sel.target = s->target;
	6996	+ sd_sel.which = V4L2_SUBDEV_FORMAT_ACTIVE;
3849	6997
3850		- ret = v4l2_subdev_call(sensor_sd, pad, set_selection, NULL, &sd_sel);
3851		- if (!ret) {
3852		- s->r = sd_sel.r;
3853		- v4l2_dbg(1, rkcif_debug, &dev->v4l2_dev, "%s: pad:%d, which:%d, target:%d\n",
3854		- __func__, pad, sd_sel.which, sd_sel.target);
	6998	+ ret = v4l2_subdev_call(sensor_sd, pad, set_selection, NULL, &sd_sel);
	6999	+ if (!ret) {
	7000	+ s->r = sd_sel.r;
	7001	+ v4l2_dbg(1, rkcif_debug, &dev->v4l2_dev, "%s: pad:%d, which:%d, target:%d\n",
	7002	+ __func__, pad, sd_sel.which, sd_sel.target);
	7003	+ }
	7004	+ } else if (s->target == V4L2_SEL_TGT_CROP) {
	7005	+ ret = rkcif_sanity_check_fmt(stream, rect);
	7006	+ if (ret) {
	7007	+ v4l2_err(&dev->v4l2_dev, "set crop failed\n");
	7008	+ return ret;
	7009	+ }
	7010	+
	7011	+ if (stream->crop_mask & CROP_SRC_SENSOR) {
	7012	+ sensor_crop = stream->crop[CROP_SRC_SENSOR];
	7013	+ if (rect->left + rect->width > sensor_crop.width \|\|
	7014	+ rect->top + rect->height > sensor_crop.height) {
	7015	+ v4l2_err(&dev->v4l2_dev,
	7016	+ "crop size is bigger than sensor input:left:%d, top:%d, width:%d, height:%d\n",
	7017	+ sensor_crop.left, sensor_crop.top,
	7018	+ sensor_crop.width, sensor_crop.height);
	7019	+ return -EINVAL;
	7020	+ }
	7021	+ } else {
	7022	+ if (rect->left + rect->width > raw_rect->width \|\|
	7023	+ rect->top + rect->height > raw_rect->height) {
	7024	+ v4l2_err(&dev->v4l2_dev,
	7025	+ "crop size is bigger than sensor raw input:left:%d, top:%d, width:%d, height:%d\n",
	7026	+ raw_rect->left, raw_rect->top,
	7027	+ raw_rect->width, raw_rect->height);
	7028	+ return -EINVAL;
	7029	+ }
	7030	+ }
	7031	+
	7032	+ stream->crop[CROP_SRC_USR] = *rect;
	7033	+ stream->crop_enable = true;
	7034	+ stream->crop_mask \|= CROP_SRC_USR_MASK;
	7035	+ stream->crop[CROP_SRC_ACT] = stream->crop[CROP_SRC_USR];
	7036	+ if (stream->crop_mask & CROP_SRC_SENSOR) {
	7037	+ sensor_crop = stream->crop[CROP_SRC_SENSOR];
	7038	+ stream->crop[CROP_SRC_ACT].left = sensor_crop.left + stream->crop[CROP_SRC_USR].left;
	7039	+ stream->crop[CROP_SRC_ACT].top = sensor_crop.top + stream->crop[CROP_SRC_USR].top;
	7040	+ }
	7041	+
	7042	+ if (stream->state == RKCIF_STATE_STREAMING) {
	7043	+ stream->crop_dyn_en = true;
	7044	+
	7045	+ v4l2_info(&dev->v4l2_dev, "enable dynamic crop, S_SELECTION(%ux%u@%u:%u) target: %d\n",
	7046	+ rect->width, rect->height, rect->left, rect->top, s->target);
	7047	+ } else {
	7048	+ v4l2_info(&dev->v4l2_dev, "static crop, S_SELECTION(%ux%u@%u:%u) target: %d\n",
	7049	+ rect->width, rect->height, rect->left, rect->top, s->target);
	7050	+ }
	7051	+ } else {
	7052	+ goto err;
3855	7053	}
3856	7054
3857	7055	return ret;
..	..	@@ -3861,7 +7059,7 @@
3861	7059	}
3862	7060
3863	7061	static int rkcif_g_selection(struct file file, void fh,
3864		- struct v4l2_selection *s)
	7062	+ struct v4l2_selection *s)
3865	7063	{
3866	7064	struct rkcif_stream *stream = video_drvdata(file);
3867	7065	struct rkcif_device *dev = stream->cifdev;
..	..	@@ -3912,19 +7110,127 @@
3912	7110	return -EINVAL;
3913	7111	}
3914	7112
	7113	+static int rkcif_get_max_common_div(int a, int b)
	7114	+{
	7115	+ int remainder = a % b;
	7116	+
	7117	+ while (remainder != 0) {
	7118	+ a = b;
	7119	+ b = remainder;
	7120	+ remainder = a % b;
	7121	+ }
	7122	+ return b;
	7123	+}
	7124	+
	7125	+void rkcif_set_fps(struct rkcif_stream stream, struct rkcif_fps fps)
	7126	+{
	7127	+ struct rkcif_sensor_info *sensor = &stream->cifdev->terminal_sensor;
	7128	+ struct rkcif_device *cif_dev = stream->cifdev;
	7129	+ struct rkcif_stream *tmp_stream = NULL;
	7130	+ u32 numerator, denominator;
	7131	+ u32 def_fps = 0;
	7132	+ u32 cur_fps = 0;
	7133	+ int cap_m, skip_n;
	7134	+ int i = 0;
	7135	+ int max_common_div;
	7136	+ bool skip_en = false;
	7137	+ s32 vblank_def = 0;
	7138	+ s32 vblank_curr = 0;
	7139	+ int ret = 0;
	7140	+
	7141	+ if (!stream->cifdev->terminal_sensor.sd) {
	7142	+ ret = rkcif_update_sensor_info(stream);
	7143	+ if (ret) {
	7144	+ v4l2_err(&stream->cifdev->v4l2_dev,
	7145	+ "%s update sensor info fail\n",
	7146	+ __func__);
	7147	+ return;
	7148	+ }
	7149	+
	7150	+ }
	7151	+ if (!stream->cifdev->terminal_sensor.sd)
	7152	+ return;
	7153	+ numerator = sensor->fi.interval.numerator;
	7154	+ denominator = sensor->fi.interval.denominator;
	7155	+ def_fps = denominator / numerator;
	7156	+
	7157	+ vblank_def = rkcif_get_sensor_vblank_def(cif_dev);
	7158	+ vblank_curr = rkcif_get_sensor_vblank(cif_dev);
	7159	+ if (vblank_def)
	7160	+ cur_fps = def_fps * (u32)(vblank_def + sensor->raw_rect.height) /
	7161	+ (u32)(vblank_curr + sensor->raw_rect.height);
	7162	+ else
	7163	+ cur_fps = def_fps;
	7164	+
	7165	+ if (fps->fps == 0 \|\| fps->fps > cur_fps) {
	7166	+ v4l2_err(&stream->cifdev->v4l2_dev,
	7167	+ "set fps %d fps failed, current fps %d fps\n",
	7168	+ fps->fps, cur_fps);
	7169	+ return;
	7170	+ }
	7171	+ cap_m = fps->fps;
	7172	+ skip_n = cur_fps - fps->fps;
	7173	+ max_common_div = rkcif_get_max_common_div(cap_m, skip_n);
	7174	+ cap_m /= max_common_div;
	7175	+ skip_n /= max_common_div;
	7176	+ if (cap_m > 64) {
	7177	+ skip_n = skip_n / (cap_m / 64);
	7178	+ if (skip_n == 0)
	7179	+ skip_n = 1;
	7180	+ cap_m = 64;
	7181	+ }
	7182	+ if (skip_n > 7) {
	7183	+ cap_m = cap_m / (skip_n / 7);
	7184	+ if (cap_m == 0)
	7185	+ cap_m = 1;
	7186	+ skip_n = 7;
	7187	+ }
	7188	+
	7189	+ if (fps->fps == cur_fps)
	7190	+ skip_en = false;
	7191	+ else
	7192	+ skip_en = true;
	7193	+
	7194	+ if (fps->ch_num > 1 && fps->ch_num < 4) {
	7195	+ for (i = 0; i < fps->ch_num; i++) {
	7196	+ tmp_stream = &cif_dev->stream[i];
	7197	+ if (skip_en) {
	7198	+ tmp_stream->skip_info.skip_to_en = true;
	7199	+ tmp_stream->skip_info.cap_m = cap_m;
	7200	+ tmp_stream->skip_info.skip_n = skip_n;
	7201	+ } else {
	7202	+ tmp_stream->skip_info.skip_to_dis = true;
	7203	+ }
	7204	+ }
	7205	+ } else {
	7206	+ if (skip_en) {
	7207	+ stream->skip_info.skip_to_en = true;
	7208	+ stream->skip_info.cap_m = cap_m;
	7209	+ stream->skip_info.skip_n = skip_n;
	7210	+ } else {
	7211	+ stream->skip_info.skip_to_dis = true;
	7212	+ }
	7213	+ }
	7214	+ v4l2_dbg(1, rkcif_debug, &stream->cifdev->v4l2_dev,
	7215	+ "skip_to_en %d, cap_m %d, skip_n %d\n",
	7216	+ stream->skip_info.skip_to_en,
	7217	+ cap_m,
	7218	+ skip_n);
	7219	+}
	7220	+
3915	7221	static int rkcif_do_reset_work(struct rkcif_device *cif_dev,
3916	7222	enum rkmodule_reset_src reset_src);
3917	7223
3918	7224	static long rkcif_ioctl_default(struct file file, void fh,
3919		- bool valid_prio, unsigned int cmd, void *arg)
	7225	+ bool valid_prio, unsigned int cmd, void *arg)
3920	7226	{
3921	7227	struct rkcif_stream *stream = video_drvdata(file);
3922	7228	struct rkcif_device *dev = stream->cifdev;
3923	7229	const struct cif_input_fmt *in_fmt;
3924	7230	struct v4l2_rect rect;
3925		- int vc = 0;
3926		- struct rkcif_reset_info *reset_info;
3927		- int reset_src = 0;
	7231	+ struct csi_channel_info csi_info;
	7232	+ struct rkcif_fps fps;
	7233	+ int reset_src;
3928	7234
3929	7235	switch (cmd) {
3930	7236	case RKCIF_CMD_GET_CSI_MEMORY_MODE:
..	..	@@ -3939,7 +7245,8 @@
3939	7245	break;
3940	7246	case RKCIF_CMD_SET_CSI_MEMORY_MODE:
3941	7247	if (dev->terminal_sensor.sd) {
3942		- in_fmt = get_input_fmt(dev->terminal_sensor.sd, &rect, 0, &vc);
	7248	+ in_fmt = rkcif_get_input_fmt(dev,
	7249	+ &rect, 0, &csi_info);
3943	7250	if (in_fmt == NULL) {
3944	7251	v4l2_err(&dev->v4l2_dev, "can't get sensor input format\n");
3945	7252	return -EINVAL;
..	..	@@ -3965,11 +7272,9 @@
3965	7272	stream->is_high_align = false;
3966	7273	}
3967	7274	break;
3968		- case RKCIF_CMD_GET_RESET_INFO:
3969		- reset_info = (struct rkcif_reset_info *)arg;
3970		- *reset_info = dev->hw_dev->reset_info;
3971		- if (dev->hw_dev->reset_info.is_need_reset)
3972		- dev->hw_dev->reset_info.is_need_reset = 0;
	7275	+ case RKCIF_CMD_SET_FPS:
	7276	+ fps = (struct rkcif_fps )arg;
	7277	+ rkcif_set_fps(stream, &fps);
3973	7278	break;
3974	7279	case RKCIF_CMD_SET_RESET:
3975	7280	reset_src = (int )arg;
..	..	@@ -3993,13 +7298,10 @@
3993	7298	.vidioc_streamoff = vb2_ioctl_streamoff,
3994	7299	.vidioc_enum_input = rkcif_enum_input,
3995	7300	.vidioc_try_fmt_vid_cap_mplane = rkcif_try_fmt_vid_cap_mplane,
3996		- .vidioc_enum_fmt_vid_cap_mplane = rkcif_enum_fmt_vid_cap_mplane,
	7301	+ .vidioc_enum_fmt_vid_cap = rkcif_enum_fmt_vid_cap_mplane,
3997	7302	.vidioc_s_fmt_vid_cap_mplane = rkcif_s_fmt_vid_cap_mplane,
3998	7303	.vidioc_g_fmt_vid_cap_mplane = rkcif_g_fmt_vid_cap_mplane,
3999	7304	.vidioc_querycap = rkcif_querycap,
4000		- .vidioc_cropcap = rkcif_cropcap,
4001		- .vidioc_s_crop = rkcif_s_crop,
4002		- .vidioc_g_crop = rkcif_g_crop,
4003	7305	.vidioc_s_selection = rkcif_s_selection,
4004	7306	.vidioc_g_selection = rkcif_g_selection,
4005	7307	.vidioc_enum_frameintervals = rkcif_enum_frameintervals,
..	..	@@ -4007,8 +7309,59 @@
4007	7309	.vidioc_default = rkcif_ioctl_default,
4008	7310	};
4009	7311
	7312	+void rkcif_vb_done_oneframe(struct rkcif_stream *stream,
	7313	+ struct vb2_v4l2_buffer *vb_done)
	7314	+{
	7315	+ const struct cif_output_fmt *fmt = stream->cif_fmt_out;
	7316	+ u32 i;
	7317	+
	7318	+ /* Dequeue a filled buffer */
	7319	+ for (i = 0; i < fmt->mplanes; i++) {
	7320	+ vb2_set_plane_payload(&vb_done->vb2_buf, i,
	7321	+ stream->pixm.plane_fmt[i].sizeimage);
	7322	+ }
	7323	+
	7324	+ vb2_buffer_done(&vb_done->vb2_buf, VB2_BUF_STATE_DONE);
	7325	+ v4l2_dbg(2, rkcif_debug, &stream->cifdev->v4l2_dev,
	7326	+ "stream[%d] vb done, index: %d, sequence %d\n", stream->id,
	7327	+ vb_done->vb2_buf.index, vb_done->sequence);
	7328	+ atomic_dec(&stream->buf_cnt);
	7329	+}
	7330	+
	7331	+static void rkcif_tasklet_handle(unsigned long data)
	7332	+{
	7333	+ struct rkcif_stream stream = (struct rkcif_stream )data;
	7334	+ struct rkcif_buffer *buf = NULL;
	7335	+ unsigned long flags = 0;
	7336	+ LIST_HEAD(local_list);
	7337	+
	7338	+ spin_lock_irqsave(&stream->vbq_lock, flags);
	7339	+ list_replace_init(&stream->vb_done_list, &local_list);
	7340	+ spin_unlock_irqrestore(&stream->vbq_lock, flags);
	7341	+
	7342	+ while (!list_empty(&local_list)) {
	7343	+ buf = list_first_entry(&local_list,
	7344	+ struct rkcif_buffer, queue);
	7345	+ list_del(&buf->queue);
	7346	+ rkcif_vb_done_oneframe(stream, &buf->vb);
	7347	+ }
	7348	+}
	7349	+
	7350	+void rkcif_vb_done_tasklet(struct rkcif_stream stream, struct rkcif_buffer buf)
	7351	+{
	7352	+ unsigned long flags = 0;
	7353	+
	7354	+ if (!stream \|\| !buf)
	7355	+ return;
	7356	+ spin_lock_irqsave(&stream->vbq_lock, flags);
	7357	+ list_add_tail(&buf->queue, &stream->vb_done_list);
	7358	+ spin_unlock_irqrestore(&stream->vbq_lock, flags);
	7359	+ tasklet_schedule(&stream->vb_done_tasklet);
	7360	+}
	7361	+
4010	7362	static void rkcif_unregister_stream_vdev(struct rkcif_stream *stream)
4011	7363	{
	7364	+ tasklet_kill(&stream->vb_done_tasklet);
4012	7365	media_entity_cleanup(&stream->vnode.vdev.entity);
4013	7366	video_unregister_device(&stream->vnode.vdev);
4014	7367	}
..	..	@@ -4042,6 +7395,7 @@
4042	7395	vdev_name = CIF_DVP_VDEV_NAME;
4043	7396	break;
4044	7397	default:
	7398	+ ret = -EINVAL;
4045	7399	v4l2_err(v4l2_dev, "Invalid stream\n");
4046	7400	goto unreg;
4047	7401	}
..	..	@@ -4064,6 +7418,7 @@
4064	7418	vdev_name = CIF_MIPI_ID3_VDEV_NAME;
4065	7419	break;
4066	7420	default:
	7421	+ ret = -EINVAL;
4067	7422	v4l2_err(v4l2_dev, "Invalid stream\n");
4068	7423	goto unreg;
4069	7424	}
..	..	@@ -4082,6 +7437,7 @@
4082	7437	vdev_name = CIF_DVP_ID3_VDEV_NAME;
4083	7438	break;
4084	7439	default:
	7440	+ ret = -EINVAL;
4085	7441	v4l2_err(v4l2_dev, "Invalid stream\n");
4086	7442	goto unreg;
4087	7443	}
..	..	@@ -4108,7 +7464,7 @@
4108	7464	V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE);
4109	7465	vdev->queue = &node->buf_queue;
4110	7466
4111		- ret = video_register_device(vdev, VFL_TYPE_GRABBER, -1);
	7467	+ ret = video_register_device(vdev, VFL_TYPE_VIDEO, -1);
4112	7468	if (ret < 0) {
4113	7469	v4l2_err(v4l2_dev,
4114	7470	"video_register_device failed with error %d\n", ret);
..	..	@@ -4119,6 +7475,11 @@
4119	7475	if (ret < 0)
4120	7476	goto unreg;
4121	7477
	7478	+ INIT_LIST_HEAD(&stream->vb_done_list);
	7479	+ tasklet_init(&stream->vb_done_tasklet,
	7480	+ rkcif_tasklet_handle,
	7481	+ (unsigned long)stream);
	7482	+ tasklet_disable(&stream->vb_done_tasklet);
4122	7483	return 0;
4123	7484	unreg:
4124	7485	video_unregister_device(vdev);
..	..	@@ -4151,7 +7512,7 @@
4151	7512	if (ret < 0)
4152	7513	goto err;
4153	7514	}
4154		-
	7515	+ dev->num_channels = stream_num;
4155	7516	return 0;
4156	7517	err:
4157	7518	for (j = 0; j < i; j++) {
..	..	@@ -4219,8 +7580,8 @@
4219	7580	}
4220	7581
4221	7582	static struct v4l2_rect rkcif_lvds_sd_get_crop(struct rkcif_lvds_subdev subdev,
4222		- struct v4l2_subdev_pad_config *cfg,
4223		- enum v4l2_subdev_format_whence which)
	7583	+ struct v4l2_subdev_pad_config *cfg,
	7584	+ enum v4l2_subdev_format_whence which)
4224	7585	{
4225	7586	if (which == V4L2_SUBDEV_FORMAT_TRY)
4226	7587	return v4l2_subdev_get_try_crop(&subdev->sd, cfg, RKCIF_LVDS_PAD_SINK);
..	..	@@ -4229,8 +7590,8 @@
4229	7590	}
4230	7591
4231	7592	static int rkcif_lvds_sd_set_selection(struct v4l2_subdev *sd,
4232		- struct v4l2_subdev_pad_config *cfg,
4233		- struct v4l2_subdev_selection *sel)
	7593	+ struct v4l2_subdev_pad_config *cfg,
	7594	+ struct v4l2_subdev_selection *sel)
4234	7595	{
4235	7596	struct rkcif_lvds_subdev *subdev = container_of(sd, struct rkcif_lvds_subdev, sd);
4236	7597	struct v4l2_subdev *sensor = get_lvds_remote_sensor(sd);
..	..	@@ -4245,8 +7606,8 @@
4245	7606	}
4246	7607
4247	7608	static int rkcif_lvds_sd_get_selection(struct v4l2_subdev *sd,
4248		- struct v4l2_subdev_pad_config *cfg,
4249		- struct v4l2_subdev_selection *sel)
	7609	+ struct v4l2_subdev_pad_config *cfg,
	7610	+ struct v4l2_subdev_selection *sel)
4250	7611	{
4251	7612	struct rkcif_lvds_subdev *subdev = container_of(sd, struct rkcif_lvds_subdev, sd);
4252	7613	struct v4l2_subdev *sensor = get_lvds_remote_sensor(sd);
..	..	@@ -4302,13 +7663,13 @@
4302	7663	return -EINVAL;
4303	7664	}
4304	7665
4305		-static int rkcif_lvds_g_mbus_config(struct v4l2_subdev *sd,
	7666	+static int rkcif_lvds_g_mbus_config(struct v4l2_subdev *sd, unsigned int pad_id,
4306	7667	struct v4l2_mbus_config *mbus)
4307	7668	{
4308	7669	struct v4l2_subdev *sensor_sd = get_lvds_remote_sensor(sd);
4309	7670	int ret;
4310	7671
4311		- ret = v4l2_subdev_call(sensor_sd, video, g_mbus_config, mbus);
	7672	+ ret = v4l2_subdev_call(sensor_sd, pad, get_mbus_config, 0, mbus);
4312	7673	if (ret)
4313	7674	return ret;
4314	7675
..	..	@@ -4331,12 +7692,13 @@
4331	7692	}
4332	7693
4333	7694	static int rkcif_sof_subscribe_event(struct v4l2_subdev sd, struct v4l2_fh fh,
4334		- struct v4l2_event_subscription *sub)
	7695	+ struct v4l2_event_subscription *sub)
4335	7696	{
4336		- if (sub->type != V4L2_EVENT_FRAME_SYNC)
	7697	+ if (sub->type == V4L2_EVENT_FRAME_SYNC \|\|
	7698	+ sub->type == V4L2_EVENT_RESET_DEV)
	7699	+ return v4l2_event_subscribe(fh, sub, RKCIF_V4L2_EVENT_ELEMS, NULL);
	7700	+ else
4337	7701	return -EINVAL;
4338		-
4339		- return v4l2_event_subscribe(fh, sub, 0, NULL);
4340	7702	}
4341	7703
4342	7704	static const struct media_entity_operations rkcif_lvds_sd_media_ops = {
..	..	@@ -4349,10 +7711,10 @@
4349	7711	.get_fmt = rkcif_lvds_sd_get_fmt,
4350	7712	.set_selection = rkcif_lvds_sd_set_selection,
4351	7713	.get_selection = rkcif_lvds_sd_get_selection,
	7714	+ .get_mbus_config = rkcif_lvds_g_mbus_config,
4352	7715	};
4353	7716
4354	7717	static const struct v4l2_subdev_video_ops rkcif_lvds_sd_video_ops = {
4355		- .g_mbus_config = rkcif_lvds_g_mbus_config,
4356	7718	.s_stream = rkcif_lvds_sd_s_stream,
4357	7719	};
4358	7720
..	..	@@ -4390,10 +7752,12 @@
4390	7752	return 0;
4391	7753	}
4392	7754
4393		-static void rkcif_lvds_set_sof(struct rkcif_device *dev, u32 seq)
	7755	+static u32 rkcif_lvds_set_sof(struct rkcif_device *dev, u32 seq)
4394	7756	{
4395	7757	if (dev)
4396	7758	atomic_set(&dev->lvds_subdev.frm_sync_seq, seq);
	7759	+
	7760	+ return 0;
4397	7761	}
4398	7762
4399	7763	int rkcif_register_lvds_subdev(struct rkcif_device *dev)
..	..	@@ -4402,6 +7766,7 @@
4402	7766	struct rkcif_lvds_subdev *lvds_subdev = &dev->lvds_subdev;
4403	7767	struct v4l2_subdev *sd;
4404	7768	int ret;
	7769	+ int pad_num = 4;
4405	7770
4406	7771	memset(lvds_subdev, 0, sizeof(*lvds_subdev));
4407	7772	lvds_subdev->cifdev = dev;
..	..	@@ -4410,7 +7775,7 @@
4410	7775	v4l2_subdev_init(sd, &rkcif_lvds_sd_ops);
4411	7776	sd->flags \|= V4L2_SUBDEV_FL_HAS_DEVNODE \| V4L2_SUBDEV_FL_HAS_EVENTS;
4412	7777	sd->entity.ops = &rkcif_lvds_sd_media_ops;
4413		- if (dev->chip_id == CHIP_RV1126_CIF)
	7778	+ if (dev->chip_id != CHIP_RV1126_CIF_LITE)
4414	7779	snprintf(sd->name, sizeof(sd->name), "rkcif-lvds-subdev");
4415	7780	else
4416	7781	snprintf(sd->name, sizeof(sd->name), "rkcif-lite-lvds-subdev");
..	..	@@ -4421,6 +7786,13 @@
4421	7786	lvds_subdev->pads[RKCIF_LVDS_PAD_SRC_ID1].flags = MEDIA_PAD_FL_SOURCE;
4422	7787	lvds_subdev->pads[RKCIF_LVDS_PAD_SRC_ID2].flags = MEDIA_PAD_FL_SOURCE;
4423	7788	lvds_subdev->pads[RKCIF_LVDS_PAD_SRC_ID3].flags = MEDIA_PAD_FL_SOURCE;
	7789	+ if (dev->chip_id == CHIP_RV1106_CIF) {
	7790	+ lvds_subdev->pads[RKCIF_LVDS_PAD_SCL_ID0].flags = MEDIA_PAD_FL_SOURCE;
	7791	+ lvds_subdev->pads[RKCIF_LVDS_PAD_SCL_ID1].flags = MEDIA_PAD_FL_SOURCE;
	7792	+ lvds_subdev->pads[RKCIF_LVDS_PAD_SCL_ID2].flags = MEDIA_PAD_FL_SOURCE;
	7793	+ lvds_subdev->pads[RKCIF_LVDS_PAD_SCL_ID3].flags = MEDIA_PAD_FL_SOURCE;
	7794	+ pad_num = RKCIF_LVDS_PAD_MAX;
	7795	+ }
4424	7796
4425	7797	lvds_subdev->in_fmt.width = RKCIF_DEFAULT_WIDTH;
4426	7798	lvds_subdev->in_fmt.height = RKCIF_DEFAULT_HEIGHT;
..	..	@@ -4429,7 +7801,7 @@
4429	7801	lvds_subdev->crop.width = RKCIF_DEFAULT_WIDTH;
4430	7802	lvds_subdev->crop.height = RKCIF_DEFAULT_HEIGHT;
4431	7803
4432		- ret = media_entity_pads_init(&sd->entity, RKCIF_LVDS_PAD_MAX,
	7804	+ ret = media_entity_pads_init(&sd->entity, pad_num,
4433	7805	lvds_subdev->pads);
4434	7806	if (ret < 0)
4435	7807	return ret;
..	..	@@ -4481,10 +7853,12 @@
4481	7853	return 0;
4482	7854	}
4483	7855
4484		-static void rkcif_dvp_set_sof(struct rkcif_device *dev, u32 seq)
	7856	+static u32 rkcif_dvp_set_sof(struct rkcif_device *dev, u32 seq)
4485	7857	{
4486	7858	if (dev)
4487	7859	atomic_set(&dev->dvp_sof_subdev.frm_sync_seq, seq);
	7860	+
	7861	+ return 0;
4488	7862	}
4489	7863
4490	7864	static const struct v4l2_subdev_core_ops rkcif_dvp_sof_sd_core_ops = {
..	..	@@ -4537,28 +7911,6 @@
4537	7911	v4l2_device_unregister_subdev(sd);
4538	7912	}
4539	7913
4540		-
4541		-static void rkcif_vb_done_oneframe(struct rkcif_stream *stream,
4542		- struct vb2_v4l2_buffer *vb_done)
4543		-{
4544		- const struct cif_output_fmt *fmt = stream->cif_fmt_out;
4545		- u32 i;
4546		-
4547		- /* Dequeue a filled buffer */
4548		- for (i = 0; i < fmt->mplanes; i++) {
4549		- vb2_set_plane_payload(&vb_done->vb2_buf, i,
4550		- stream->pixm.plane_fmt[i].sizeimage);
4551		- }
4552		-
4553		- if (stream->cifdev->hdr.mode == NO_HDR)
4554		- vb_done->vb2_buf.timestamp = ktime_get_ns();
4555		-
4556		- vb2_buffer_done(&vb_done->vb2_buf, VB2_BUF_STATE_DONE);
4557		- v4l2_dbg(1, rkcif_debug, &stream->cifdev->v4l2_dev,
4558		- "stream[%d] vb done, index: %d, sequence %d\n", stream->id,
4559		- vb_done->vb2_buf.index, vb_done->sequence);
4560		-}
4561		-
4562	7914	void rkcif_irq_oneframe(struct rkcif_device *cif_dev)
4563	7915	{
4564	7916	/* TODO: xuhf-debug: add stream type */
..	..	@@ -4590,7 +7942,7 @@
4590	7942	}
4591	7943
4592	7944	if ((intstat & FRAME_END)) {
4593		- struct vb2_v4l2_buffer *vb_done = NULL;
	7945	+ struct rkcif_buffer *active_buf = NULL;
4594	7946
4595	7947	rkcif_write_register(cif_dev, CIF_REG_DVP_INTSTAT,
4596	7948	FRAME_END_CLR);
..	..	@@ -4623,11 +7975,11 @@
4623	7975	if (frmid % 2 != 0) {
4624	7976	stream->frame_phase = CIF_CSI_FRAME0_READY;
4625	7977	if (stream->curr_buf)
4626		- vb_done = &stream->curr_buf->vb;
	7978	+ active_buf = stream->curr_buf;
4627	7979	} else {
4628	7980	stream->frame_phase = CIF_CSI_FRAME1_READY;
4629	7981	if (stream->next_buf)
4630		- vb_done = &stream->next_buf->vb;
	7982	+ active_buf = stream->next_buf;
4631	7983	}
4632	7984
4633	7985	/* In one-frame mode:
..	..	@@ -4640,46 +7992,28 @@
4640	7992	ret = rkcif_assign_new_buffer_oneframe(stream,
4641	7993	RKCIF_YUV_ADDR_STATE_UPDATE);
4642	7994
4643		- if (vb_done && (!ret)) {
4644		- vb_done->sequence = stream->frame_idx;
4645		- rkcif_vb_done_oneframe(stream, vb_done);
	7995	+ if (active_buf && (!ret)) {
	7996	+ active_buf->vb.sequence = stream->frame_idx - 1;
	7997	+ rkcif_vb_done_tasklet(stream, active_buf);
4646	7998	}
4647	7999
4648		- stream->frame_idx++;
4649		- cif_dev->irq_stats.all_frm_end_cnt++;
	8000	+ cif_dev->irq_stats.frm_end_cnt[stream->id]++;
4650	8001	}
4651	8002	}
4652	8003
4653	8004	static int rkcif_csi_g_mipi_id(struct v4l2_device *v4l2_dev,
4654		- unsigned int intstat)
	8005	+ unsigned int intstat)
4655	8006	{
4656		- if (intstat & CSI_FRAME_END_ID0) {
4657		- if ((intstat & CSI_FRAME_END_ID0) ==
4658		- CSI_FRAME_END_ID0)
4659		- v4l2_warn(v4l2_dev, "frame0/1 trigger simultaneously in ID0\n");
	8007	+ if (intstat & CSI_FRAME_END_ID0)
4660	8008	return RKCIF_STREAM_MIPI_ID0;
4661		- }
4662	8009
4663		- if (intstat & CSI_FRAME_END_ID1) {
4664		- if ((intstat & CSI_FRAME_END_ID1) ==
4665		- CSI_FRAME_END_ID1)
4666		- v4l2_warn(v4l2_dev, "frame0/1 trigger simultaneously in ID1\n");
	8010	+ if (intstat & CSI_FRAME_END_ID1)
4667	8011	return RKCIF_STREAM_MIPI_ID1;
4668		- }
4669	8012
4670		- if (intstat & CSI_FRAME_END_ID2) {
4671		- if ((intstat & CSI_FRAME_END_ID2) ==
4672		- CSI_FRAME_END_ID2)
4673		- v4l2_warn(v4l2_dev, "frame0/1 trigger simultaneously in ID2\n");
	8013	+ if (intstat & CSI_FRAME_END_ID2)
4674	8014	return RKCIF_STREAM_MIPI_ID2;
4675		- }
4676		-
4677		- if (intstat & CSI_FRAME_END_ID3) {
4678		- if ((intstat & CSI_FRAME_END_ID3) ==
4679		- CSI_FRAME_END_ID3)
4680		- v4l2_warn(v4l2_dev, "frame0/1 trigger simultaneously in ID3\n");
	8015	+ if (intstat & CSI_FRAME_END_ID3)
4681	8016	return RKCIF_STREAM_MIPI_ID3;
4682		- }
4683	8017
4684	8018	return -EINVAL;
4685	8019	}
..	..	@@ -4688,38 +8022,42 @@
4688	8022	u32 *intstat, u32 frm_stat)
4689	8023	{
4690	8024	if (*intstat & DVP_FRAME_END_ID0) {
4691		- if ((frm_stat & DVP_CHANNEL0_FRM_READ) ==
4692		- DVP_CHANNEL0_FRM_READ)
4693		- v4l2_warn(v4l2_dev, "frame0/1 trigger simultaneously in DVP ID0\n");
4694		-
4695	8025	*intstat &= ~DVP_FRAME_END_ID0;
4696	8026	return RKCIF_STREAM_MIPI_ID0;
4697	8027	}
4698	8028
4699	8029	if (*intstat & DVP_FRAME_END_ID1) {
4700		- if ((frm_stat & DVP_CHANNEL1_FRM_READ) ==
4701		- DVP_CHANNEL1_FRM_READ)
4702		- v4l2_warn(v4l2_dev, "frame0/1 trigger simultaneously in DVP ID1\n");
4703		-
4704	8030	*intstat &= ~DVP_FRAME_END_ID1;
4705	8031	return RKCIF_STREAM_MIPI_ID1;
4706	8032	}
4707	8033
4708	8034	if (*intstat & DVP_FRAME_END_ID2) {
4709		- if ((frm_stat & DVP_CHANNEL2_FRM_READ) ==
4710		- DVP_CHANNEL2_FRM_READ)
4711		- v4l2_warn(v4l2_dev, "frame0/1 trigger simultaneously in DVP ID2\n");
4712	8035	*intstat &= ~DVP_FRAME_END_ID2;
4713	8036	return RKCIF_STREAM_MIPI_ID2;
4714	8037	}
4715	8038
4716	8039	if (*intstat & DVP_FRAME_END_ID3) {
4717		- if ((frm_stat & DVP_CHANNEL3_FRM_READ) ==
4718		- DVP_CHANNEL3_FRM_READ)
4719		- v4l2_warn(v4l2_dev, "frame0/1 trigger simultaneously in DVP ID3\n");
4720	8040	*intstat &= ~DVP_FRAME_END_ID3;
4721	8041	return RKCIF_STREAM_MIPI_ID3;
4722	8042	}
	8043	+
	8044	+ return -EINVAL;
	8045	+}
	8046	+
	8047	+static int rkcif_dvp_g_ch_id_by_fe(struct v4l2_device *v4l2_dev,
	8048	+ u32 intstat)
	8049	+{
	8050	+ if (intstat & DVP_ALL_END_ID0)
	8051	+ return RKCIF_STREAM_MIPI_ID0;
	8052	+
	8053	+ if (intstat & DVP_ALL_END_ID1)
	8054	+ return RKCIF_STREAM_MIPI_ID1;
	8055	+
	8056	+ if (intstat & DVP_ALL_END_ID2)
	8057	+ return RKCIF_STREAM_MIPI_ID2;
	8058	+
	8059	+ if (intstat & DVP_ALL_END_ID3)
	8060	+ return RKCIF_STREAM_MIPI_ID3;
4723	8061
4724	8062	return -EINVAL;
4725	8063	}
..	..	@@ -4730,7 +8068,6 @@
4730	8068	struct rkcif_device,
4731	8069	reset_watchdog_timer);
4732	8070	struct rkcif_stream *stream = &dev->stream[RKCIF_STREAM_MIPI_ID0];
4733		- struct rkcif_hw_timer *hw_timer = &dev->hw_dev->hw_timer;
4734	8071	bool is_triggered = false, is_assign_triggered = false, is_first_err = false;
4735	8072	unsigned long flags;
4736	8073	u64 cur_time, diff_time;
..	..	@@ -4741,7 +8078,7 @@
4741	8078	timer->csi2_err_cnt_odd != 0) {
4742	8079	timer->csi2_err_cnt_odd = 0;
4743	8080	timer->csi2_err_cnt_even = 0;
4744		- hw_timer->reset_src = RKCIF_RESET_SRC_ERR_CSI2;
	8081	+ timer->reset_src = RKCIF_RESET_SRC_ERR_CSI2;
4745	8082	timer->csi2_err_triggered_cnt++;
4746	8083	if (timer->csi2_err_triggered_cnt == 1) {
4747	8084	is_first_err = true;
..	..	@@ -4760,7 +8097,7 @@
4760	8097	cur_time = ktime_get_ns();
4761	8098	diff_time = cur_time - timer->csi2_first_err_timestamp;
4762	8099	diff_time = div_u64(diff_time, 1000000);
4763		- if (diff_time >= hw_timer->err_time_interval) {
	8100	+ if (diff_time >= timer->err_time_interval) {
4764	8101	is_triggered = true;
4765	8102	v4l2_info(&dev->v4l2_dev, "trigger reset for time out of csi err\n");
4766	8103	goto end_judge;
..	..	@@ -4780,19 +8117,10 @@
4780	8117	* when fs cnt is beyond 2, it indicates that frame end is not coming,
4781	8118	* or fs and fe had been not paired.
4782	8119	*/
4783		- if (hw_timer->monitor_mode != RKCIF_MONITOR_MODE_HOTPLUG &&
4784		- (stream->is_fs_fe_not_paired \|\|
4785		- stream->fs_cnt_in_single_frame > RKCIF_FS_DETECTED_NUM)) {
	8120	+ if (stream->is_fs_fe_not_paired \|\|
	8121	+ stream->fs_cnt_in_single_frame > RKCIF_FS_DETECTED_NUM) {
4786	8122	is_triggered = true;
4787	8123	v4l2_info(&dev->v4l2_dev, "reset for fs & fe not paired\n");
4788		- }
4789		- if (dev->irq_stats.csi_bwidth_lack_cnt) {
4790		- is_triggered = true;
4791		- dev->irq_stats.csi_bwidth_lack_cnt = 0;
4792		- }
4793		- if (dev->irq_stats.csi_overflow_cnt) {
4794		- is_triggered = true;
4795		- dev->irq_stats.csi_overflow_cnt = 0;
4796	8124	}
4797	8125	end_judge:
4798	8126	spin_unlock_irqrestore(&timer->csi2_err_lock, flags);
..	..	@@ -4800,7 +8128,30 @@
4800	8128	return is_triggered;
4801	8129	}
4802	8130
4803		-static s32 rkcif_get_sensor_vblank(struct rkcif_device *dev)
	8131	+static bool rkcif_is_triggered_monitoring(struct rkcif_device *dev)
	8132	+{
	8133	+ struct rkcif_timer *timer = &dev->reset_watchdog_timer;
	8134	+ struct rkcif_stream *stream = &dev->stream[RKCIF_STREAM_MIPI_ID0];
	8135	+ bool ret = false;
	8136	+
	8137	+ if (timer->monitor_mode == RKCIF_MONITOR_MODE_IDLE)
	8138	+ ret = false;
	8139	+
	8140	+ if (timer->monitor_mode == RKCIF_MONITOR_MODE_CONTINUE \|\|
	8141	+ timer->monitor_mode == RKCIF_MONITOR_MODE_HOTPLUG) {
	8142	+ if (stream->frame_idx >= timer->triggered_frame_num)
	8143	+ ret = true;
	8144	+ }
	8145	+
	8146	+ if (timer->monitor_mode == RKCIF_MONITOR_MODE_TRIGGER) {
	8147	+ timer->is_csi2_err_occurred = rkcif_is_csi2_err_trigger_reset(timer);
	8148	+ ret = timer->is_csi2_err_occurred;
	8149	+ }
	8150	+
	8151	+ return ret;
	8152	+}
	8153	+
	8154	+s32 rkcif_get_sensor_vblank(struct rkcif_device *dev)
4804	8155	{
4805	8156	struct rkcif_sensor_info *terminal_sensor = &dev->terminal_sensor;
4806	8157	struct v4l2_subdev *sd = terminal_sensor->sd;
..	..	@@ -4817,7 +8168,7 @@
4817	8168	return 0;
4818	8169	}
4819	8170
4820		-static s32 rkcif_get_sensor_vblank_def(struct rkcif_device *dev)
	8171	+s32 rkcif_get_sensor_vblank_def(struct rkcif_device *dev)
4821	8172	{
4822	8173	struct rkcif_sensor_info *terminal_sensor = &dev->terminal_sensor;
4823	8174	struct v4l2_subdev *sd = terminal_sensor->sd;
..	..	@@ -4843,7 +8194,7 @@
4843	8194	const struct cif_output_fmt *fmt;
4844	8195	u32 fourcc;
4845	8196
4846		- fmt = find_output_fmt(stream, stream->pixm.pixelformat);
	8197	+ fmt = rkcif_find_output_fmt(stream, stream->pixm.pixelformat);
4847	8198	if (!fmt) {
4848	8199	v4l2_err(&dev->v4l2_dev, "can not find output format: 0x%x",
4849	8200	stream->pixm.pixelformat);
..	..	@@ -4859,13 +8210,14 @@
4859	8210	* writing of ddr, aliged with 256
4860	8211	*/
4861	8212	if (fmt->fmt_type == CIF_FMT_TYPE_RAW && stream->is_compact &&
4862		- fmt->csi_fmt_val != CSI_WRDDR_TYPE_RGB888) {
	8213	+ fmt->csi_fmt_val != CSI_WRDDR_TYPE_RGB888 &&
	8214	+ fmt->csi_fmt_val != CSI_WRDDR_TYPE_RGB565) {
4863	8215	crop_vwidth = ALIGN(raw_width fmt->raw_bpp / 8, 256);
4864	8216	} else {
4865	8217	crop_vwidth = ALIGN(raw_width fmt->bpp[0] / 8, 8);
4866	8218	}
4867	8219
4868		- if (channel->fmt_val == CSI_WRDDR_TYPE_RGB888)
	8220	+ if (channel->fmt_val == CSI_WRDDR_TYPE_RGB888 \|\| channel->fmt_val == CSI_WRDDR_TYPE_RGB565)
4869	8221	crop_width = raw_width fmt->bpp[0] / 8;
4870	8222	/*
4871	8223	* rk cif don't support output yuyv fmt data
..	..	@@ -4893,12 +8245,15 @@
4893	8245	return;
4894	8246
4895	8247	mbus = &cif_dev->active_sensor->mbus;
4896		- if (mbus->type == V4L2_MBUS_CSI2 \|\|
	8248	+ if (mbus->type == V4L2_MBUS_CSI2_DPHY \|\|
	8249	+ mbus->type == V4L2_MBUS_CSI2_CPHY \|\|
4897	8250	mbus->type == V4L2_MBUS_CCP2) {
4898	8251	struct csi_channel_info *channel = &cif_dev->channels[stream->id];
4899	8252
4900	8253	if (channel->fmt_val == CSI_WRDDR_TYPE_RGB888)
4901	8254	crop_x = 3 * stream->crop[CROP_SRC_ACT].left;
	8255	+ else if (channel->fmt_val == CSI_WRDDR_TYPE_RGB565)
	8256	+ crop_x = 2 * stream->crop[CROP_SRC_ACT].left;
4902	8257	else
4903	8258	crop_x = stream->crop[CROP_SRC_ACT].left;
4904	8259
..	..	@@ -4940,15 +8295,8 @@
4940	8295	crop_y << CIF_CROP_Y_SHIFT \| crop_x);
4941	8296
4942	8297	if (stream->cif_fmt_in->fmt_type == CIF_FMT_TYPE_RAW) {
4943		- fmt = find_output_fmt(stream, stream->pixm.pixelformat);
4944		- if (fmt->fourcc == V4L2_PIX_FMT_GREY \|\|
4945		- fmt->fourcc == V4L2_PIX_FMT_SRGGB8 \|\|
4946		- fmt->fourcc == V4L2_PIX_FMT_SGRBG8 \|\|
4947		- fmt->fourcc == V4L2_PIX_FMT_SGBRG8 \|\|
4948		- fmt->fourcc == V4L2_PIX_FMT_SBGGR8)
4949		- crop_vwidth = ALIGN(raw_width * fmt->raw_bpp / 8, 256);
4950		- else
4951		- crop_vwidth = raw_width * rkcif_cal_raw_vir_line_ratio(stream, fmt);
	8298	+ fmt = rkcif_find_output_fmt(stream, stream->pixm.pixelformat);
	8299	+ crop_vwidth = raw_width * rkcif_cal_raw_vir_line_ratio(stream, fmt);
4952	8300	}
4953	8301	rkcif_write_register(cif_dev, CIF_REG_DVP_VIR_LINE_WIDTH, crop_vwidth);
4954	8302
..	..	@@ -4959,41 +8307,94 @@
4959	8307	stream->crop_dyn_en = false;
4960	8308	}
4961	8309
4962		-void rkcif_monitor_reset_event(struct rkcif_hw *hw)
	8310	+static void rkcif_monitor_reset_event(struct rkcif_device *dev)
4963	8311	{
4964		- struct rkcif_hw_timer *hw_timer = &hw->hw_timer;
4965		- struct rkcif_timer *timer = NULL;
4966		- struct rkcif_device *cif_dev = NULL;
4967	8312	struct rkcif_stream *stream = NULL;
4968		- unsigned long flags;
4969		- int i = 0, j = 0;
	8313	+ struct rkcif_timer *timer = &dev->reset_watchdog_timer;
	8314	+ unsigned int cycle = 0;
	8315	+ u64 fps, timestamp0, timestamp1;
	8316	+ unsigned long flags, fps_flags;
	8317	+ int i = 0;
4970	8318
4971		- if (hw_timer->is_running)
	8319	+ if (timer->is_running)
4972	8320	return;
4973	8321
4974		- if (hw_timer->monitor_mode == RKCIF_MONITOR_MODE_IDLE)
	8322	+ if (timer->monitor_mode == RKCIF_MONITOR_MODE_IDLE)
4975	8323	return;
4976	8324
4977		- spin_lock_irqsave(&hw_timer->timer_lock, flags);
4978		- hw_timer->is_running = true;
4979		- for (j = 0; i < hw->dev_num; j++) {
4980		- cif_dev = hw->cif_dev[i];
4981		- timer = &cif_dev->reset_watchdog_timer;
4982		- for (i = 0; i < cif_dev->num_channels; i++) {
4983		- stream = &cif_dev->stream[i];
4984		- if (stream->state == RKCIF_STATE_STREAMING)
4985		- timer->last_buf_wakeup_cnt[i] = stream->frame_idx;
4986		- }
	8325	+ for (i = 0; i < RKCIF_MAX_STREAM_MIPI; i++) {
	8326	+ stream = &dev->stream[i];
	8327	+ if (stream->state == RKCIF_STATE_STREAMING)
	8328	+ break;
4987	8329	}
4988		- hw_timer->cycle_jif = msecs_to_jiffies(hw_timer->monitor_cycle);
4989		- hw_timer->timer.expires = jiffies + hw_timer->cycle_jif;
4990		- mod_timer(&hw_timer->timer, hw_timer->timer.expires);
4991	8330
4992		- spin_unlock_irqrestore(&hw_timer->timer_lock, flags);
	8331	+ if (i >= RKCIF_MAX_STREAM_MIPI)
	8332	+ return;
4993	8333
4994		- v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev,
4995		- "start monitor timer, monitor cycle %d\n",
4996		- hw_timer->monitor_cycle);
	8334	+ timer->is_triggered = rkcif_is_triggered_monitoring(dev);
	8335	+
	8336	+ if (timer->is_triggered) {
	8337	+ struct v4l2_rect *raw_rect = &dev->terminal_sensor.raw_rect;
	8338	+ enum rkcif_monitor_mode mode;
	8339	+ s32 vblank = 0;
	8340	+ u32 vts = 0;
	8341	+ u64 numerator = 0;
	8342	+ u64 denominator = 0;
	8343	+
	8344	+ if (stream->frame_idx > 2) {
	8345	+ spin_lock_irqsave(&stream->fps_lock, fps_flags);
	8346	+ timestamp0 = stream->fps_stats.frm0_timestamp;
	8347	+ timestamp1 = stream->fps_stats.frm1_timestamp;
	8348	+ spin_unlock_irqrestore(&stream->fps_lock, fps_flags);
	8349	+
	8350	+ fps = timestamp0 > timestamp1 ?
	8351	+ timestamp0 - timestamp1 : timestamp1 - timestamp0;
	8352	+ fps = div_u64(fps, 1000);
	8353	+ } else {
	8354	+ numerator = dev->terminal_sensor.fi.interval.numerator;
	8355	+ denominator = dev->terminal_sensor.fi.interval.denominator;
	8356	+ fps = div_u64(1000000 * numerator, denominator);
	8357	+ }
	8358	+ spin_lock_irqsave(&timer->timer_lock, flags);
	8359	+
	8360	+ timer->frame_end_cycle_us = fps;
	8361	+
	8362	+ vblank = rkcif_get_sensor_vblank(dev);
	8363	+ timer->raw_height = raw_rect->height;
	8364	+ vts = timer->raw_height + vblank;
	8365	+ timer->vts = vts;
	8366	+
	8367	+ timer->line_end_cycle = div_u64(timer->frame_end_cycle_us, timer->vts);
	8368	+ fps = div_u64(timer->frame_end_cycle_us, 1000);
	8369	+ cycle = fps * timer->frm_num_of_monitor_cycle;
	8370	+ timer->cycle = msecs_to_jiffies(cycle);
	8371	+
	8372	+ timer->run_cnt = 0;
	8373	+ timer->is_running = true;
	8374	+ timer->is_buf_stop_update = false;
	8375	+ for (i = 0; i < dev->num_channels; i++) {
	8376	+ stream = &dev->stream[i];
	8377	+ if (stream->state == RKCIF_STATE_STREAMING)
	8378	+ timer->last_buf_wakeup_cnt[i] = stream->buf_wake_up_cnt;
	8379	+ }
	8380	+ /* in trigger mode, monitoring count is fps */
	8381	+ mode = timer->monitor_mode;
	8382	+ if (mode == RKCIF_MONITOR_MODE_CONTINUE \|\|
	8383	+ mode == RKCIF_MONITOR_MODE_HOTPLUG)
	8384	+ timer->max_run_cnt = 0xffffffff - CIF_TIMEOUT_FRAME_NUM;
	8385	+ else
	8386	+ timer->max_run_cnt = div_u64(1000, fps) * 1;
	8387	+
	8388	+ timer->timer.expires = jiffies + timer->cycle;
	8389	+ mod_timer(&timer->timer, timer->timer.expires);
	8390	+
	8391	+ spin_unlock_irqrestore(&timer->timer_lock, flags);
	8392	+
	8393	+ v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev,
	8394	+ "%s:mode:%d, raw height:%d,vblank:%d, cycle:%ld, fps:%llu\n",
	8395	+ __func__, timer->monitor_mode, raw_rect->height,
	8396	+ vblank, timer->cycle, div_u64(1000, fps));
	8397	+ }
4997	8398	}
4998	8399
4999	8400	static void rkcif_rdbk_frame_end(struct rkcif_stream *stream)
..	..	@@ -5003,13 +8404,15 @@
5003	8404	u32 denominator, numerator;
5004	8405	u64 l_ts, m_ts, s_ts, time = 30000000LL;
5005	8406	int ret, fps = -1;
	8407	+ int i = 0;
	8408	+ unsigned long flags;
5006	8409
5007		- if (dev->hdr.mode == HDR_X2) {
	8410	+ if (dev->hdr.hdr_mode == HDR_X2) {
5008	8411	if (stream->id != RKCIF_STREAM_MIPI_ID1 \|\|
5009	8412	dev->stream[RKCIF_STREAM_MIPI_ID0].state != RKCIF_STATE_STREAMING \|\|
5010	8413	dev->stream[RKCIF_STREAM_MIPI_ID1].state != RKCIF_STATE_STREAMING)
5011	8414	return;
5012		- } else if (dev->hdr.mode == HDR_X3) {
	8415	+ } else if (dev->hdr.hdr_mode == HDR_X3) {
5013	8416	if (stream->id != RKCIF_STREAM_MIPI_ID2 \|\|
5014	8417	dev->stream[RKCIF_STREAM_MIPI_ID0].state != RKCIF_STATE_STREAMING \|\|
5015	8418	dev->stream[RKCIF_STREAM_MIPI_ID1].state != RKCIF_STATE_STREAMING \|\|
..	..	@@ -5022,13 +8425,13 @@
5022	8425	if (denominator && numerator)
5023	8426	time = numerator * 1000 / denominator * 1000 * 1000;
5024	8427
5025		- if (dev->hdr.mode == HDR_X3) {
	8428	+ if (dev->hdr.hdr_mode == HDR_X3) {
5026	8429	if (dev->rdbk_buf[RDBK_L] &&
5027	8430	dev->rdbk_buf[RDBK_M] &&
5028	8431	dev->rdbk_buf[RDBK_S]) {
5029		- l_ts = dev->rdbk_buf[RDBK_L]->vb.vb2_buf.timestamp;
5030		- m_ts = dev->rdbk_buf[RDBK_M]->vb.vb2_buf.timestamp;
5031		- s_ts = dev->rdbk_buf[RDBK_S]->vb.vb2_buf.timestamp;
	8432	+ l_ts = dev->rdbk_buf[RDBK_L]->fe_timestamp;
	8433	+ m_ts = dev->rdbk_buf[RDBK_M]->fe_timestamp;
	8434	+ s_ts = dev->rdbk_buf[RDBK_S]->fe_timestamp;
5032	8435
5033	8436	if (m_ts < l_ts \|\| s_ts < m_ts) {
5034	8437	v4l2_err(&dev->v4l2_dev,
..	..	@@ -5058,14 +8461,25 @@
5058	8461	goto RDBK_FRM_UNMATCH;
5059	8462	}
5060	8463	}
5061		- dev->rdbk_buf[RDBK_L]->vb.sequence = dev->rdbk_buf[RDBK_S]->vb.sequence;
5062		- dev->rdbk_buf[RDBK_M]->vb.sequence = dev->rdbk_buf[RDBK_S]->vb.sequence;
5063		- rkcif_vb_done_oneframe(&dev->stream[RKCIF_STREAM_MIPI_ID0],
5064		- &dev->rdbk_buf[RDBK_L]->vb);
5065		- rkcif_vb_done_oneframe(&dev->stream[RKCIF_STREAM_MIPI_ID1],
5066		- &dev->rdbk_buf[RDBK_M]->vb);
5067		- rkcif_vb_done_oneframe(&dev->stream[RKCIF_STREAM_MIPI_ID2],
5068		- &dev->rdbk_buf[RDBK_S]->vb);
	8464	+ dev->rdbk_buf[RDBK_M]->vb.sequence = dev->rdbk_buf[RDBK_L]->vb.sequence;
	8465	+ dev->rdbk_buf[RDBK_S]->vb.sequence = dev->rdbk_buf[RDBK_L]->vb.sequence;
	8466	+ if (dev->is_support_tools &&
	8467	+ dev->stream[RKCIF_STREAM_MIPI_ID0].tools_vdev->state == RKCIF_STATE_STREAMING &&
	8468	+ dev->stream[RKCIF_STREAM_MIPI_ID1].tools_vdev->state == RKCIF_STATE_STREAMING &&
	8469	+ dev->stream[RKCIF_STREAM_MIPI_ID2].tools_vdev->state == RKCIF_STATE_STREAMING) {
	8470	+ for (i = 0; i < 3; i++) {
	8471	+ spin_lock_irqsave(&dev->stream[i].tools_vdev->vbq_lock, flags);
	8472	+ list_add_tail(&dev->rdbk_buf[i]->queue,
	8473	+ &dev->stream[i].tools_vdev->buf_done_head);
	8474	+ if (!work_busy(&dev->stream[i].tools_vdev->work))
	8475	+ schedule_work(&dev->stream[i].tools_vdev->work);
	8476	+ spin_unlock_irqrestore(&dev->stream[i].tools_vdev->vbq_lock, flags);
	8477	+ }
	8478	+ } else {
	8479	+ rkcif_vb_done_tasklet(&dev->stream[RKCIF_STREAM_MIPI_ID0], dev->rdbk_buf[RDBK_L]);
	8480	+ rkcif_vb_done_tasklet(&dev->stream[RKCIF_STREAM_MIPI_ID1], dev->rdbk_buf[RDBK_M]);
	8481	+ rkcif_vb_done_tasklet(&dev->stream[RKCIF_STREAM_MIPI_ID2], dev->rdbk_buf[RDBK_S]);
	8482	+ }
5069	8483	} else {
5070	8484	if (!dev->rdbk_buf[RDBK_L])
5071	8485	v4l2_err(&dev->v4l2_dev, "lost long frames\n");
..	..	@@ -5075,10 +8489,10 @@
5075	8489	v4l2_err(&dev->v4l2_dev, "lost short frames\n");
5076	8490	goto RDBK_FRM_UNMATCH;
5077	8491	}
5078		- } else if (dev->hdr.mode == HDR_X2) {
	8492	+ } else if (dev->hdr.hdr_mode == HDR_X2) {
5079	8493	if (dev->rdbk_buf[RDBK_L] && dev->rdbk_buf[RDBK_M]) {
5080		- l_ts = dev->rdbk_buf[RDBK_L]->vb.vb2_buf.timestamp;
5081		- s_ts = dev->rdbk_buf[RDBK_M]->vb.vb2_buf.timestamp;
	8494	+ l_ts = dev->rdbk_buf[RDBK_L]->fe_timestamp;
	8495	+ s_ts = dev->rdbk_buf[RDBK_M]->fe_timestamp;
5082	8496
5083	8497	if (s_ts < l_ts) {
5084	8498	v4l2_err(&dev->v4l2_dev,
..	..	@@ -5107,11 +8521,22 @@
5107	8521	goto RDBK_FRM_UNMATCH;
5108	8522	}
5109	8523	}
5110		- dev->rdbk_buf[RDBK_L]->vb.sequence = dev->rdbk_buf[RDBK_M]->vb.sequence;
5111		- rkcif_vb_done_oneframe(&dev->stream[RKCIF_STREAM_MIPI_ID0],
5112		- &dev->rdbk_buf[RDBK_L]->vb);
5113		- rkcif_vb_done_oneframe(&dev->stream[RKCIF_STREAM_MIPI_ID1],
5114		- &dev->rdbk_buf[RDBK_M]->vb);
	8524	+ dev->rdbk_buf[RDBK_M]->vb.sequence = dev->rdbk_buf[RDBK_L]->vb.sequence;
	8525	+ if (dev->is_support_tools &&
	8526	+ dev->stream[RKCIF_STREAM_MIPI_ID0].tools_vdev->state == RKCIF_STATE_STREAMING &&
	8527	+ dev->stream[RKCIF_STREAM_MIPI_ID1].tools_vdev->state == RKCIF_STATE_STREAMING) {
	8528	+ for (i = 0; i < 2; i++) {
	8529	+ spin_lock_irqsave(&dev->stream[i].tools_vdev->vbq_lock, flags);
	8530	+ list_add_tail(&dev->rdbk_buf[i]->queue,
	8531	+ &dev->stream[i].tools_vdev->buf_done_head);
	8532	+ if (!work_busy(&dev->stream[i].tools_vdev->work))
	8533	+ schedule_work(&dev->stream[i].tools_vdev->work);
	8534	+ spin_unlock_irqrestore(&dev->stream[i].tools_vdev->vbq_lock, flags);
	8535	+ }
	8536	+ } else {
	8537	+ rkcif_vb_done_tasklet(&dev->stream[RKCIF_STREAM_MIPI_ID0], dev->rdbk_buf[RDBK_L]);
	8538	+ rkcif_vb_done_tasklet(&dev->stream[RKCIF_STREAM_MIPI_ID1], dev->rdbk_buf[RDBK_M]);
	8539	+ }
5115	8540	} else {
5116	8541	if (!dev->rdbk_buf[RDBK_L])
5117	8542	v4l2_err(&dev->v4l2_dev, "lost long frames\n");
..	..	@@ -5119,8 +8544,6 @@
5119	8544	v4l2_err(&dev->v4l2_dev, "lost short frames\n");
5120	8545	goto RDBK_FRM_UNMATCH;
5121	8546	}
5122		- } else {
5123		- rkcif_vb_done_oneframe(stream, &dev->rdbk_buf[RDBK_S]->vb);
5124	8547	}
5125	8548
5126	8549	dev->rdbk_buf[RDBK_L] = NULL;
..	..	@@ -5147,10 +8570,26 @@
5147	8570	dev->rdbk_buf[RDBK_S] = NULL;
5148	8571	}
5149	8572
	8573	+static void rkcif_buf_done_with_tools(struct rkcif_stream *stream,
	8574	+ struct rkcif_buffer *active_buf)
	8575	+{
	8576	+ unsigned long flags;
	8577	+
	8578	+ spin_lock_irqsave(&stream->tools_vdev->vbq_lock, flags);
	8579	+ if (stream->tools_vdev->state == RKCIF_STATE_STREAMING) {
	8580	+ list_add_tail(&active_buf->queue, &stream->tools_vdev->buf_done_head);
	8581	+ if (!work_busy(&stream->tools_vdev->work))
	8582	+ schedule_work(&stream->tools_vdev->work);
	8583	+ } else {
	8584	+ rkcif_vb_done_tasklet(stream, active_buf);
	8585	+ }
	8586	+ spin_unlock_irqrestore(&stream->tools_vdev->vbq_lock, flags);
	8587	+}
	8588	+
5150	8589	static void rkcif_buf_done_prepare(struct rkcif_stream *stream,
5151		- struct rkcif_buffer *active_buf,
5152		- int mipi_id,
5153		- u32 mode)
	8590	+ struct rkcif_buffer *active_buf,
	8591	+ int mipi_id,
	8592	+ u32 mode)
5154	8593	{
5155	8594	unsigned long flags;
5156	8595	struct vb2_v4l2_buffer *vb_done = NULL;
..	..	@@ -5158,8 +8597,13 @@
5158	8597
5159	8598	if (active_buf) {
5160	8599	vb_done = &active_buf->vb;
5161		- vb_done->vb2_buf.timestamp = ktime_get_ns();
5162		- vb_done->sequence = stream->frame_idx;
	8600	+ if (cif_dev->chip_id < CHIP_RK3588_CIF &&
	8601	+ cif_dev->active_sensor->mbus.type == V4L2_MBUS_BT656)
	8602	+ vb_done->vb2_buf.timestamp = stream->readout.fe_timestamp;
	8603	+ else
	8604	+ vb_done->vb2_buf.timestamp = stream->readout.fs_timestamp;
	8605	+ vb_done->sequence = stream->frame_idx - 1;
	8606	+ active_buf->fe_timestamp = ktime_get_ns();
5163	8607	if (stream->is_line_wake_up) {
5164	8608	spin_lock_irqsave(&stream->fps_lock, flags);
5165	8609	if (mode)
..	..	@@ -5173,13 +8617,22 @@
5173	8617	vb_done->sequence /= 2;
5174	8618	}
5175	8619
5176		- if (cif_dev->hdr.mode == NO_HDR) {
	8620	+ if (cif_dev->hdr.hdr_mode == NO_HDR \|\| cif_dev->hdr.hdr_mode == HDR_COMPR) {
5177	8621	if (stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED) {
5178		- if (stream->frame_phase == CIF_CSI_FRAME1_READY && active_buf)
5179		- rkcif_vb_done_oneframe(stream, vb_done);
	8622	+ if (stream->frame_phase == CIF_CSI_FRAME1_READY && active_buf) {
	8623	+
	8624	+ if (cif_dev->is_support_tools && stream->tools_vdev)
	8625	+ rkcif_buf_done_with_tools(stream, active_buf);
	8626	+ else
	8627	+ rkcif_vb_done_tasklet(stream, active_buf);
	8628	+ }
5180	8629	} else {
5181		- if (active_buf)
5182		- rkcif_vb_done_oneframe(stream, vb_done);
	8630	+ if (active_buf) {
	8631	+ if (cif_dev->is_support_tools && stream->tools_vdev)
	8632	+ rkcif_buf_done_with_tools(stream, active_buf);
	8633	+ else
	8634	+ rkcif_vb_done_tasklet(stream, active_buf);
	8635	+ }
5183	8636	}
5184	8637	} else {
5185	8638	if (cif_dev->is_start_hdr) {
..	..	@@ -5188,11 +8641,12 @@
5188	8641	if (cif_dev->rdbk_buf[RDBK_L]) {
5189	8642	v4l2_err(&cif_dev->v4l2_dev,
5190	8643	"multiple long data in %s frame,frm_idx:%d,state:0x%x\n",
5191		- cif_dev->hdr.mode == HDR_X2 ? "hdr_x2" : "hdr_x3",
	8644	+ cif_dev->hdr.hdr_mode == HDR_X2 ? "hdr_x2" : "hdr_x3",
5192	8645	stream->frame_idx,
5193	8646	cif_dev->rdbk_buf[RDBK_L]->vb.vb2_buf.state);
5194	8647	cif_dev->rdbk_buf[RDBK_L]->vb.vb2_buf.state = VB2_BUF_STATE_ACTIVE;
5195	8648	rkcif_buf_queue(&cif_dev->rdbk_buf[RDBK_L]->vb.vb2_buf);
	8649	+ cif_dev->rdbk_buf[RDBK_L] = NULL;
5196	8650	}
5197	8651	if (active_buf)
5198	8652	cif_dev->rdbk_buf[RDBK_L] = active_buf;
..	..	@@ -5200,29 +8654,31 @@
5200	8654	if (cif_dev->rdbk_buf[RDBK_M]) {
5201	8655	v4l2_err(&cif_dev->v4l2_dev,
5202	8656	"multiple %s frame,frm_idx:%d,state:0x%x\n",
5203		- cif_dev->hdr.mode == HDR_X2 ? "short data in hdr_x2" : "medium data in hdr_x3",
	8657	+ cif_dev->hdr.hdr_mode == HDR_X2 ? "short data in hdr_x2" : "medium data in hdr_x3",
5204	8658	stream->frame_idx,
5205	8659	cif_dev->rdbk_buf[RDBK_M]->vb.vb2_buf.state);
5206	8660	cif_dev->rdbk_buf[RDBK_M]->vb.vb2_buf.state = VB2_BUF_STATE_ACTIVE;
5207	8661	rkcif_buf_queue(&cif_dev->rdbk_buf[RDBK_M]->vb.vb2_buf);
	8662	+ cif_dev->rdbk_buf[RDBK_M] = NULL;
5208	8663	}
5209	8664	if (active_buf)
5210	8665	cif_dev->rdbk_buf[RDBK_M] = active_buf;
5211		- if (cif_dev->hdr.mode == HDR_X2)
	8666	+ if (cif_dev->hdr.hdr_mode == HDR_X2)
5212	8667	rkcif_rdbk_frame_end(stream);
5213	8668	} else if (mipi_id == RKCIF_STREAM_MIPI_ID2) {
5214	8669	if (cif_dev->rdbk_buf[RDBK_S]) {
5215	8670	v4l2_err(&cif_dev->v4l2_dev,
5216	8671	"multiple %s frame, frm_idx:%d,state:0x%x\n",
5217		- cif_dev->hdr.mode == HDR_X2 ? "err short data in hdr_x3" : "short data in hdr_x3",
	8672	+ cif_dev->hdr.hdr_mode == HDR_X2 ? "err short data in hdr_x3" : "short data in hdr_x3",
5218	8673	stream->frame_idx,
5219	8674	cif_dev->rdbk_buf[RDBK_S]->vb.vb2_buf.state);
5220	8675	cif_dev->rdbk_buf[RDBK_S]->vb.vb2_buf.state = VB2_BUF_STATE_ACTIVE;
5221	8676	rkcif_buf_queue(&cif_dev->rdbk_buf[RDBK_S]->vb.vb2_buf);
	8677	+ cif_dev->rdbk_buf[RDBK_S] = NULL;
5222	8678	}
5223	8679	if (active_buf)
5224	8680	cif_dev->rdbk_buf[RDBK_S] = active_buf;
5225		- if (cif_dev->hdr.mode == HDR_X3)
	8681	+ if (cif_dev->hdr.hdr_mode == HDR_X3)
5226	8682	rkcif_rdbk_frame_end(stream);
5227	8683	}
5228	8684	spin_unlock_irqrestore(&cif_dev->hdr_lock, flags);
..	..	@@ -5265,12 +8721,129 @@
5265	8721	}
5266	8722	ret = rkcif_get_new_buffer_wake_up_mode(stream);
5267	8723	if (ret)
5268		- goto end_wake_up;
5269		-
	8724	+ return;
5270	8725	rkcif_buf_done_prepare(stream, active_buf, mipi_id, mode);
5271		-end_wake_up:
5272		- stream->frame_idx++;
	8726	+}
5273	8727
	8728	+static void rkcif_store_last_buf_for_online(struct rkcif_stream *stream,
	8729	+ struct rkcif_rx_buffer *buf)
	8730	+{
	8731	+ struct rkcif_device *dev = stream->cifdev;
	8732	+ struct v4l2_mbus_config *mbus_cfg = &dev->active_sensor->mbus;
	8733	+ u32 frm0_addr_y, frm1_addr_y;
	8734	+
	8735	+ INIT_LIST_HEAD(&stream->rx_buf_head);
	8736	+ stream->curr_buf_toisp = buf;
	8737	+ stream->next_buf_toisp = buf;
	8738	+ if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
	8739	+ mbus_cfg->type == V4L2_MBUS_CSI2_CPHY \|\|
	8740	+ mbus_cfg->type == V4L2_MBUS_CCP2) {
	8741	+ frm0_addr_y = get_reg_index_of_frm0_y_addr(stream->id);
	8742	+ frm1_addr_y = get_reg_index_of_frm1_y_addr(stream->id);
	8743	+ } else {
	8744	+ frm0_addr_y = get_dvp_reg_index_of_frm0_y_addr(stream->id);
	8745	+ frm1_addr_y = get_dvp_reg_index_of_frm1_y_addr(stream->id);
	8746	+ }
	8747	+ rkcif_write_register(dev, frm0_addr_y,
	8748	+ buf->dummy.dma_addr);
	8749	+ rkcif_write_register(dev, frm1_addr_y,
	8750	+ buf->dummy.dma_addr);
	8751	+}
	8752	+
	8753	+static void rkcif_release_unnecessary_buf_for_online(struct rkcif_stream *stream,
	8754	+ struct rkcif_rx_buffer *buf)
	8755	+{
	8756	+ struct rkcif_device *dev = stream->cifdev;
	8757	+ struct sditf_priv *priv = dev->sditf[0];
	8758	+ struct rkcif_rx_buffer *rx_buf = NULL;
	8759	+ unsigned long flags;
	8760	+ int i = 0;
	8761	+
	8762	+ spin_lock_irqsave(&priv->cif_dev->buffree_lock, flags);
	8763	+ for (i = 0; i < priv->buf_num; i++) {
	8764	+ rx_buf = &stream->rx_buf[i];
	8765	+ if (rx_buf && (!rx_buf->dummy.is_free) && rx_buf != buf) {
	8766	+ list_add_tail(&rx_buf->list_free, &priv->buf_free_list);
	8767	+ stream->total_buf_num--;
	8768	+ }
	8769	+ }
	8770	+ spin_unlock_irqrestore(&priv->cif_dev->buffree_lock, flags);
	8771	+ schedule_work(&priv->buffree_work.work);
	8772	+}
	8773	+
	8774	+static void rkcif_line_wake_up_rdbk(struct rkcif_stream *stream, int mipi_id)
	8775	+{
	8776	+ u32 mode;
	8777	+ struct rkcif_rx_buffer *active_buf = NULL;
	8778	+ struct sditf_priv *priv = NULL;
	8779	+ unsigned long flags;
	8780	+ int ret = 0;
	8781	+
	8782	+ mode = stream->line_int_cnt % 2;
	8783	+ if (mode) {
	8784	+ if (stream->curr_buf_toisp)
	8785	+ active_buf = stream->curr_buf_toisp;
	8786	+ stream->frame_phase = CIF_CSI_FRAME0_READY;
	8787	+ } else {
	8788	+ if (stream->next_buf_toisp)
	8789	+ active_buf = stream->next_buf_toisp;
	8790	+ stream->frame_phase = CIF_CSI_FRAME1_READY;
	8791	+ }
	8792	+
	8793	+ if (!active_buf) {
	8794	+ v4l2_err(&stream->cifdev->v4l2_dev,
	8795	+ "err buffer state in %s\n",
	8796	+ __func__);
	8797	+ return;
	8798	+ }
	8799	+
	8800	+ if (stream->stopping) {
	8801	+ stream->is_can_stop = true;
	8802	+ return;
	8803	+ }
	8804	+ ret = rkcif_get_new_buffer_wake_up_mode_rdbk(stream);
	8805	+ v4l2_dbg(3, rkcif_debug, &stream->cifdev->v4l2_dev,
	8806	+ "%d frame_idx %d, last_rx_buf_idx %d cur dma buf %x\n",
	8807	+ __LINE__, stream->frame_idx, stream->last_rx_buf_idx,
	8808	+ (u32)active_buf->dummy.dma_addr);
	8809	+ if (!ret) {
	8810	+ priv = stream->cifdev->sditf[0];
	8811	+ if (stream->cur_stream_mode & RKCIF_STREAM_MODE_TOISP_RDBK) {
	8812	+ spin_lock_irqsave(&stream->vbq_lock, flags);
	8813	+ if (stream->cifdev->is_thunderboot &&
	8814	+ (stream->frame_idx - 1) == stream->last_rx_buf_idx &&
	8815	+ stream->cifdev->is_rdbk_to_online) {
	8816	+ stream->cur_stream_mode &= ~RKCIF_STREAM_MODE_TOISP_RDBK;
	8817	+ stream->cur_stream_mode \|= RKCIF_STREAM_MODE_TOISP;
	8818	+ stream->cifdev->wait_line = 0;
	8819	+ stream->is_line_wake_up = false;
	8820	+ if (stream->cifdev->hdr.hdr_mode == NO_HDR \|\|
	8821	+ (priv->hdr_cfg.hdr_mode == HDR_X2 && stream->id == 1) \|\|
	8822	+ (priv->hdr_cfg.hdr_mode == HDR_X3 && stream->id == 2)) {
	8823	+ stream->to_stop_dma = RKCIF_DMAEN_BY_ISP;
	8824	+ rkcif_stop_dma_capture(stream);
	8825	+ }
	8826	+ active_buf->dbufs.is_switch = true;
	8827	+ if ((priv->hdr_cfg.hdr_mode == HDR_X2 && stream->id != 1) \|\|
	8828	+ (priv->hdr_cfg.hdr_mode == HDR_X3 && stream->id != 2)) {
	8829	+ rkcif_store_last_buf_for_online(stream, active_buf);
	8830	+ stream->is_change_toisp = true;
	8831	+ }
	8832	+ }
	8833	+ spin_unlock_irqrestore(&stream->vbq_lock, flags);
	8834	+ active_buf->dbufs.sequence = stream->frame_idx - 1;
	8835	+ active_buf->dbufs.timestamp = stream->readout.fs_timestamp;
	8836	+ active_buf->fe_timestamp = ktime_get_ns();
	8837	+ stream->last_frame_idx = stream->frame_idx;
	8838	+ if (stream->cifdev->hdr.hdr_mode == NO_HDR) {
	8839	+ rkcif_s_rx_buffer(stream->cifdev, &active_buf->dbufs);
	8840	+ if (stream->cifdev->is_support_tools && stream->tools_vdev)
	8841	+ rkcif_rdbk_with_tools(stream, active_buf);
	8842	+ } else {
	8843	+ rkcif_rdbk_frame_end_toisp(stream, active_buf);
	8844	+ }
	8845	+ }
	8846	+ }
5274	8847	}
5275	8848
5276	8849	static void rkcif_deal_readout_time(struct rkcif_stream *stream)
..	..	@@ -5281,17 +8854,24 @@
5281	8854
5282	8855	spin_lock_irqsave(&stream->fps_lock, flags);
5283	8856	stream->readout.fe_timestamp = ktime_get_ns();
	8857	+
	8858	+ if (cif_dev->inf_id == RKCIF_DVP) {
	8859	+ spin_unlock_irqrestore(&stream->fps_lock, flags);
	8860	+ return;
	8861	+ }
	8862	+
5284	8863	if (stream->id == RKCIF_STREAM_MIPI_ID0)
5285	8864	detect_stream->readout.readout_time = stream->readout.fe_timestamp - stream->readout.fs_timestamp;
5286	8865
5287		- if ((cif_dev->hdr.mode == NO_HDR) && (stream->id == RKCIF_STREAM_MIPI_ID0)) {
	8866	+ if ((cif_dev->hdr.hdr_mode == NO_HDR \|\| cif_dev->hdr.hdr_mode == HDR_COMPR) &&
	8867	+ (stream->id == RKCIF_STREAM_MIPI_ID0)) {
5288	8868	detect_stream->readout.early_time = stream->readout.fe_timestamp - stream->readout.wk_timestamp;
5289	8869
5290		- } else if ((cif_dev->hdr.mode == HDR_X2) && (stream->id == RKCIF_STREAM_MIPI_ID1)) {
	8870	+ } else if ((cif_dev->hdr.hdr_mode == HDR_X2) && (stream->id == RKCIF_STREAM_MIPI_ID1)) {
5291	8871	detect_stream->readout.early_time = stream->readout.fe_timestamp - stream->readout.wk_timestamp;
5292	8872	detect_stream->readout.total_time = stream->readout.fe_timestamp - detect_stream->readout.fe_timestamp;
5293	8873	detect_stream->readout.total_time += detect_stream->readout.readout_time;
5294		- } else if ((cif_dev->hdr.mode == HDR_X3) && (stream->id == RKCIF_STREAM_MIPI_ID2)) {
	8874	+ } else if ((cif_dev->hdr.hdr_mode == HDR_X3) && (stream->id == RKCIF_STREAM_MIPI_ID2)) {
5295	8875	detect_stream->readout.early_time = stream->readout.fe_timestamp - stream->readout.wk_timestamp;
5296	8876	detect_stream->readout.total_time = stream->readout.fe_timestamp - detect_stream->readout.fe_timestamp;
5297	8877	detect_stream->readout.total_time += detect_stream->readout.readout_time;
..	..	@@ -5310,11 +8890,8 @@
5310	8890	int ret = 0;
5311	8891
5312	8892	if (stream->frame_phase == (CIF_CSI_FRAME0_READY \| CIF_CSI_FRAME1_READY)) {
5313		-
5314		- v4l2_err(&cif_dev->v4l2_dev, "stream[%d], frm0/frm1 end simultaneously,frm id:%d\n",
5315		- stream->id, stream->frame_idx);
5316		-
5317		- stream->frame_idx++;
	8893	+ cif_dev->err_state \|= (RKCIF_ERR_ID0_TRIG_SIMULT << stream->id);
	8894	+ cif_dev->irq_stats.trig_simult_cnt[stream->id]++;
5318	8895	return;
5319	8896	}
5320	8897	if (!stream->is_line_wake_up) {
..	..	@@ -5332,99 +8909,181 @@
5332	8909	spin_unlock_irqrestore(&stream->fps_lock, flags);
5333	8910	}
5334	8911
5335		- if (cif_dev->inf_id == RKCIF_MIPI_LVDS)
5336		- rkcif_deal_readout_time(stream);
	8912	+ rkcif_deal_readout_time(stream);
	8913	+
	8914	+ if (!stream->is_line_wake_up) {
	8915	+ ret = rkcif_assign_new_buffer_pingpong(stream,
	8916	+ RKCIF_YUV_ADDR_STATE_UPDATE,
	8917	+ mipi_id);
	8918	+ if (ret && cif_dev->chip_id < CHIP_RK3588_CIF)
	8919	+ return;
	8920	+ } else {
	8921	+ ret = rkcif_update_new_buffer_wake_up_mode(stream);
	8922	+ if (ret && cif_dev->chip_id < CHIP_RK3588_CIF)
	8923	+ return;
	8924	+ }
	8925	+ if (cif_dev->chip_id < CHIP_RK3588_CIF &&
	8926	+ cif_dev->active_sensor->mbus.type == V4L2_MBUS_BT656 &&
	8927	+ stream->id != 0)
	8928	+ stream->frame_idx++;
	8929	+ if (!stream->is_line_wake_up && stream->dma_en & RKCIF_DMAEN_BY_VICAP)
	8930	+ rkcif_buf_done_prepare(stream, active_buf, mipi_id, 0);
5337	8931
5338	8932	if (cif_dev->chip_id == CHIP_RV1126_CIF \|\|
5339	8933	cif_dev->chip_id == CHIP_RV1126_CIF_LITE \|\|
5340	8934	cif_dev->chip_id == CHIP_RK3568_CIF)
5341		- rkcif_luma_isr(&cif_dev->luma_vdev, mipi_id, stream->frame_idx);
5342		-
5343		- if (!stream->is_line_wake_up) {
5344		- ret = rkcif_assign_new_buffer_pingpong(stream,
5345		- RKCIF_YUV_ADDR_STATE_UPDATE,
5346		- mipi_id);
5347		- if (ret)
5348		- goto end;
5349		- } else {
5350		- ret = rkcif_update_new_buffer_wake_up_mode(stream);
5351		- if (ret)
5352		- return;
5353		- }
5354		- if (!stream->is_line_wake_up)
5355		- rkcif_buf_done_prepare(stream, active_buf, mipi_id, 0);
5356		-
5357		-end:
5358		- if (!stream->is_line_wake_up)
5359		- stream->frame_idx++;
	8935	+ rkcif_luma_isr(&cif_dev->luma_vdev, mipi_id, cif_dev->stream[0].frame_idx - 1);
5360	8936	}
5361	8937
5362		-u32 rkcif_get_sof(struct rkcif_device *cif_dev)
	8938	+static void rkcif_update_stream_toisp(struct rkcif_device *cif_dev,
	8939	+ struct rkcif_stream *stream,
	8940	+ int mipi_id)
	8941	+{
	8942	+ if (stream->frame_phase == (CIF_CSI_FRAME0_READY \| CIF_CSI_FRAME1_READY)) {
	8943	+
	8944	+ v4l2_err(&cif_dev->v4l2_dev, "stream[%d], frm0/frm1 end simultaneously,frm id:%d\n",
	8945	+ stream->id, stream->frame_idx);
	8946	+ return;
	8947	+ }
	8948	+
	8949	+ spin_lock(&stream->fps_lock);
	8950	+ if (stream->frame_phase & CIF_CSI_FRAME0_READY)
	8951	+ stream->fps_stats.frm0_timestamp = ktime_get_ns();
	8952	+ else if (stream->frame_phase & CIF_CSI_FRAME1_READY)
	8953	+ stream->fps_stats.frm1_timestamp = ktime_get_ns();
	8954	+ spin_unlock(&stream->fps_lock);
	8955	+
	8956	+ if (cif_dev->inf_id == RKCIF_MIPI_LVDS)
	8957	+ rkcif_deal_readout_time(stream);
	8958	+
	8959	+ if (!stream->is_line_wake_up)
	8960	+ rkcif_assign_new_buffer_pingpong_toisp(stream,
	8961	+ RKCIF_YUV_ADDR_STATE_UPDATE,
	8962	+ mipi_id);
	8963	+}
	8964	+
	8965	+static void rkcif_update_stream_rockit(struct rkcif_device *cif_dev,
	8966	+ struct rkcif_stream *stream,
	8967	+ int mipi_id)
	8968	+{
	8969	+ struct rkcif_buffer *active_buf = NULL;
	8970	+ unsigned long flags;
	8971	+ int ret = 0;
	8972	+
	8973	+ if (stream->frame_phase == (CIF_CSI_FRAME0_READY \| CIF_CSI_FRAME1_READY)) {
	8974	+
	8975	+ v4l2_err(&cif_dev->v4l2_dev, "stream[%d], frm0/frm1 end simultaneously,frm id:%d\n",
	8976	+ stream->id, stream->frame_idx);
	8977	+ return;
	8978	+ }
	8979	+ if (!stream->is_line_wake_up) {
	8980	+
	8981	+ spin_lock_irqsave(&stream->fps_lock, flags);
	8982	+ if (stream->frame_phase & CIF_CSI_FRAME0_READY) {
	8983	+ if (stream->curr_buf_rockit)
	8984	+ active_buf = stream->curr_buf_rockit;
	8985	+ stream->fps_stats.frm0_timestamp = ktime_get_ns();
	8986	+ } else if (stream->frame_phase & CIF_CSI_FRAME1_READY) {
	8987	+ if (stream->next_buf_rockit)
	8988	+ active_buf = stream->next_buf_rockit;
	8989	+ stream->fps_stats.frm1_timestamp = ktime_get_ns();
	8990	+ }
	8991	+ spin_unlock_irqrestore(&stream->fps_lock, flags);
	8992	+ }
	8993	+
	8994	+ if (cif_dev->inf_id == RKCIF_MIPI_LVDS)
	8995	+ rkcif_deal_readout_time(stream);
	8996	+
	8997	+ ret = rkcif_assign_new_buffer_pingpong_rockit(stream,
	8998	+ RKCIF_YUV_ADDR_STATE_UPDATE,
	8999	+ mipi_id);
	9000	+ if (ret)
	9001	+ return;
	9002	+
	9003	+ if (active_buf) {
	9004	+ active_buf->vb.vb2_buf.timestamp = stream->readout.fs_timestamp;
	9005	+ active_buf->vb.sequence = stream->frame_idx - 1;
	9006	+ rkcif_rockit_buf_done(stream, active_buf);
	9007	+ }
	9008	+}
	9009	+
	9010	+static u32 rkcif_get_sof(struct rkcif_device *cif_dev)
5363	9011	{
5364	9012	u32 val = 0x0;
5365	9013	struct rkcif_sensor_info *sensor = cif_dev->active_sensor;
	9014	+ struct csi2_dev *csi;
5366	9015
5367		- if (sensor->mbus.type == V4L2_MBUS_CSI2)
5368		- val = rkcif_csi2_get_sof();
5369		- else if (sensor->mbus.type == V4L2_MBUS_CCP2)
	9016	+ if (sensor->mbus.type == V4L2_MBUS_CSI2_DPHY \|\|
	9017	+ sensor->mbus.type == V4L2_MBUS_CSI2_CPHY) {
	9018	+ csi = container_of(sensor->sd, struct csi2_dev, sd);
	9019	+ val = rkcif_csi2_get_sof(csi);
	9020	+ } else if (sensor->mbus.type == V4L2_MBUS_CCP2) {
5370	9021	val = rkcif_lvds_get_sof(cif_dev);
5371		- else if (sensor->mbus.type == V4L2_MBUS_PARALLEL \|\|
5372		- sensor->mbus.type == V4L2_MBUS_BT656)
	9022	+ } else if (sensor->mbus.type == V4L2_MBUS_PARALLEL \|\|
	9023	+ sensor->mbus.type == V4L2_MBUS_BT656) {
5373	9024	val = rkcif_dvp_get_sof(cif_dev);
5374		-
	9025	+ }
5375	9026	return val;
5376	9027	}
5377	9028
5378	9029	static void rkcif_set_sof(struct rkcif_device *cif_dev, u32 seq)
5379	9030	{
5380	9031	struct rkcif_sensor_info *sensor = cif_dev->active_sensor;
	9032	+ struct csi2_dev *csi;
5381	9033
5382		- if (sensor->mbus.type == V4L2_MBUS_CSI2)
5383		- rkcif_csi2_set_sof(seq);
5384		- else if (sensor->mbus.type == V4L2_MBUS_CCP2)
	9034	+ if (sensor->mbus.type == V4L2_MBUS_CSI2_DPHY \|\|
	9035	+ sensor->mbus.type == V4L2_MBUS_CSI2_CPHY) {
	9036	+ csi = container_of(sensor->sd, struct csi2_dev, sd);
	9037	+ rkcif_csi2_set_sof(csi, seq);
	9038	+ } else if (sensor->mbus.type == V4L2_MBUS_CCP2) {
5385	9039	rkcif_lvds_set_sof(cif_dev, seq);
5386		- else if (sensor->mbus.type == V4L2_MBUS_PARALLEL \|\|
5387		- sensor->mbus.type == V4L2_MBUS_BT656)
	9040	+ } else if (sensor->mbus.type == V4L2_MBUS_PARALLEL \|\|
	9041	+ sensor->mbus.type == V4L2_MBUS_BT656) {
5388	9042	rkcif_dvp_set_sof(cif_dev, seq);
	9043	+ }
5389	9044	}
5390	9045
5391		-static int rkcif_streamoff_in_reset(struct rkcif_device *cif_dev,
5392		- struct rkcif_stream *resume_stream[],
5393		- struct rkcif_resume_info *resume_info,
5394		- enum rkmodule_reset_src reset_src)
	9046	+static int rkcif_do_reset_work(struct rkcif_device *cif_dev,
	9047	+ enum rkmodule_reset_src reset_src)
5395	9048	{
5396		- struct rkcif_stream *stream = NULL;
5397	9049	struct rkcif_pipeline *p = &cif_dev->pipe;
	9050	+ struct rkcif_stream *stream = NULL;
	9051	+ struct rkcif_stream *resume_stream[RKCIF_MAX_STREAM_MIPI] = { NULL };
5398	9052	struct rkcif_sensor_info *terminal_sensor = &cif_dev->terminal_sensor;
5399		- u32 on, sof_cnt;
	9053	+ struct rkcif_resume_info *resume_info = &cif_dev->reset_work.resume_info;
	9054	+ struct rkcif_timer *timer = &cif_dev->reset_watchdog_timer;
	9055	+ struct sditf_priv *priv = cif_dev->sditf[0];
5400	9056	int i, j, ret = 0;
5401		- int stream_off_cnt = 0;
	9057	+ u32 on, sof_cnt;
	9058	+ int capture_mode = 0;
	9059	+
	9060	+ mutex_lock(&cif_dev->stream_lock);
	9061	+ if (cif_dev->reset_work_cancel) {
	9062	+ ret = 0;
	9063	+ goto unlock_stream;
	9064	+ }
	9065	+ v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev, "do rkcif reset\n");
5402	9066
5403	9067	for (i = 0, j = 0; i < RKCIF_MAX_STREAM_MIPI; i++) {
5404	9068	stream = &cif_dev->stream[i];
5405		- mutex_lock(&cif_dev->stream_lock);
	9069	+
5406	9070	if (stream->state == RKCIF_STATE_STREAMING) {
5407		- stream_off_cnt++;
5408	9071
5409	9072	v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev,
5410	9073	"stream[%d] stopping\n", stream->id);
5411	9074
5412	9075	rkcif_stream_stop(stream);
5413	9076
5414		- atomic_dec(&p->stream_cnt);
5415		-
5416	9077	if (stream->id == RKCIF_STREAM_MIPI_ID0) {
5417	9078	sof_cnt = rkcif_get_sof(cif_dev);
5418		- v4l2_err(&cif_dev->v4l2_dev,
	9079	+ v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev,
5419	9080	"%s: stream[%d] sync frmid & csi_sof, frm_id:%d, csi_sof:%d\n",
5420	9081	__func__,
5421	9082	stream->id,
5422	9083	stream->frame_idx,
5423	9084	sof_cnt);
5424	9085
5425		- resume_info->frm_sync_seq = sof_cnt;
5426		- if (stream->frame_idx != sof_cnt)
5427		- stream->frame_idx = sof_cnt;
	9086	+ resume_info->frm_sync_seq = stream->frame_idx;
5428	9087	}
5429	9088
5430	9089	stream->state = RKCIF_STATE_RESET_IN_STREAMING;
..	..	@@ -5435,59 +9094,63 @@
5435	9094
5436	9095	v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev,
5437	9096	"%s stop stream[%d] in streaming, frm_id:%d, csi_sof:%d\n",
5438		- __func__, stream->id, stream->frame_idx, rkcif_csi2_get_sof());
	9097	+ __func__, stream->id, stream->frame_idx, rkcif_get_sof(cif_dev));
5439	9098
5440	9099	}
5441		- mutex_unlock(&cif_dev->stream_lock);
5442	9100	}
5443		- if (!stream_off_cnt)
5444		- return 0;
5445	9101
5446	9102	on = 0;
5447	9103	for (i = 0; i < p->num_subdevs; i++) {
5448	9104
5449	9105	if (p->subdevs[i] == terminal_sensor->sd) {
5450	9106
5451		- if (reset_src == RKCIF_RESET_SRC_ERR_CSI2 \|\|
5452		- reset_src == RKCIF_RESET_SRC_ERR_HOTPLUG \|\|
5453		- reset_src == RKICF_RESET_SRC_ERR_CUTOFF) {
5454		-
	9107	+ if (reset_src != RKCIF_RESET_SRC_ERR_APP) {
5455	9108	ret = v4l2_subdev_call(p->subdevs[i], core, ioctl,
5456	9109	RKMODULE_SET_QUICK_STREAM, &on);
5457	9110	if (ret)
5458		- v4l2_err(&cif_dev->v4l2_dev, "quick stream off subdev:%s failed\n",
	9111	+ v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev,
	9112	+ "quick stream off subdev:%s failed\n",
5459	9113	p->subdevs[i]->name);
5460	9114	}
	9115	+ } else {
	9116	+ ret = v4l2_subdev_call(p->subdevs[i], video, s_stream, on);
5461	9117	}
5462		-
5463	9118	if (ret)
5464		- v4l2_err(&cif_dev->v4l2_dev, "%s:stream %s subdev:%s failed\n",
	9119	+ v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev,
	9120	+ "%s:stream %s subdev:%s failed\n",
5465	9121	__func__, on ? "on" : "off", p->subdevs[i]->name);
5466		-
5467	9122	}
5468		- return ret;
5469		-}
5470	9123
5471		-static int rkcif_streamon_in_reset(struct rkcif_device *cif_dev,
5472		- struct rkcif_stream *resume_stream[],
5473		- struct rkcif_resume_info *resume_info,
5474		- enum rkmodule_reset_src reset_src)
5475		-{
5476		- struct rkcif_timer *timer = &cif_dev->reset_watchdog_timer;
5477		- struct rkcif_stream *stream = NULL;
5478		- struct rkcif_pipeline *p = &cif_dev->pipe;
5479		- struct rkcif_sensor_info *terminal_sensor = &cif_dev->terminal_sensor;
5480		- int i = 0;
5481		- int ret = 0;
5482		- int on = 0;
5483		- int stream_on_cnt = 0;
	9124	+ if (priv && priv->is_combine_mode && cif_dev->sditf_cnt <= RKCIF_MAX_SDITF) {
	9125	+ for (i = 0; i < cif_dev->sditf_cnt; i++) {
	9126	+ if (cif_dev->sditf[i] && cif_dev->sditf[i]->sensor_sd)
	9127	+ ret = v4l2_subdev_call(cif_dev->sditf[i]->sensor_sd, core, ioctl,
	9128	+ RKMODULE_SET_QUICK_STREAM, &on);
	9129	+ }
	9130	+ }
5484	9131
5485		- for (i = 0; i < RKCIF_MAX_STREAM_MIPI; i++) {
	9132	+ rockchip_clear_system_status(SYS_STATUS_CIF0);
	9133	+
	9134	+ if (cif_dev->chip_id >= CHIP_RK3588_CIF) {
	9135	+ rkcif_do_soft_reset(cif_dev);
	9136	+ } else {
	9137	+
	9138	+ rkcif_do_cru_reset(cif_dev);
	9139	+
	9140	+ rkcif_disable_sys_clk(cif_dev->hw_dev);
	9141	+
	9142	+ udelay(5);
	9143	+
	9144	+ ret = rkcif_enable_sys_clk(cif_dev->hw_dev);
	9145	+
	9146	+ if (ret < 0) {
	9147	+ v4l2_err(&cif_dev->v4l2_dev, "%s:resume cif clk failed\n", __func__);
	9148	+ goto unlock_stream;
	9149	+ }
	9150	+ }
	9151	+
	9152	+ for (i = 0; i < j; i++) {
5486	9153	stream = resume_stream[i];
5487		- if (stream == NULL \|\| stream->state != RKCIF_STATE_RESET_IN_STREAMING)
5488		- break;
5489		- mutex_lock(&cif_dev->stream_lock);
5490		- stream_on_cnt++;
5491	9154	stream->fs_cnt_in_single_frame = 0;
5492	9155	if (stream->cif_fmt_in->field == V4L2_FIELD_INTERLACED) {
5493	9156	if (stream->curr_buf == stream->next_buf) {
..	..	@@ -5502,26 +9165,35 @@
5502	9165	stream->curr_buf = NULL;
5503	9166	stream->next_buf = NULL;
5504	9167	}
5505		- if (cif_dev->active_sensor->mbus.type == V4L2_MBUS_CSI2 \|\|
5506		- cif_dev->active_sensor->mbus.type == V4L2_MBUS_CCP2)
5507		- ret = rkcif_csi_stream_start(stream);
	9168	+ if (!cif_dev->sditf[0] \|\| cif_dev->sditf[0]->mode.rdbk_mode == RKISP_VICAP_RDBK_AIQ)
	9169	+ capture_mode = RKCIF_STREAM_MODE_CAPTURE;
	9170	+ else {
	9171	+ if (cif_dev->sditf[0]->mode.rdbk_mode == RKISP_VICAP_ONLINE)
	9172	+ capture_mode = RKCIF_STREAM_MODE_TOISP;
	9173	+ else
	9174	+ capture_mode = RKCIF_STREAM_MODE_TOISP_RDBK;
	9175	+ }
	9176	+ if (cif_dev->active_sensor &&
	9177	+ (cif_dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_DPHY \|\|
	9178	+ cif_dev->active_sensor->mbus.type == V4L2_MBUS_CSI2_CPHY \|\|
	9179	+ cif_dev->active_sensor->mbus.type == V4L2_MBUS_CCP2))
	9180	+ ret = rkcif_csi_stream_start(stream, capture_mode);
5508	9181	else
5509		- ret = rkcif_stream_start(stream);
	9182	+ ret = rkcif_stream_start(stream, capture_mode);
5510	9183	if (ret) {
5511	9184	v4l2_err(&cif_dev->v4l2_dev, "%s:resume stream[%d] failed\n",
5512	9185	__func__, stream->id);
5513	9186	goto unlock_stream;
5514	9187	}
5515		- atomic_inc(&p->stream_cnt);
5516		- stream->streamon_timestamp = ktime_get_ns();
5517		- mutex_unlock(&cif_dev->stream_lock);
	9188	+
5518	9189	v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev,
5519	9190	"resume stream[%d], frm_idx:%d, csi_sof:%d\n",
5520	9191	stream->id, stream->frame_idx,
5521	9192	rkcif_get_sof(cif_dev));
5522	9193	}
5523		- if (!stream_on_cnt)
5524		- return 0;
	9194	+
	9195	+ rockchip_set_system_status(SYS_STATUS_CIF0);
	9196	+
5525	9197	on = 1;
5526	9198	for (i = 0; i < p->num_subdevs; i++) {
5527	9199
..	..	@@ -5529,9 +9201,7 @@
5529	9201
5530	9202	rkcif_set_sof(cif_dev, resume_info->frm_sync_seq);
5531	9203
5532		- if (reset_src == RKCIF_RESET_SRC_ERR_CSI2 \|\|
5533		- reset_src == RKCIF_RESET_SRC_ERR_HOTPLUG \|\|
5534		- reset_src == RKICF_RESET_SRC_ERR_CUTOFF) {
	9204	+ if (reset_src != RKCIF_RESET_SRC_ERR_APP) {
5535	9205	ret = v4l2_subdev_call(p->subdevs[i], core, ioctl,
5536	9206	RKMODULE_SET_QUICK_STREAM, &on);
5537	9207	if (ret)
..	..	@@ -5539,6 +9209,11 @@
5539	9209	"quick stream on subdev:%s failed\n",
5540	9210	p->subdevs[i]->name);
5541	9211	}
	9212	+ } else {
	9213	+ if (p->subdevs[i] == terminal_sensor->sd)
	9214	+ rkcif_set_sof(cif_dev, resume_info->frm_sync_seq);
	9215	+
	9216	+ ret = v4l2_subdev_call(p->subdevs[i], video, s_stream, on);
5542	9217	}
5543	9218
5544	9219	if (ret)
..	..	@@ -5546,71 +9221,28 @@
5546	9221	p->subdevs[i]->name);
5547	9222	}
5548	9223
5549		- rkcif_start_luma(&cif_dev->luma_vdev, resume_stream[0]->cif_fmt_in);
	9224	+ if (priv && priv->is_combine_mode && cif_dev->sditf_cnt <= RKCIF_MAX_SDITF) {
	9225	+ for (i = 0; i < cif_dev->sditf_cnt; i++) {
	9226	+ if (cif_dev->sditf[i] && cif_dev->sditf[i]->sensor_sd)
	9227	+ v4l2_subdev_call(cif_dev->sditf[i]->sensor_sd, core, ioctl,
	9228	+ RKMODULE_SET_QUICK_STREAM, &on);
	9229	+ }
	9230	+ }
	9231	+
	9232	+ if (cif_dev->chip_id < CHIP_RK3588_CIF)
	9233	+ rkcif_start_luma(&cif_dev->luma_vdev,
	9234	+ cif_dev->stream[RKCIF_STREAM_MIPI_ID0].cif_fmt_in);
5550	9235
5551	9236	timer->csi2_err_triggered_cnt = 0;
	9237	+ rkcif_monitor_reset_event(cif_dev);
5552	9238
5553	9239	v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev, "do rkcif reset successfully!\n");
5554		-
5555	9240	mutex_unlock(&cif_dev->stream_lock);
5556	9241	return 0;
5557	9242
5558	9243	unlock_stream:
5559	9244	mutex_unlock(&cif_dev->stream_lock);
5560	9245	return ret;
5561		-}
5562		-
5563		-static int rkcif_do_reset_work(struct rkcif_device *cif_dev,
5564		- enum rkmodule_reset_src reset_src)
5565		-{
5566		- struct rkcif_stream *resume_stream[RKCIF_MAX_DEV][RKCIF_MAX_STREAM_MIPI] = {0};
5567		- struct rkcif_resume_info *resume_info[RKCIF_MAX_DEV];
5568		- struct rkcif_hw *hw = cif_dev->hw_dev;
5569		- struct rkcif_device *cifdev = NULL;
5570		- int i = 0;
5571		- int ret = 0;
5572		-
5573		- v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev, "do rkcif reset\n");
5574		-
5575		- for (i = 0; i < hw->dev_num; i++) {
5576		- cifdev = hw->cif_dev[i];
5577		- resume_info[i] = &cifdev->reset_work.resume_info;
5578		- ret \|= rkcif_streamoff_in_reset(cifdev,
5579		- resume_stream[i],
5580		- resume_info[i],
5581		- reset_src);
5582		- }
5583		-
5584		- rockchip_clear_system_status(SYS_STATUS_CIF0);
5585		-
5586		- rkcif_do_cru_reset(cif_dev);
5587		-
5588		- rkcif_disable_sys_clk(cif_dev->hw_dev);
5589		-
5590		- udelay(5);
5591		-
5592		- ret \|= rkcif_enable_sys_clk(cif_dev->hw_dev);
5593		- if (ret < 0)
5594		- v4l2_err(&cif_dev->v4l2_dev, "%s:resume cif clk failed\n", __func__);
5595		-
5596		- for (i = 0; i < hw->dev_num; i++) {
5597		- cifdev = hw->cif_dev[i];
5598		- resume_info[i] = &cifdev->reset_work.resume_info;
5599		- ret \|= rkcif_streamon_in_reset(cifdev,
5600		- resume_stream[i],
5601		- resume_info[i],
5602		- reset_src);
5603		- }
5604		-
5605		- rockchip_set_system_status(SYS_STATUS_CIF0);
5606		-
5607		- hw->hw_timer.is_running = false;
5608		- rkcif_monitor_reset_event(cif_dev->hw_dev);
5609		-
5610		- v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev, "do rkcif reset successfully!\n");
5611		-
5612		- return ret;
5613		-
5614	9246	}
5615	9247
5616	9248	void rkcif_reset_work(struct work_struct *work)
..	..	@@ -5628,128 +9260,183 @@
5628	9260	v4l2_info(&dev->v4l2_dev, "do reset work failed!\n");
5629	9261	}
5630	9262
5631		-static bool rkcif_is_stream_stop_output(struct rkcif_stream *stream)
	9263	+static bool rkcif_is_reduced_frame_rate(struct rkcif_device *dev)
5632	9264	{
5633		- struct rkcif_device *dev = stream->cifdev;
5634		- struct rkcif_hw_timer *hw_timer = &dev->hw_dev->hw_timer;
5635		- struct rkcif_stream *tmp_stream = NULL;
	9265	+ struct rkcif_timer *timer = &dev->reset_watchdog_timer;
	9266	+ struct rkcif_stream *stream = &dev->stream[RKCIF_STREAM_MIPI_ID0];
5636	9267	struct v4l2_rect *raw_rect = &dev->terminal_sensor.raw_rect;
5637		- u64 fps, diff_time;
5638		- unsigned int i;
5639		- s64 vblank_def = 0;
5640		- s32 vblank = 0;
5641		- u64 numerator = 0;
5642		- u64 denominator = 0;
5643		- u64 cur_timestamp = 0;
	9268	+ u64 fps, timestamp0, timestamp1, diff_time;
	9269	+ unsigned long fps_flags;
	9270	+ unsigned int deviation = 1;
	9271	+ bool is_reduced = false;
	9272	+ u64 cur_time = 0;
	9273	+ u64 time_distance = 0;
5644	9274
5645		- if (dev->hdr.mode == HDR_X3) {
5646		- for (i = 0; i < 3; i++) {
5647		- tmp_stream = &dev->stream[i];
5648		- if (tmp_stream->state != RKCIF_STATE_STREAMING)
5649		- return false;
5650		- }
5651		- } else if (dev->hdr.mode == HDR_X2) {
5652		- for (i = 0; i < 2; i++) {
5653		- tmp_stream = &dev->stream[i];
5654		- if (tmp_stream->state != RKCIF_STATE_STREAMING)
5655		- return false;
5656		- }
5657		- }
	9275	+ spin_lock_irqsave(&stream->fps_lock, fps_flags);
	9276	+ timestamp0 = stream->fps_stats.frm0_timestamp;
	9277	+ timestamp1 = stream->fps_stats.frm1_timestamp;
	9278	+ spin_unlock_irqrestore(&stream->fps_lock, fps_flags);
5658	9279
5659		- vblank_def = rkcif_get_sensor_vblank_def(dev);
5660		- vblank = rkcif_get_sensor_vblank(dev);
5661		- numerator = dev->terminal_sensor.fi.interval.numerator;
5662		- denominator = dev->terminal_sensor.fi.interval.denominator;
5663		- fps = div_u64(1000 * numerator, denominator);
5664		- fps *= (raw_rect->height + vblank);
5665		- fps = div_u64((raw_rect->height + vblank_def), fps);
	9280	+ fps = timestamp0 > timestamp1 ?
	9281	+ timestamp0 - timestamp1 : timestamp1 - timestamp0;
	9282	+ fps = div_u64(fps, 1000);
	9283	+ diff_time = fps > timer->frame_end_cycle_us ?
	9284	+ fps - timer->frame_end_cycle_us : 0;
	9285	+ deviation = DIV_ROUND_UP(timer->vts, 100);
5666	9286
5667		- if (fps > hw_timer->monitor_cycle) {
5668		- v4l2_dbg(1, rkcif_debug, &dev->v4l2_dev, "camera work in long expsure, not to check stream loss\n");
	9287	+ v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev, "diff_time:%lld,devi_t:%ld,devi_h:%d\n",
	9288	+ diff_time, timer->line_end_cycle * deviation, deviation);
	9289	+
	9290	+ cur_time = ktime_get_ns();
	9291	+ time_distance = timestamp0 > timestamp1 ?
	9292	+ cur_time - timestamp0 : cur_time - timestamp1;
	9293	+ time_distance = div_u64(time_distance, 1000);
	9294	+ if (time_distance > fps * 2)
5669	9295	return false;
	9296	+
	9297	+ if (diff_time > timer->line_end_cycle * deviation) {
	9298	+ s32 vblank = 0;
	9299	+ unsigned int vts;
	9300	+
	9301	+ is_reduced = true;
	9302	+ vblank = rkcif_get_sensor_vblank(dev);
	9303	+ vts = vblank + timer->raw_height;
	9304	+
	9305	+ v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev, "old vts:%d,new vts:%d\n", timer->vts, vts);
	9306	+
	9307	+ v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev,
	9308	+ "reduce frame rate,vblank:%d, height(raw output):%d, fps:%lld, frm_end_t:%ld, line_t:%ld, diff:%lld\n",
	9309	+ rkcif_get_sensor_vblank(dev),
	9310	+ raw_rect->height,
	9311	+ fps,
	9312	+ timer->frame_end_cycle_us,
	9313	+ timer->line_end_cycle,
	9314	+ diff_time);
	9315	+
	9316	+ timer->vts = vts;
	9317	+ timer->frame_end_cycle_us = fps;
	9318	+ timer->line_end_cycle = div_u64(timer->frame_end_cycle_us, timer->vts);
	9319	+ } else {
	9320	+ is_reduced = false;
5670	9321	}
5671	9322
5672		- cur_timestamp = ktime_get_ns();
5673		- diff_time = cur_timestamp - stream->streamon_timestamp;
5674		- diff_time = div_u64(diff_time, 1000000);
5675		- if (diff_time > hw_timer->monitor_cycle + 10)
5676		- return true;
	9323	+ timer->frame_end_cycle_us = fps;
5677	9324
5678		- return false;
	9325	+ fps = div_u64(fps, 1000);
	9326	+ fps = fps * timer->frm_num_of_monitor_cycle;
	9327	+ timer->cycle = msecs_to_jiffies(fps);
	9328	+ timer->timer.expires = jiffies + timer->cycle;
	9329	+
	9330	+ return is_reduced;
	9331	+
5679	9332	}
5680	9333
5681		-static void rkcif_init_reset_work(struct rkcif_hw_timer *hw_timer)
	9334	+static void rkcif_dvp_event_reset_pipe(struct rkcif_device *dev, int reset_src)
5682	9335	{
5683		- struct rkcif_hw *hw = container_of(hw_timer,
5684		- struct rkcif_hw,
5685		- hw_timer);
5686		- struct rkcif_device *dev = NULL;
	9336	+ struct rkcif_dvp_sof_subdev *subdev = &dev->dvp_sof_subdev;
	9337	+
	9338	+ if (subdev) {
	9339	+ struct v4l2_event event = {
	9340	+ .type = V4L2_EVENT_RESET_DEV,
	9341	+ .reserved[0] = reset_src,
	9342	+ };
	9343	+ v4l2_event_queue(subdev->sd.devnode, &event);
	9344	+ }
	9345	+}
	9346	+
	9347	+static void rkcif_lvds_event_reset_pipe(struct rkcif_device *dev, int reset_src)
	9348	+{
	9349	+ struct rkcif_lvds_subdev *subdev = &dev->lvds_subdev;
	9350	+
	9351	+ if (subdev) {
	9352	+ struct v4l2_event event = {
	9353	+ .type = V4L2_EVENT_RESET_DEV,
	9354	+ .reserved[0] = reset_src,
	9355	+ };
	9356	+ v4l2_event_queue(subdev->sd.devnode, &event);
	9357	+ }
	9358	+}
	9359	+
	9360	+static void rkcif_send_reset_event(struct rkcif_device *cif_dev, int reset_src)
	9361	+{
	9362	+ struct v4l2_mbus_config *mbus = &cif_dev->active_sensor->mbus;
	9363	+ struct csi2_dev *csi;
	9364	+
	9365	+ if (mbus->type == V4L2_MBUS_CSI2_DPHY \|\|
	9366	+ mbus->type == V4L2_MBUS_CSI2_CPHY) {
	9367	+ csi = container_of(cif_dev->active_sensor->sd, struct csi2_dev, sd);
	9368	+ rkcif_csi2_event_reset_pipe(csi, reset_src);
	9369	+ } else if (mbus->type == V4L2_MBUS_CCP2) {
	9370	+ rkcif_lvds_event_reset_pipe(cif_dev, reset_src);
	9371	+ } else {
	9372	+ rkcif_dvp_event_reset_pipe(cif_dev, reset_src);
	9373	+ }
	9374	+ v4l2_dbg(3, rkcif_debug, &cif_dev->v4l2_dev,
	9375	+ "send reset event,bus type 0x%x\n",
	9376	+ mbus->type);
	9377	+}
	9378	+
	9379	+static void rkcif_init_reset_work(struct rkcif_timer *timer)
	9380	+{
	9381	+ struct rkcif_device *dev = container_of(timer,
	9382	+ struct rkcif_device,
	9383	+ reset_watchdog_timer);
5687	9384	struct rkcif_stream *stream = NULL;
5688		- struct rkcif_timer *timer;
5689	9385	unsigned long flags;
5690		- int i = 0, j = 0;
	9386	+ int i = 0;
5691	9387
5692	9388	v4l2_info(&dev->v4l2_dev,
5693	9389	"do reset work schedule, run_cnt:%d, reset source:%d\n",
5694		- hw_timer->run_cnt, hw_timer->reset_src);
	9390	+ timer->run_cnt, timer->reset_src);
5695	9391
5696		- for (j = 0; j < hw->dev_num; j++) {
5697		- dev = hw->cif_dev[j];
5698		- timer = &dev->reset_watchdog_timer;
5699		- spin_lock_irqsave(&timer->csi2_err_lock, flags);
5700		- timer->is_triggered = false;
5701		- timer->csi2_err_cnt_odd = 0;
5702		- timer->csi2_err_cnt_even = 0;
5703		- timer->csi2_err_fs_fe_cnt = 0;
5704		- timer->notifer_called_cnt = 0;
5705		- for (i = 0; i < dev->num_channels; i++) {
5706		- stream = &dev->stream[i];
5707		- if (stream->state == RKCIF_STATE_STREAMING)
5708		- timer->last_buf_wakeup_cnt[stream->id] = stream->frame_idx;
5709		- }
5710		- spin_unlock_irqrestore(&timer->csi2_err_lock, flags);
	9392	+ spin_lock_irqsave(&timer->timer_lock, flags);
	9393	+ timer->is_running = false;
	9394	+ timer->is_triggered = false;
	9395	+ timer->csi2_err_cnt_odd = 0;
	9396	+ timer->csi2_err_cnt_even = 0;
	9397	+ timer->csi2_err_fs_fe_cnt = 0;
	9398	+ timer->notifer_called_cnt = 0;
	9399	+ for (i = 0; i < dev->num_channels; i++) {
	9400	+ stream = &dev->stream[i];
	9401	+ if (stream->state == RKCIF_STATE_STREAMING)
	9402	+ timer->last_buf_wakeup_cnt[stream->id] = stream->buf_wake_up_cnt;
5711	9403	}
5712		- if (hw_timer->is_reset_by_user) {
5713		- hw->reset_info.is_need_reset = 1;
5714		- hw->reset_info.reset_src = hw_timer->reset_src;
	9404	+ spin_unlock_irqrestore(&timer->timer_lock, flags);
	9405	+ if (timer->is_ctrl_by_user) {
	9406	+ rkcif_send_reset_event(dev, timer->reset_src);
5715	9407	} else {
5716		- dev->reset_work.reset_src = hw_timer->reset_src;
5717		- if (schedule_work(&dev->reset_work.work)) {
	9408	+ if (!schedule_work(&dev->reset_work.work))
5718	9409	v4l2_info(&dev->v4l2_dev,
5719		- "schedule reset work successfully\n");
5720		- } else {
5721		- v4l2_info(&dev->v4l2_dev,
5722		- "schedule reset work failed\n");
5723		- }
	9410	+ "schedule reset work failed\n");
	9411	+ dev->reset_work.reset_src = timer->reset_src;
5724	9412	}
5725	9413	}
5726	9414
5727	9415	static int rkcif_detect_reset_event(struct rkcif_stream *stream,
5728	9416	struct rkcif_timer *timer,
5729		- int *check_cnt,
	9417	+ int check_cnt,
5730	9418	bool *is_mod_timer)
5731	9419	{
5732	9420	struct rkcif_device *dev = stream->cifdev;
5733	9421	struct rkcif_sensor_info *terminal_sensor = &dev->terminal_sensor;
5734		- struct rkcif_hw_timer *hw_timer = &dev->hw_dev->hw_timer;
	9422	+ unsigned long flags;
5735	9423	int ret, is_reset = 0;
5736	9424	struct rkmodule_vicap_reset_info rst_info;
5737	9425
5738		- v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev,
5739		- "info: frame end still update(%d, %d), detect cnt: %d, mode:%d check_cnt:%d\n",
5740		- timer->last_buf_wakeup_cnt[stream->id], stream->frame_idx,
5741		- hw_timer->run_cnt, hw_timer->monitor_mode, *check_cnt);
	9426	+ if (timer->last_buf_wakeup_cnt[stream->id] < stream->buf_wake_up_cnt &&
	9427	+ check_cnt == 0) {
5742	9428
5743		- if (timer->last_buf_wakeup_cnt[stream->id] < stream->frame_idx) {
5744		- *check_cnt += 1;
5745	9429	v4l2_dbg(1, rkcif_debug, &dev->v4l2_dev,
5746		- "info: frame end still update(%d, %d), detect cnt: %d, mode:%d\n",
	9430	+ "info: frame end still update(%d, %d) in detecting cnt:%d, mode:%d\n",
5747	9431	timer->last_buf_wakeup_cnt[stream->id], stream->frame_idx,
5748		- hw_timer->run_cnt, hw_timer->monitor_mode);
	9432	+ timer->run_cnt, timer->monitor_mode);
5749	9433
5750		- timer->last_buf_wakeup_cnt[stream->id] = stream->frame_idx;
	9434	+ timer->last_buf_wakeup_cnt[stream->id] = stream->buf_wake_up_cnt;
5751	9435
5752		- if (hw_timer->monitor_mode == RKCIF_MONITOR_MODE_HOTPLUG) {
	9436	+ if (stream->frame_idx > 2)
	9437	+ rkcif_is_reduced_frame_rate(dev);
	9438	+
	9439	+ if (timer->monitor_mode == RKCIF_MONITOR_MODE_HOTPLUG) {
5753	9440	ret = v4l2_subdev_call(terminal_sensor->sd,
5754	9441	core, ioctl,
5755	9442	RKMODULE_GET_VICAP_RST_INFO,
..	..	@@ -5759,144 +9446,139 @@
5759	9446	else
5760	9447	is_reset = rst_info.is_reset;
5761	9448	rst_info.is_reset = 0;
5762		- hw_timer->reset_src = RKCIF_RESET_SRC_ERR_HOTPLUG;
	9449	+ if (is_reset)
	9450	+ timer->reset_src = RKCIF_RESET_SRC_ERR_HOTPLUG;
5763	9451	v4l2_subdev_call(terminal_sensor->sd, core, ioctl,
5764	9452	RKMODULE_SET_VICAP_RST_INFO, &rst_info);
5765		- if (!is_reset && stream->cifdev->inf_id == RKCIF_MIPI_LVDS)
	9453	+ if (!is_reset) {
5766	9454	is_reset = rkcif_is_csi2_err_trigger_reset(timer);
5767		- } else if (hw_timer->monitor_mode == RKCIF_MONITOR_MODE_CONTINUE) {
5768		- if (stream->cifdev->inf_id == RKCIF_MIPI_LVDS)
5769		- is_reset = rkcif_is_csi2_err_trigger_reset(timer);
5770		- } else if (hw_timer->monitor_mode == RKCIF_MONITOR_MODE_TRIGGER) {
5771		- if (stream->cifdev->inf_id == RKCIF_MIPI_LVDS) {
5772		- is_reset = timer->is_csi2_err_occurred;
5773	9455	if (is_reset)
5774		- hw_timer->reset_src = RKCIF_RESET_SRC_ERR_CSI2;
5775		- timer->is_csi2_err_occurred = false;
	9456	+ timer->reset_src = RKCIF_RESET_SRC_ERR_CSI2;
5776	9457	}
	9458	+ } else if (timer->monitor_mode == RKCIF_MONITOR_MODE_CONTINUE) {
	9459	+ is_reset = rkcif_is_csi2_err_trigger_reset(timer);
	9460	+ } else if (timer->monitor_mode == RKCIF_MONITOR_MODE_TRIGGER) {
	9461	+ is_reset = timer->is_csi2_err_occurred;
	9462	+ if (is_reset)
	9463	+ timer->reset_src = RKCIF_RESET_SRC_ERR_CSI2;
	9464	+ timer->is_csi2_err_occurred = false;
5777	9465	}
5778	9466
5779	9467	if (is_reset) {
5780		- rkcif_init_reset_work(hw_timer);
	9468	+ rkcif_init_reset_work(timer);
5781	9469	return is_reset;
5782	9470	}
5783		- *is_mod_timer = true;
5784		- } else if (timer->last_buf_wakeup_cnt[stream->id] == stream->frame_idx) {
5785		- bool is_loss_stream = false;
5786	9471
5787		- *check_cnt += 1;
5788		- if (hw_timer->run_cnt > 4)
5789		- is_loss_stream = rkcif_is_stream_stop_output(stream);
5790		-
5791		- if (is_loss_stream) {
5792		- v4l2_info(&dev->v4l2_dev,
5793		- "do reset work due to frame end is stopped, run_cnt:%d\n",
5794		- hw_timer->run_cnt);
5795		-
5796		- hw_timer->reset_src = RKICF_RESET_SRC_ERR_CUTOFF;
5797		- is_reset = true;
5798		- rkcif_init_reset_work(hw_timer);
	9472	+ if (timer->monitor_mode == RKCIF_MONITOR_MODE_CONTINUE \|\|
	9473	+ timer->monitor_mode == RKCIF_MONITOR_MODE_HOTPLUG) {
	9474	+ if (timer->run_cnt == timer->max_run_cnt)
	9475	+ timer->run_cnt = 0x0;
	9476	+ *is_mod_timer = true;
5799	9477	} else {
	9478	+ if (timer->run_cnt <= timer->max_run_cnt) {
	9479	+ *is_mod_timer = true;
	9480	+ } else {
	9481	+ spin_lock_irqsave(&timer->timer_lock, flags);
	9482	+ timer->is_triggered = false;
	9483	+ timer->is_running = false;
	9484	+ spin_unlock_irqrestore(&timer->timer_lock, flags);
	9485	+ v4l2_info(&dev->v4l2_dev, "stop reset detecting!\n");
	9486	+ }
	9487	+ }
	9488	+ } else if (timer->last_buf_wakeup_cnt[stream->id] == stream->buf_wake_up_cnt) {
	9489	+
	9490	+ bool is_reduced = false;
	9491	+
	9492	+ if (stream->frame_idx > 2)
	9493	+ is_reduced = rkcif_is_reduced_frame_rate(dev);
	9494	+ else if (timer->run_cnt < 20)
	9495	+ is_reduced = true;
	9496	+
	9497	+ if (is_reduced) {
5800	9498	*is_mod_timer = true;
5801	9499	v4l2_dbg(3, rkcif_debug, &dev->v4l2_dev, "%s fps is reduced\n", __func__);
	9500	+ } else {
	9501	+
	9502	+ v4l2_info(&dev->v4l2_dev,
	9503	+ "do reset work due to frame end is stopped, run_cnt:%d\n",
	9504	+ timer->run_cnt);
	9505	+
	9506	+ timer->reset_src = RKICF_RESET_SRC_ERR_CUTOFF;
	9507	+ rkcif_init_reset_work(timer);
	9508	+ is_reset = true;
5802	9509	}
5803	9510	}
5804	9511
5805		- return is_reset;
5806		-
5807		-}
5808		-
5809		-static int rkcif_dvp_err_trigger_reset(struct rkcif_device *dev)
5810		-{
5811		- int is_reset = 0;
5812		-
5813		- if (dev->irq_stats.dvp_overflow_cnt) {
5814		- dev->irq_stats.dvp_overflow_cnt = 0;
5815		- is_reset = 1;
5816		- }
5817		- return is_reset;
5818		-}
5819		-
5820		-static int rkcif_detect_reset_event_all_dev(struct rkcif_device *dev,
5821		- int *check_cnt,
5822		- bool *is_mod_timer)
5823		-{
5824		- struct rkcif_timer *timer = &dev->reset_watchdog_timer;
5825		- struct rkcif_stream *stream = NULL;
5826		- int i = 0;
5827		- int is_reset = 0;
5828		- int check_cnt_local = 0;
5829		-
5830		- for (i = 0; i < dev->num_channels; i++) {
5831		- stream = &dev->stream[i];
5832		- if (stream->state == RKCIF_STATE_STREAMING) {
5833		- is_reset = rkcif_detect_reset_event(stream,
5834		- timer,
5835		- &check_cnt_local,
5836		- is_mod_timer);
5837		- if (is_reset)
5838		- break;
5839		- }
5840		- }
5841		- if (!is_reset && dev->inf_id == RKCIF_DVP)
5842		- is_reset = rkcif_dvp_err_trigger_reset(dev);
5843		-
5844		- if (check_cnt_local)
5845		- *check_cnt += 1;
5846	9512	return is_reset;
5847	9513
5848	9514	}
5849	9515
5850	9516	void rkcif_reset_watchdog_timer_handler(struct timer_list *t)
5851	9517	{
5852		- struct rkcif_hw_timer *hw_timer = container_of(t, struct rkcif_hw_timer, timer);
5853		- struct rkcif_hw *hw = container_of(hw_timer,
5854		- struct rkcif_hw,
5855		- hw_timer);
5856		- struct rkcif_device *dev = NULL;
	9518	+ struct rkcif_timer *timer = container_of(t, struct rkcif_timer, timer);
	9519	+ struct rkcif_device *dev = container_of(timer,
	9520	+ struct rkcif_device,
	9521	+ reset_watchdog_timer);
	9522	+ struct rkcif_stream *stream = NULL;
5857	9523	unsigned long flags;
5858	9524	unsigned int i;
5859	9525	int is_reset = 0;
5860	9526	int check_cnt = 0;
5861	9527	bool is_mod_timer = false;
5862	9528
5863		- for (i = 0; i < hw->dev_num; i++) {
5864		- dev = hw->cif_dev[i];
5865		- is_reset = rkcif_detect_reset_event_all_dev(dev,
5866		- &check_cnt,
	9529	+ for (i = 0; i < dev->num_channels; i++) {
	9530	+ stream = &dev->stream[i];
	9531	+ if (stream->state == RKCIF_STATE_STREAMING) {
	9532	+ is_reset = rkcif_detect_reset_event(stream,
	9533	+ timer,
	9534	+ check_cnt,
5867	9535	&is_mod_timer);
5868		- if (is_reset)
5869		- break;
5870		-
	9536	+ check_cnt++;
	9537	+ if (is_reset)
	9538	+ break;
	9539	+ }
5871	9540	}
5872		-
5873	9541	if (!is_reset && is_mod_timer)
5874		- mod_timer(&hw_timer->timer, jiffies + hw_timer->cycle_jif);
	9542	+ mod_timer(&timer->timer, jiffies + timer->cycle);
5875	9543
5876		- hw_timer->run_cnt += 1;
	9544	+ timer->run_cnt += 1;
5877	9545
5878		- if (!check_cnt && !is_reset) {
5879		- spin_lock_irqsave(&hw_timer->timer_lock, flags);
5880		- hw_timer->is_running = false;
5881		- spin_unlock_irqrestore(&hw_timer->timer_lock, flags);
	9546	+ if (!check_cnt) {
	9547	+ spin_lock_irqsave(&timer->timer_lock, flags);
	9548	+ timer->is_triggered = false;
	9549	+ timer->is_running = false;
	9550	+ spin_unlock_irqrestore(&timer->timer_lock, flags);
5882	9551
5883		- dev_info(hw->dev,
5884		- "all stream is stopped, stop reset detect!\n");
	9552	+ v4l2_info(&dev->v4l2_dev,
	9553	+ "all stream is stopped, stop reset detect!\n");
5885	9554	}
5886	9555	}
5887	9556
5888	9557	int rkcif_reset_notifier(struct notifier_block *nb,
5889	9558	unsigned long action, void *data)
5890	9559	{
5891		- struct rkcif_device *dev = container_of(nb, struct rkcif_device, reset_notifier);
5892		- struct rkcif_timer *timer = &dev->reset_watchdog_timer;
5893		- struct rkcif_hw_timer *hw_timer = &dev->hw_dev->hw_timer;
	9560	+ struct rkcif_hw *hw = container_of(nb, struct rkcif_hw, reset_notifier);
	9561	+ struct rkcif_device *dev = NULL;
	9562	+ struct rkcif_timer *timer = NULL;
5894	9563	unsigned long flags, val;
	9564	+ u32 *csi_idx = data;
	9565	+ int i = 0;
	9566	+ bool is_match_dev = false;
5895	9567
5896		- if (hw_timer->is_running) {
	9568	+ for (i = 0; i < hw->dev_num; i++) {
	9569	+ dev = hw->cif_dev[i];
	9570	+ if (*csi_idx == dev->csi_host_idx) {
	9571	+ is_match_dev = true;
	9572	+ break;
	9573	+ }
	9574	+ }
	9575	+ if (!is_match_dev)
	9576	+ return -EINVAL;
	9577	+ timer = &dev->reset_watchdog_timer;
	9578	+ if (timer->is_running) {
5897	9579	val = action & CSI2_ERR_COUNT_ALL_MASK;
5898	9580	spin_lock_irqsave(&timer->csi2_err_lock, flags);
5899		- if ((val % hw_timer->err_ref_cnt) == 0) {
	9581	+ if ((val % timer->csi2_err_ref_cnt) == 0) {
5900	9582	timer->notifer_called_cnt++;
5901	9583	if ((timer->notifer_called_cnt % 2) == 0)
5902	9584	timer->csi2_err_cnt_even = val;
..	..	@@ -5914,7 +9596,12 @@
5914	9596	static void rkcif_modify_line_int(struct rkcif_stream *stream, bool en)
5915	9597	{
5916	9598	struct rkcif_device *cif_dev = stream->cifdev;
	9599	+ u32 line_intr_en = 0;
5917	9600
	9601	+ if (cif_dev->chip_id >= CHIP_RK3588_CIF)
	9602	+ line_intr_en = CSI_LINE_INTEN_RK3588(stream->id);
	9603	+ else
	9604	+ line_intr_en = CSI_LINE_INTEN(stream->id);
5918	9605	if (en) {
5919	9606	if (cif_dev->wait_line_bak != cif_dev->wait_line) {
5920	9607	cif_dev->wait_line_bak = cif_dev->wait_line;
..	..	@@ -5924,44 +9611,73 @@
5924	9611	cif_dev->wait_line << 16 \| cif_dev->wait_line);
5925	9612	}
5926	9613	rkcif_write_register_or(cif_dev, CIF_REG_MIPI_LVDS_INTEN,
5927		- CSI_LINE_INTEN(stream->id));
	9614	+ line_intr_en);
	9615	+ stream->is_line_inten = true;
5928	9616	} else {
5929	9617	rkcif_write_register_and(cif_dev, CIF_REG_MIPI_LVDS_INTEN,
5930		- ~(CSI_LINE_INTEN(stream->id)));
	9618	+ ~line_intr_en);
5931	9619	}
5932	9620	}
5933	9621
5934	9622	static void rkcif_detect_wake_up_mode_change(struct rkcif_stream *stream)
5935	9623	{
5936	9624	struct rkcif_device *cif_dev = stream->cifdev;
	9625	+ struct sditf_priv *priv = cif_dev->sditf[0];
	9626	+ bool is_change = false;
	9627	+ int ch = 0;
	9628	+ int i = 0;
	9629	+
	9630	+ if (!priv \|\| priv->mode.rdbk_mode == RKISP_VICAP_ONLINE)
	9631	+ return;
	9632	+
	9633	+ if ((cif_dev->hdr.hdr_mode == NO_HDR \|\| cif_dev->hdr.hdr_mode == HDR_COMPR) &&
	9634	+ stream->id == RKCIF_STREAM_MIPI_ID0) {
	9635	+ if (cif_dev->wait_line != cif_dev->wait_line_cache)
	9636	+ cif_dev->wait_line = cif_dev->wait_line_cache;
	9637	+ } else if (cif_dev->hdr.hdr_mode == HDR_X2 && stream->id == RKCIF_STREAM_MIPI_ID1) {
	9638	+ if (cif_dev->wait_line != cif_dev->wait_line_cache)
	9639	+ cif_dev->wait_line = cif_dev->wait_line_cache;
	9640	+ } else if (cif_dev->hdr.hdr_mode == HDR_X3 && stream->id == RKCIF_STREAM_MIPI_ID2) {
	9641	+ if (cif_dev->wait_line != cif_dev->wait_line_cache)
	9642	+ cif_dev->wait_line = cif_dev->wait_line_cache;
	9643	+ }
5937	9644
5938	9645	if (cif_dev->wait_line && (!stream->is_line_wake_up)) {
	9646	+ is_change = true;
5939	9647	stream->is_line_wake_up = true;
5940	9648	if (stream->frame_phase == CIF_CSI_FRAME0_READY)
5941	9649	stream->line_int_cnt = 1;
5942	9650	else if (stream->frame_phase == CIF_CSI_FRAME1_READY)
5943	9651	stream->line_int_cnt = 0;
	9652	+ if (cif_dev->hdr.hdr_mode == HDR_X2) {
	9653	+ cif_dev->stream[0].is_line_wake_up = true;
	9654	+ cif_dev->stream[0].line_int_cnt = stream->line_int_cnt;
	9655	+ } else if (cif_dev->hdr.hdr_mode == HDR_X3) {
	9656	+ cif_dev->stream[0].is_line_wake_up = true;
	9657	+ cif_dev->stream[1].is_line_wake_up = true;
	9658	+ cif_dev->stream[0].line_int_cnt = stream->line_int_cnt;
	9659	+ cif_dev->stream[1].line_int_cnt = stream->line_int_cnt;
	9660	+ }
5944	9661	} else if ((cif_dev->wait_line == 0) && stream->is_line_wake_up) {
5945	9662	stream->is_line_wake_up = false;
5946	9663	}
5947	9664	if (stream->is_line_wake_up) {
5948		- rkcif_modify_line_int(stream, true);
5949		- stream->is_line_inten = true;
5950		- }
5951		-
5952		- if (cif_dev->hdr.mode == NO_HDR && stream->id == RKCIF_STREAM_MIPI_ID0) {
5953		- if (cif_dev->wait_line != cif_dev->wait_line_cache)
5954		- cif_dev->wait_line = cif_dev->wait_line_cache;
5955		- } else if (cif_dev->hdr.mode == HDR_X2 && stream->id == RKCIF_STREAM_MIPI_ID1) {
5956		- if (cif_dev->wait_line != cif_dev->wait_line_cache)
5957		- cif_dev->wait_line = cif_dev->wait_line_cache;
5958		- } else if (cif_dev->hdr.mode == HDR_X3 && stream->id == RKCIF_STREAM_MIPI_ID2) {
5959		- if (cif_dev->wait_line != cif_dev->wait_line_cache)
5960		- cif_dev->wait_line = cif_dev->wait_line_cache;
	9665	+ if (is_change) {
	9666	+ if (cif_dev->hdr.hdr_mode == HDR_X2)
	9667	+ ch = 2;
	9668	+ else if (cif_dev->hdr.hdr_mode == HDR_X3)
	9669	+ ch = 3;
	9670	+ else
	9671	+ ch = 1;
	9672	+ for (i = 0; i < ch; i++)
	9673	+ rkcif_modify_line_int(&cif_dev->stream[i], true);
	9674	+ } else {
	9675	+ rkcif_modify_line_int(stream, true);
	9676	+ }
5961	9677	}
5962	9678	}
5963	9679
5964		-static u32 rkisp_mbus_pixelcode_to_v4l2(u32 pixelcode)
	9680	+u32 rkcif_mbus_pixelcode_to_v4l2(u32 pixelcode)
5965	9681	{
5966	9682	u32 pixelformat;
5967	9683
..	..	@@ -6050,13 +9766,14 @@
6050	9766	v4l2_subdev_call(cif_dev->terminal_sensor.sd, pad, get_fmt, NULL, &fmt);
6051	9767
6052	9768	memset(&pixm, 0, sizeof(pixm));
6053		- pixm.pixelformat = rkisp_mbus_pixelcode_to_v4l2(fmt.format.code);
	9769	+ pixm.pixelformat = rkcif_mbus_pixelcode_to_v4l2(fmt.format.code);
6054	9770	pixm.width = fmt.format.width;
6055	9771	pixm.height = fmt.format.height;
6056	9772
6057	9773	memset(&input_sel, 0, sizeof(input_sel));
6058	9774	input_sel.pad = i;
6059	9775	input_sel.target = V4L2_SEL_TGT_CROP_BOUNDS;
	9776	+ input_sel.which = V4L2_SUBDEV_FORMAT_ACTIVE;
6060	9777	ret = v4l2_subdev_call(cif_dev->terminal_sensor.sd,
6061	9778	pad, get_selection, NULL,
6062	9779	&input_sel);
..	..	@@ -6069,12 +9786,899 @@
6069	9786	}
6070	9787	}
6071	9788
	9789	+void rkcif_enable_dma_capture(struct rkcif_stream *stream, bool is_only_enable)
	9790	+{
	9791	+ struct rkcif_device *cif_dev = stream->cifdev;
	9792	+ struct v4l2_mbus_config *mbus_cfg = &cif_dev->active_sensor->mbus;
	9793	+ struct csi_channel_info *channel = &cif_dev->channels[stream->id];
	9794	+ u32 val = 0;
	9795	+
	9796	+ if (stream->buf_owner == RKCIF_DMAEN_BY_ISP)
	9797	+ stream->buf_owner = RKCIF_DMAEN_BY_ISP_TO_VICAP;
	9798	+
	9799	+ if (stream->dma_en) {
	9800	+ stream->dma_en \|= stream->to_en_dma;
	9801	+ stream->to_en_dma = 0;
	9802	+ return;
	9803	+ }
	9804	+
	9805	+ stream->dma_en \|= stream->to_en_dma;
	9806	+ if (!is_only_enable) {
	9807	+ if (stream->to_en_dma == RKCIF_DMAEN_BY_VICAP) {
	9808	+ rkcif_assign_new_buffer_pingpong(stream,
	9809	+ RKCIF_YUV_ADDR_STATE_INIT,
	9810	+ stream->id);
	9811	+ rkcif_write_register(cif_dev, get_reg_index_of_frm0_y_vlw(stream->id),
	9812	+ channel->virtual_width);
	9813	+ } else if (stream->to_en_dma == RKCIF_DMAEN_BY_ISP) {
	9814	+ rkcif_assign_new_buffer_pingpong_toisp(stream,
	9815	+ RKCIF_YUV_ADDR_STATE_INIT,
	9816	+ stream->id);
	9817	+ }
	9818	+ }
	9819	+ if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
	9820	+ mbus_cfg->type == V4L2_MBUS_CSI2_CPHY)
	9821	+ rkcif_write_register_or(cif_dev, CIF_REG_MIPI_LVDS_CTRL, 0x00010000);
	9822	+ else
	9823	+ rkcif_write_register_or(cif_dev, CIF_REG_DVP_CTRL, 0x00010000);
	9824	+ if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
	9825	+ mbus_cfg->type == V4L2_MBUS_CSI2_CPHY) {
	9826	+ val = rkcif_read_register(cif_dev, get_reg_index_of_id_ctrl0(stream->id));
	9827	+ if (!stream->is_compact)
	9828	+ val \|= CSI_WRDDR_TYPE_RAW_UNCOMPACT;
	9829	+ else
	9830	+ val &= ~CSI_WRDDR_TYPE_RAW_UNCOMPACT;
	9831	+ val \|= CSI_DMA_ENABLE;
	9832	+ rkcif_write_register(cif_dev, get_reg_index_of_id_ctrl0(stream->id), val);
	9833	+ } else if (mbus_cfg->type == V4L2_MBUS_CCP2) {
	9834	+ val = rkcif_read_register(cif_dev, get_reg_index_of_lvds_id_ctrl0(stream->id));
	9835	+ if (!stream->is_compact)
	9836	+ val \|= CSI_WRDDR_TYPE_RAW_UNCOMPACT << 17;
	9837	+ else
	9838	+ val &= ~(CSI_WRDDR_TYPE_RAW_UNCOMPACT << 17);
	9839	+ val \|= LVDS_DMAEN_RV1106;
	9840	+ rkcif_write_register(cif_dev, get_reg_index_of_lvds_id_ctrl0(stream->id), val);
	9841	+ } else {
	9842	+ val = rkcif_read_register(cif_dev, CIF_REG_DVP_FOR);
	9843	+ if (!stream->is_compact)
	9844	+ val \|= CSI_WRDDR_TYPE_RAW_UNCOMPACT << 11;
	9845	+ else
	9846	+ val &= ~(CSI_WRDDR_TYPE_RAW_UNCOMPACT << 11);
	9847	+ rkcif_write_register(cif_dev, CIF_REG_DVP_FOR, val);
	9848	+ val = rkcif_read_register(cif_dev, CIF_REG_DVP_CTRL);
	9849	+ if (cif_dev->chip_id == CHIP_RK3588_CIF)
	9850	+ val \|= DVP_DMA_EN;
	9851	+ else if (cif_dev->chip_id == CHIP_RV1106_CIF)
	9852	+ val \|= DVP_SW_DMA_EN(stream->id);
	9853	+ rkcif_write_register(cif_dev, CIF_REG_DVP_CTRL, val);
	9854	+ }
	9855	+
	9856	+ stream->to_en_dma = 0;
	9857	+}
	9858	+
	9859	+static int rkcif_stop_dma_capture(struct rkcif_stream *stream)
	9860	+{
	9861	+ struct rkcif_device *cif_dev = stream->cifdev;
	9862	+ struct v4l2_mbus_config *mbus_cfg = &cif_dev->active_sensor->mbus;
	9863	+ u32 val = 0;
	9864	+
	9865	+ if (stream->buf_replace_cnt)
	9866	+ return -EINVAL;
	9867	+
	9868	+ stream->dma_en &= ~stream->to_stop_dma;
	9869	+
	9870	+ if (stream->dma_en != 0) {
	9871	+ if (stream->dma_en & RKCIF_DMAEN_BY_ISP)
	9872	+ stream->buf_owner = RKCIF_DMAEN_BY_ISP;
	9873	+ stream->to_stop_dma = 0;
	9874	+ return 0;
	9875	+ }
	9876	+
	9877	+ if (mbus_cfg->type == V4L2_MBUS_CSI2_DPHY \|\|
	9878	+ mbus_cfg->type == V4L2_MBUS_CSI2_CPHY) {
	9879	+ val = rkcif_read_register(cif_dev, get_reg_index_of_id_ctrl0(stream->id));
	9880	+ val &= ~CSI_DMA_ENABLE;
	9881	+ if (stream->is_stop_capture) {
	9882	+ val &= ~CSI_ENABLE_CAPTURE;
	9883	+ stream->is_stop_capture = false;
	9884	+ }
	9885	+ rkcif_write_register(cif_dev, get_reg_index_of_id_ctrl0(stream->id), val);
	9886	+ } else if (mbus_cfg->type == V4L2_MBUS_CCP2) {
	9887	+ val = rkcif_read_register(cif_dev, get_reg_index_of_lvds_id_ctrl0(stream->id));
	9888	+ val &= ~LVDS_DMAEN_RV1106;
	9889	+ if (stream->is_stop_capture) {
	9890	+ val &= ~ENABLE_CAPTURE;
	9891	+ stream->is_stop_capture = false;
	9892	+ }
	9893	+ rkcif_write_register(cif_dev, get_reg_index_of_lvds_id_ctrl0(stream->id), val);
	9894	+ } else {
	9895	+ val = rkcif_read_register(cif_dev, CIF_REG_DVP_CTRL);
	9896	+ if (cif_dev->chip_id == CHIP_RK3588_CIF)
	9897	+ val &= ~DVP_DMA_EN;
	9898	+ else if (cif_dev->chip_id == CHIP_RV1106_CIF)
	9899	+ val &= ~(DVP_SW_DMA_EN(stream->id));
	9900	+ if (stream->is_stop_capture) {
	9901	+ val &= ~ENABLE_CAPTURE;
	9902	+ stream->is_stop_capture = false;
	9903	+ }
	9904	+ rkcif_write_register(cif_dev, CIF_REG_DVP_CTRL, val);
	9905	+ }
	9906	+ stream->to_stop_dma = 0;
	9907	+ v4l2_dbg(4, rkcif_debug, &cif_dev->v4l2_dev,
	9908	+ "stream[%d] replace_cnt %d, y_addr 0x%x, 0x%x\n",
	9909	+ stream->id, stream->buf_replace_cnt,
	9910	+ rkcif_read_register(cif_dev, get_reg_index_of_frm0_y_addr(stream->id)),
	9911	+ rkcif_read_register(cif_dev, get_reg_index_of_frm1_y_addr(stream->id)));
	9912	+ return 0;
	9913	+}
	9914	+
	9915	+static void rkcif_send_sof(struct rkcif_device *cif_dev)
	9916	+{
	9917	+ struct v4l2_mbus_config *mbus = &cif_dev->active_sensor->mbus;
	9918	+ struct csi2_dev *csi;
	9919	+
	9920	+ if (mbus->type == V4L2_MBUS_CSI2_DPHY \|\|
	9921	+ mbus->type == V4L2_MBUS_CSI2_CPHY) {
	9922	+ csi = container_of(cif_dev->active_sensor->sd, struct csi2_dev, sd);
	9923	+ rkcif_csi2_event_inc_sof(csi);
	9924	+ } else if (mbus->type == V4L2_MBUS_CCP2) {
	9925	+ rkcif_lvds_event_inc_sof(cif_dev);
	9926	+ } else {
	9927	+ rkcif_dvp_event_inc_sof(cif_dev);
	9928	+ }
	9929	+}
	9930	+
	9931	+static int rkcif_g_toisp_ch(unsigned int intstat_glb, int index)
	9932	+{
	9933	+ if (intstat_glb & TOISP_END_CH0(index))
	9934	+ return RKCIF_TOISP_CH0;
	9935	+ if (intstat_glb & TOISP_END_CH1(index))
	9936	+ return RKCIF_TOISP_CH1;
	9937	+ if (intstat_glb & TOISP_END_CH2(index))
	9938	+ return RKCIF_TOISP_CH2;
	9939	+
	9940	+ return -EINVAL;
	9941	+}
	9942	+
	9943	+static int rkcif_g_toisp_fs(unsigned int intstat_glb, int index)
	9944	+{
	9945	+ if (intstat_glb & TOISP_FS_CH0(index))
	9946	+ return RKCIF_TOISP_CH0;
	9947	+ if (intstat_glb & TOISP_FS_CH1(index))
	9948	+ return RKCIF_TOISP_CH1;
	9949	+ if (intstat_glb & TOISP_FS_CH2(index))
	9950	+ return RKCIF_TOISP_CH2;
	9951	+
	9952	+ return -EINVAL;
	9953	+}
	9954	+
	9955	+static void rkcif_toisp_check_stop_status(struct sditf_priv *priv,
	9956	+ unsigned int intstat_glb,
	9957	+ int index)
	9958	+{
	9959	+ int ch = 0;
	9960	+ struct rkcif_stream *stream;
	9961	+ int src_id = 0;
	9962	+ int i = 0;
	9963	+ u32 val = 0;
	9964	+ u64 cur_time = 0;
	9965	+
	9966	+ for (i = 0; i < TOISP_CH_MAX; i++) {
	9967	+ ch = rkcif_g_toisp_ch(intstat_glb, index);
	9968	+ if (ch >= 0) {
	9969	+ src_id = priv->toisp_inf.ch_info[ch].id;
	9970	+ if (src_id == 24)
	9971	+ stream = &priv->cif_dev->stream[0];
	9972	+ else
	9973	+ stream = &priv->cif_dev->stream[src_id % 4];
	9974	+ if (stream->stopping) {
	9975	+ v4l2_dbg(3, rkcif_debug, &priv->cif_dev->v4l2_dev,
	9976	+ "stream[%d] stop\n",
	9977	+ stream->id);
	9978	+ rkcif_stream_stop(stream);
	9979	+ stream->stopping = false;
	9980	+ wake_up(&stream->wq_stopped);
	9981	+ }
	9982	+
	9983	+ if (stream->cifdev->chip_id >= CHIP_RV1106_CIF)
	9984	+ rkcif_modify_frame_skip_config(stream);
	9985	+ if (stream->cifdev->rdbk_debug &&
	9986	+ stream->frame_idx < 15)
	9987	+ v4l2_info(&priv->cif_dev->v4l2_dev,
	9988	+ "stream[%d] toisp fe %d\n",
	9989	+ stream->id,
	9990	+ stream->frame_idx - 1);
	9991	+
	9992	+ switch (ch) {
	9993	+ case RKCIF_TOISP_CH0:
	9994	+ val = TOISP_END_CH0(index);
	9995	+ intstat_glb = intstat_glb & (~val);
	9996	+ break;
	9997	+ case RKCIF_TOISP_CH1:
	9998	+ val = TOISP_END_CH1(index);
	9999	+ intstat_glb = intstat_glb & (~val);
	10000	+ break;
	10001	+ case RKCIF_TOISP_CH2:
	10002	+ val = TOISP_END_CH2(index);
	10003	+ intstat_glb = intstat_glb & (~val);
	10004	+ break;
	10005	+ default:
	10006	+ break;
	10007	+ }
	10008	+ }
	10009	+ ch = rkcif_g_toisp_fs(intstat_glb, index);
	10010	+ if (ch >= 0) {
	10011	+ src_id = priv->toisp_inf.ch_info[ch].id;
	10012	+ if (src_id == 24)
	10013	+ stream = &priv->cif_dev->stream[0];
	10014	+ else
	10015	+ stream = &priv->cif_dev->stream[src_id % 4];
	10016	+ if (stream->id == 0)
	10017	+ rkcif_send_sof(stream->cifdev);
	10018	+ stream->frame_idx++;
	10019	+ cur_time = ktime_get_ns();
	10020	+ stream->readout.readout_time = cur_time - stream->readout.fs_timestamp;
	10021	+ stream->readout.fs_timestamp = cur_time;
	10022	+ if (stream->cifdev->rdbk_debug &&
	10023	+ stream->frame_idx < 15)
	10024	+ v4l2_info(&priv->cif_dev->v4l2_dev,
	10025	+ "stream[%d] toisp sof seq %d\n",
	10026	+ stream->id,
	10027	+ stream->frame_idx - 1);
	10028	+ if (stream->to_en_dma)
	10029	+ rkcif_enable_dma_capture(stream, false);
	10030	+ if (stream->to_en_scale) {
	10031	+ stream->to_en_scale = false;
	10032	+ rkcif_scale_start(stream->scale_vdev);
	10033	+ }
	10034	+ switch (ch) {
	10035	+ case RKCIF_TOISP_CH0:
	10036	+ val = TOISP_FS_CH0(index);
	10037	+ intstat_glb = intstat_glb & (~val);
	10038	+ break;
	10039	+ case RKCIF_TOISP_CH1:
	10040	+ val = TOISP_FS_CH1(index);
	10041	+ intstat_glb = intstat_glb & (~val);
	10042	+ break;
	10043	+ case RKCIF_TOISP_CH2:
	10044	+ val = TOISP_FS_CH2(index);
	10045	+ intstat_glb = intstat_glb & (~val);
	10046	+ break;
	10047	+ default:
	10048	+ break;
	10049	+ }
	10050	+ }
	10051	+ }
	10052	+}
	10053	+
	10054	+void rkcif_irq_handle_toisp(struct rkcif_device *cif_dev, unsigned int intstat_glb)
	10055	+{
	10056	+ int i = 0;
	10057	+ bool to_check = false;
	10058	+ struct sditf_priv *priv = cif_dev->sditf[0];
	10059	+
	10060	+ if (!priv \|\| priv->mode.rdbk_mode != RKISP_VICAP_ONLINE)
	10061	+ return;
	10062	+
	10063	+ for (i = 0; i < 2; i++) {
	10064	+ if (priv->toisp_inf.link_mode == TOISP0 &&
	10065	+ i == 0) {
	10066	+ to_check = true;
	10067	+ } else if (priv->toisp_inf.link_mode == TOISP1 &&
	10068	+ i == 1) {
	10069	+ to_check = true;
	10070	+ } else if (priv->toisp_inf.link_mode == TOISP_UNITE &&
	10071	+ i == 1) {
	10072	+ to_check = true;
	10073	+ }
	10074	+ if (to_check)
	10075	+ rkcif_toisp_check_stop_status(priv, intstat_glb, i);
	10076	+ }
	10077	+}
	10078	+
	10079	+static int rkcif_check_group_sync_state(struct rkcif_device *cif_dev)
	10080	+{
	10081	+ struct rkcif_stream *detect_stream = &cif_dev->stream[0];
	10082	+ struct rkcif_stream *next_stream = NULL;
	10083	+ struct rkcif_hw *hw = cif_dev->hw_dev;
	10084	+ u64 fs_interval = 0;
	10085	+ int i = 0;
	10086	+ int ret = 0;
	10087	+ struct rkcif_multi_sync_config *sync_config;
	10088	+
	10089	+ sync_config = &hw->sync_config[cif_dev->sync_cfg.group];
	10090	+ sync_config->sync_code \|= BIT(cif_dev->csi_host_idx);
	10091	+ v4l2_dbg(3, rkcif_debug, &cif_dev->v4l2_dev,
	10092	+ "sync code 0x%x, mask 0x%x, update 0x%x, cache 0x%x, timestamp %llu\n",
	10093	+ sync_config->sync_code,
	10094	+ sync_config->sync_mask,
	10095	+ sync_config->update_code,
	10096	+ sync_config->update_cache,
	10097	+ detect_stream->readout.fs_timestamp);
	10098	+
	10099	+ if (sync_config->sync_code != sync_config->sync_mask)
	10100	+ return -EINVAL;
	10101	+
	10102	+ for (i = 0; i < sync_config->dev_cnt; i++) {
	10103	+ if (sync_config->mode == RKCIF_MASTER_MASTER) {
	10104	+ if (i < sync_config->ext_master.count)
	10105	+ next_stream = &sync_config->ext_master.cif_dev[i]->stream
	10106	+ [0];
	10107	+ else
	10108	+ next_stream = &sync_config->int_master.cif_dev[0]->stream
	10109	+ [0];
	10110	+ } else if (sync_config->mode == RKCIF_MASTER_SLAVE) {
	10111	+ if (i < sync_config->slave.count)
	10112	+ next_stream = &sync_config->slave.cif_dev[i]->stream
	10113	+ [0];
	10114	+ else
	10115	+ next_stream = &sync_config->int_master.cif_dev[0]->stream
	10116	+ [0];
	10117	+ } else {
	10118	+ v4l2_err(&cif_dev->v4l2_dev,
	10119	+ "ERROR: invalid group sync mode\n");
	10120	+ ret = -EINVAL;
	10121	+ break;
	10122	+ }
	10123	+ if (detect_stream == next_stream)
	10124	+ continue;
	10125	+ fs_interval = abs(detect_stream->readout.fs_timestamp - next_stream->readout.fs_timestamp);
	10126	+ if (fs_interval > RKCIF_MAX_INTERVAL_NS) {
	10127	+ ret = -EINVAL;
	10128	+ break;
	10129	+ }
	10130	+ }
	10131	+ return ret;
	10132	+}
	10133	+
	10134	+static void rkcif_deal_sof(struct rkcif_device *cif_dev)
	10135	+{
	10136	+ struct rkcif_stream *detect_stream = &cif_dev->stream[0];
	10137	+ struct rkcif_hw *hw = cif_dev->hw_dev;
	10138	+ struct rkcif_device *tmp_dev = NULL;
	10139	+ unsigned long flags;
	10140	+ int i = 0;
	10141	+ int ret = 0;
	10142	+
	10143	+ if (cif_dev->chip_id < CHIP_RK3588_CIF)
	10144	+ detect_stream->fs_cnt_in_single_frame++;
	10145	+ spin_lock_irqsave(&detect_stream->fps_lock, flags);
	10146	+ detect_stream->readout.fs_timestamp = ktime_get_ns();
	10147	+ spin_unlock_irqrestore(&detect_stream->fps_lock, flags);
	10148	+
	10149	+ if (cif_dev->sync_cfg.type != RKCIF_NOSYNC_MODE) {
	10150	+ struct rkcif_multi_sync_config *sync_config;
	10151	+
	10152	+ sync_config = &hw->sync_config[cif_dev->sync_cfg.group];
	10153	+ ret = rkcif_check_group_sync_state(cif_dev);
	10154	+ if (!ret) {
	10155	+ sync_config->sync_code = 0;
	10156	+ sync_config->frame_idx++;
	10157	+ spin_lock_irqsave(&hw->group_lock, flags);
	10158	+ sync_config->update_cache = sync_config->sync_mask;
	10159	+ if (!sync_config->update_code) {
	10160	+ sync_config->update_code = sync_config->update_cache;
	10161	+ sync_config->update_cache = 0;
	10162	+ }
	10163	+ spin_unlock_irqrestore(&hw->group_lock, flags);
	10164	+ for (i = 0; i < sync_config->dev_cnt; i++) {
	10165	+ if (sync_config->mode == RKCIF_MASTER_MASTER) {
	10166	+ if (i < sync_config->ext_master.count)
	10167	+ tmp_dev = sync_config->ext_master.cif_dev[i];
	10168	+ else
	10169	+ tmp_dev = sync_config->int_master.cif_dev[0];
	10170	+ } else if (sync_config->mode == RKCIF_MASTER_SLAVE) {
	10171	+ if (i < sync_config->slave.count)
	10172	+ tmp_dev = sync_config->slave.cif_dev[i];
	10173	+ else
	10174	+ tmp_dev = sync_config->int_master.cif_dev[0];
	10175	+ } else {
	10176	+ v4l2_err(&cif_dev->v4l2_dev,
	10177	+ "ERROR: invalid group sync mode\n");
	10178	+ }
	10179	+ if (tmp_dev) {
	10180	+ rkcif_send_sof(tmp_dev);
	10181	+ tmp_dev->stream[0].frame_idx = sync_config->frame_idx;
	10182	+ }
	10183	+ }
	10184	+ }
	10185	+ } else {
	10186	+ if (!cif_dev->sditf[0] \|\| cif_dev->sditf[0]->mode.rdbk_mode) {
	10187	+ rkcif_send_sof(cif_dev);
	10188	+ detect_stream->frame_idx++;
	10189	+ }
	10190	+ if (detect_stream->cifdev->rdbk_debug &&
	10191	+ detect_stream->frame_idx < 15 &&
	10192	+ (!cif_dev->sditf[0] \|\| cif_dev->sditf[0]->mode.rdbk_mode))
	10193	+ v4l2_info(&cif_dev->v4l2_dev,
	10194	+ "stream[%d] sof %d %lld\n",
	10195	+ detect_stream->id,
	10196	+ detect_stream->frame_idx - 1,
	10197	+ ktime_get_ns());
	10198	+ }
	10199	+}
	10200	+
	10201	+unsigned int rkcif_irq_global(struct rkcif_device *cif_dev)
	10202	+{
	10203	+ unsigned int intstat_glb = 0;
	10204	+
	10205	+ intstat_glb = rkcif_read_register(cif_dev, CIF_REG_GLB_INTST);
	10206	+ if (intstat_glb)
	10207	+ v4l2_dbg(2, rkcif_debug, &cif_dev->v4l2_dev,
	10208	+ "intstat_glb 0x%x\n",
	10209	+ intstat_glb);
	10210	+ else
	10211	+ return intstat_glb;
	10212	+
	10213	+ if (intstat_glb & SCALE_TOISP_AXI0_ERR) {
	10214	+ v4l2_err(&cif_dev->v4l2_dev,
	10215	+ "ERROR: scale channel, AXI0 bus err intstat_glb:0x%x !!\n",
	10216	+ intstat_glb);
	10217	+ return 0;
	10218	+ }
	10219	+ if (intstat_glb & SCALE_TOISP_AXI1_ERR) {
	10220	+ v4l2_err(&cif_dev->v4l2_dev,
	10221	+ "ERROR: scale channel, AXI1 bus err intstat_glb:0x%x !!\n",
	10222	+ intstat_glb);
	10223	+ return 0;
	10224	+ }
	10225	+ rkcif_irq_handle_scale(cif_dev, intstat_glb);
	10226	+ return intstat_glb;
	10227	+}
	10228	+
	10229	+static bool rkcif_check_buffer_prepare(struct rkcif_stream *stream)
	10230	+{
	10231	+ struct rkcif_device *cif_dev = stream->cifdev;
	10232	+ unsigned long flags;
	10233	+ bool is_update = false;
	10234	+ struct rkcif_multi_sync_config *sync_config;
	10235	+
	10236	+ spin_lock_irqsave(&cif_dev->hw_dev->group_lock, flags);
	10237	+ sync_config = &cif_dev->hw_dev->sync_config[cif_dev->sync_cfg.group];
	10238	+ if (stream->id == 0 &&
	10239	+ sync_config->update_code & BIT(cif_dev->csi_host_idx)) {
	10240	+ is_update = true;
	10241	+ sync_config->update_code &= ~(BIT(cif_dev->csi_host_idx));
	10242	+ if (!sync_config->update_code &&
	10243	+ sync_config->update_cache) {
	10244	+ sync_config->update_code = sync_config->update_cache;
	10245	+ sync_config->update_cache = 0;
	10246	+ }
	10247	+ } else {
	10248	+ if (cif_dev->rdbk_buf[RDBK_L])
	10249	+ is_update = true;
	10250	+ }
	10251	+
	10252	+ spin_unlock_irqrestore(&cif_dev->hw_dev->group_lock, flags);
	10253	+ return is_update;
	10254	+}
	10255	+
	10256	+void rkcif_err_print_work(struct work_struct *work)
	10257	+{
	10258	+ struct rkcif_err_state_work *err_state_work = container_of(work,
	10259	+ struct rkcif_err_state_work,
	10260	+ work);
	10261	+ struct rkcif_device *dev = container_of(err_state_work,
	10262	+ struct rkcif_device,
	10263	+ err_state_work);
	10264	+ u32 err_state = 0;
	10265	+ int intstat = 0;
	10266	+ int lastline = 0;
	10267	+ int lastpixel = 0;
	10268	+ u64 cur_time = 0;
	10269	+ bool is_print = false;
	10270	+
	10271	+ cur_time = ktime_get_ns();
	10272	+ if (err_state_work->last_timestamp == 0) {
	10273	+ is_print = true;
	10274	+ } else {
	10275	+ if (cur_time - err_state_work->last_timestamp > 500000000)
	10276	+ is_print = true;
	10277	+ }
	10278	+ err_state_work->last_timestamp = cur_time;
	10279	+ err_state = err_state_work->err_state;
	10280	+ intstat = err_state_work->intstat;
	10281	+ lastline = err_state_work->lastline;
	10282	+ lastpixel = err_state_work->lastpixel;
	10283	+ if (err_state & RKCIF_ERR_ID0_NOT_BUF && is_print)
	10284	+ v4l2_err(&dev->v4l2_dev,
	10285	+ "stream[0] not active buffer, frame num %d, cnt %llu\n",
	10286	+ dev->stream[0].frame_idx, dev->irq_stats.not_active_buf_cnt[0]);
	10287	+ if (err_state & RKCIF_ERR_ID1_NOT_BUF && is_print)
	10288	+ v4l2_err(&dev->v4l2_dev,
	10289	+ "stream[1] not active buffer, frame num %d, cnt %llu\n",
	10290	+ dev->stream[1].frame_idx, dev->irq_stats.not_active_buf_cnt[1]);
	10291	+ if (err_state & RKCIF_ERR_ID2_NOT_BUF && is_print)
	10292	+ v4l2_err(&dev->v4l2_dev,
	10293	+ "stream[2] not active buffer, frame num %d, cnt %llu\n",
	10294	+ dev->stream[2].frame_idx, dev->irq_stats.not_active_buf_cnt[2]);
	10295	+ if (err_state & RKCIF_ERR_ID3_NOT_BUF && is_print)
	10296	+ v4l2_err(&dev->v4l2_dev,
	10297	+ "stream[3] not active buffer, frame num %d, cnt %llu\n",
	10298	+ dev->stream[3].frame_idx, dev->irq_stats.not_active_buf_cnt[3]);
	10299	+ if (err_state & RKCIF_ERR_ID0_TRIG_SIMULT && is_print)
	10300	+ v4l2_err(&dev->v4l2_dev,
	10301	+ "stream[0], frm0/frm1 end simultaneously,frm id:%d, cnt %llu\n",
	10302	+ dev->stream[0].frame_idx, dev->irq_stats.trig_simult_cnt[0]);
	10303	+ if (err_state & RKCIF_ERR_ID1_TRIG_SIMULT && is_print)
	10304	+ v4l2_err(&dev->v4l2_dev,
	10305	+ "stream[1], frm0/frm1 end simultaneously,frm id:%d, cnt %llu\n",
	10306	+ dev->stream[1].frame_idx, dev->irq_stats.trig_simult_cnt[1]);
	10307	+ if (err_state & RKCIF_ERR_ID2_TRIG_SIMULT && is_print)
	10308	+ v4l2_err(&dev->v4l2_dev,
	10309	+ "stream[2], frm0/frm1 end simultaneously,frm id:%d, cnt %llu\n",
	10310	+ dev->stream[2].frame_idx, dev->irq_stats.trig_simult_cnt[2]);
	10311	+ if (err_state & RKCIF_ERR_ID3_TRIG_SIMULT && is_print)
	10312	+ v4l2_err(&dev->v4l2_dev,
	10313	+ "stream[3], frm0/frm1 end simultaneously,frm id:%d, cnt %llu\n",
	10314	+ dev->stream[3].frame_idx, dev->irq_stats.trig_simult_cnt[3]);
	10315	+ if (err_state & RKCIF_ERR_SIZE)
	10316	+ v4l2_err(&dev->v4l2_dev,
	10317	+ "ERROR: csi size err, intstat:0x%x, lastline:0x%x, cnt %llu\n",
	10318	+ intstat, lastline, dev->irq_stats.csi_size_err_cnt);
	10319	+ if (err_state & RKCIF_ERR_OVERFLOW)
	10320	+ v4l2_err(&dev->v4l2_dev,
	10321	+ "ERROR: csi fifo overflow, intstat:0x%x, lastline:0x%x, cnt %llu\n",
	10322	+ intstat, lastline, dev->irq_stats.csi_overflow_cnt);
	10323	+ if (err_state & RKCIF_ERR_BANDWIDTH_LACK)
	10324	+ v4l2_err(&dev->v4l2_dev,
	10325	+ "ERROR: csi bandwidth lack, intstat:0x%x, lastline:0x%x, cnt %llu\n",
	10326	+ intstat, lastline, dev->irq_stats.csi_bwidth_lack_cnt);
	10327	+ if (err_state & RKCIF_ERR_ID0_MULTI_FS)
	10328	+ v4l2_err(&dev->v4l2_dev,
	10329	+ "ERR: multi fs in oneframe in id0, fs_num:%u\n",
	10330	+ dev->stream[0].fs_cnt_in_single_frame);
	10331	+ if (err_state & RKCIF_ERR_BUS)
	10332	+ v4l2_err(&dev->v4l2_dev, "dvp bus err, intstat 0x%x, last line 0x%x\n",
	10333	+ intstat, lastline);
	10334	+ if (err_state & RKCIF_ERR_PIXEL)
	10335	+ v4l2_err(&dev->v4l2_dev, "dvp pix err, intstat 0x%x, last pixel 0x%x\n",
	10336	+ intstat, lastpixel);
	10337	+ if (err_state & RKCIF_ERR_LINE)
	10338	+ v4l2_err(&dev->v4l2_dev, "dvp line err, intstat 0x%x, last line 0x%x\n",
	10339	+ intstat, lastline);
	10340	+}
	10341	+
	10342	+/* pingpong irq for rk3588 and next */
	10343	+void rkcif_irq_pingpong_v1(struct rkcif_device *cif_dev)
	10344	+{
	10345	+ struct rkcif_stream *stream;
	10346	+ struct rkcif_stream *detect_stream = &cif_dev->stream[0];
	10347	+ struct v4l2_mbus_config *mbus;
	10348	+ unsigned int intstat, i = 0xff;
	10349	+ unsigned long flags;
	10350	+ bool is_update = false;
	10351	+ int ret = 0;
	10352	+
	10353	+ if (!cif_dev->active_sensor)
	10354	+ return;
	10355	+
	10356	+ mbus = &cif_dev->active_sensor->mbus;
	10357	+ if (mbus->type == V4L2_MBUS_CSI2_DPHY \|\|
	10358	+ mbus->type == V4L2_MBUS_CSI2_CPHY \|\|
	10359	+ mbus->type == V4L2_MBUS_CCP2) {
	10360	+ int mipi_id;
	10361	+ u32 lastline = 0;
	10362	+
	10363	+ intstat = rkcif_read_register(cif_dev, CIF_REG_MIPI_LVDS_INTSTAT);
	10364	+ lastline = rkcif_read_register(cif_dev, CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID0_1);
	10365	+ cif_dev->err_state_work.lastline = lastline;
	10366	+ cif_dev->err_state_work.intstat = intstat;
	10367	+
	10368	+ /* clear all interrupts that has been triggered */
	10369	+ if (intstat) {
	10370	+ rkcif_write_register(cif_dev, CIF_REG_MIPI_LVDS_INTSTAT, intstat);
	10371	+ v4l2_dbg(2, rkcif_debug, &cif_dev->v4l2_dev,
	10372	+ "intstat 0x%x\n",
	10373	+ intstat);
	10374	+ } else {
	10375	+ return;
	10376	+ }
	10377	+
	10378	+ if (intstat & CSI_SIZE_ERR) {
	10379	+ cif_dev->irq_stats.csi_size_err_cnt++;
	10380	+ cif_dev->err_state \|= RKCIF_ERR_SIZE;
	10381	+ rkcif_write_register_or(cif_dev, CIF_REG_MIPI_LVDS_CTRL, 0x000A0000);
	10382	+ return;
	10383	+ }
	10384	+
	10385	+ if (intstat & CSI_FIFO_OVERFLOW_V1) {
	10386	+ cif_dev->irq_stats.csi_overflow_cnt++;
	10387	+ cif_dev->err_state \|= RKCIF_ERR_OVERFLOW;
	10388	+ return;
	10389	+ }
	10390	+
	10391	+ if (intstat & CSI_BANDWIDTH_LACK_V1) {
	10392	+ cif_dev->irq_stats.csi_bwidth_lack_cnt++;
	10393	+ cif_dev->err_state \|= RKCIF_ERR_BANDWIDTH_LACK;
	10394	+ }
	10395	+
	10396	+ if (intstat & CSI_ALL_ERROR_INTEN_V1) {
	10397	+ cif_dev->irq_stats.all_err_cnt++;
	10398	+ return;
	10399	+ }
	10400	+
	10401	+ for (i = 0; i < RKCIF_MAX_STREAM_MIPI; i++) {
	10402	+ mipi_id = rkcif_csi_g_mipi_id(&cif_dev->v4l2_dev,
	10403	+ intstat);
	10404	+ if (mipi_id < 0)
	10405	+ continue;
	10406	+
	10407	+ stream = &cif_dev->stream[mipi_id];
	10408	+ if (!cif_dev->sditf[0] \|\|
	10409	+ cif_dev->sditf[0]->mode.rdbk_mode)
	10410	+ stream->buf_wake_up_cnt++;
	10411	+
	10412	+ if (stream->stopping && (!stream->dma_en)) {
	10413	+ rkcif_stream_stop(stream);
	10414	+ stream->stopping = false;
	10415	+ wake_up(&stream->wq_stopped);
	10416	+ continue;
	10417	+ }
	10418	+
	10419	+ if (stream->state != RKCIF_STATE_STREAMING)
	10420	+ continue;
	10421	+ stream->is_in_vblank = true;
	10422	+ switch (mipi_id) {
	10423	+ case RKCIF_STREAM_MIPI_ID0:
	10424	+ stream->frame_phase = SW_FRM_END_ID0(intstat);
	10425	+ intstat &= ~CSI_FRAME_END_ID0;
	10426	+ break;
	10427	+ case RKCIF_STREAM_MIPI_ID1:
	10428	+ stream->frame_phase = SW_FRM_END_ID1(intstat);
	10429	+ intstat &= ~CSI_FRAME_END_ID1;
	10430	+ break;
	10431	+ case RKCIF_STREAM_MIPI_ID2:
	10432	+ stream->frame_phase = SW_FRM_END_ID2(intstat);
	10433	+ intstat &= ~CSI_FRAME_END_ID2;
	10434	+ break;
	10435	+ case RKCIF_STREAM_MIPI_ID3:
	10436	+ stream->frame_phase = SW_FRM_END_ID3(intstat);
	10437	+ intstat &= ~CSI_FRAME_END_ID3;
	10438	+ break;
	10439	+ }
	10440	+ if (stream->cifdev->rdbk_debug &&
	10441	+ stream->frame_idx < 15 &&
	10442	+ (!cif_dev->sditf[0] \|\| cif_dev->sditf[0]->mode.rdbk_mode))
	10443	+ v4l2_info(&cif_dev->v4l2_dev,
	10444	+ "stream[%d] fe %d, phase %d, %lld\n",
	10445	+ stream->id,
	10446	+ stream->frame_idx - 1,
	10447	+ stream->frame_phase,
	10448	+ ktime_get_ns());
	10449	+ if (stream->is_finish_stop_dma && stream->is_wait_dma_stop) {
	10450	+ stream->is_wait_dma_stop = false;
	10451	+ wake_up(&stream->wq_stopped);
	10452	+ stream->is_finish_stop_dma = false;
	10453	+ continue;
	10454	+ }
	10455	+ if (stream->crop_dyn_en)
	10456	+ rkcif_dynamic_crop(stream);
	10457	+
	10458	+ if (stream->dma_en & RKCIF_DMAEN_BY_VICAP) {
	10459	+ if (cif_dev->sync_cfg.type == RKCIF_NOSYNC_MODE)
	10460	+ is_update = true;
	10461	+ else
	10462	+ is_update = rkcif_check_buffer_prepare(stream);
	10463	+ v4l2_dbg(4, rkcif_debug, &cif_dev->v4l2_dev,
	10464	+ "dma capture by vicap, is_updata %d, group mode %d, dma_en %d\n",
	10465	+ is_update, cif_dev->sync_cfg.type, stream->dma_en);
	10466	+ if (is_update)
	10467	+ rkcif_update_stream(cif_dev, stream, mipi_id);
	10468	+ } else if (stream->dma_en & RKCIF_DMAEN_BY_ISP) {
	10469	+ v4l2_dbg(4, rkcif_debug, &cif_dev->v4l2_dev,
	10470	+ "dma capture by isp, dma_en 0x%x\n",
	10471	+ stream->dma_en);
	10472	+ rkcif_update_stream_toisp(cif_dev, stream, mipi_id);
	10473	+ } else if (stream->dma_en & RKCIF_DMAEN_BY_ROCKIT) {
	10474	+ v4l2_dbg(4, rkcif_debug, &cif_dev->v4l2_dev,
	10475	+ "dma capture by rockit, dma_en 0x%x\n",
	10476	+ stream->dma_en);
	10477	+ rkcif_update_stream_rockit(cif_dev, stream, mipi_id);
	10478	+ }
	10479	+
	10480	+ if (cif_dev->chip_id >= CHIP_RV1106_CIF)
	10481	+ rkcif_modify_frame_skip_config(stream);
	10482	+ if (stream->is_change_toisp) {
	10483	+ stream->is_change_toisp = false;
	10484	+ if ((cif_dev->hdr.hdr_mode == HDR_X2 && stream->id != 1) \|\|
	10485	+ (cif_dev->hdr.hdr_mode == HDR_X3 && stream->id != 2))
	10486	+ rkcif_release_unnecessary_buf_for_online(stream,
	10487	+ stream->curr_buf_toisp);
	10488	+ else
	10489	+ sditf_change_to_online(cif_dev->sditf[0]);
	10490	+ }
	10491	+
	10492	+ spin_lock_irqsave(&stream->vbq_lock, flags);
	10493	+ if (!(stream->dma_en & RKCIF_DMAEN_BY_ISP) && stream->lack_buf_cnt == 2) {
	10494	+ v4l2_dbg(4, rkcif_debug, &cif_dev->v4l2_dev,
	10495	+ "stream[%d] to stop dma, lack_buf_cnt %d\n",
	10496	+ stream->id, stream->lack_buf_cnt);
	10497	+ stream->to_stop_dma = RKCIF_DMAEN_BY_VICAP;
	10498	+ rkcif_stop_dma_capture(stream);
	10499	+ }
	10500	+ spin_unlock_irqrestore(&stream->vbq_lock, flags);
	10501	+ if (stream->to_en_scale) {
	10502	+ stream->to_en_scale = false;
	10503	+ rkcif_scale_start(stream->scale_vdev);
	10504	+ }
	10505	+ rkcif_detect_wake_up_mode_change(stream);
	10506	+ if (cif_dev->chip_id < CHIP_RK3588_CIF &&
	10507	+ mipi_id == RKCIF_STREAM_MIPI_ID0) {
	10508	+ if ((intstat & (CSI_FRAME1_START_ID0 \| CSI_FRAME0_START_ID0)) == 0 &&
	10509	+ detect_stream->fs_cnt_in_single_frame > 1) {
	10510	+ cif_dev->err_state \|= RKCIF_ERR_ID0_MULTI_FS;
	10511	+ detect_stream->is_fs_fe_not_paired = true;
	10512	+ detect_stream->fs_cnt_in_single_frame = 0;
	10513	+ } else {
	10514	+ detect_stream->fs_cnt_in_single_frame--;
	10515	+ }
	10516	+ }
	10517	+ rkcif_monitor_reset_event(cif_dev);
	10518	+ cif_dev->irq_stats.frm_end_cnt[stream->id]++;
	10519	+ }
	10520	+
	10521	+ for (i = 0; i < RKCIF_MAX_STREAM_MIPI; i++) {
	10522	+ if (intstat & CSI_START_INTSTAT(i)) {
	10523	+ stream = &cif_dev->stream[i];
	10524	+ if (i == 0) {
	10525	+ rkcif_deal_sof(cif_dev);
	10526	+ } else {
	10527	+ spin_lock_irqsave(&stream->fps_lock, flags);
	10528	+ stream->readout.fs_timestamp = ktime_get_ns();
	10529	+ stream->frame_idx++;
	10530	+ spin_unlock_irqrestore(&stream->fps_lock, flags);
	10531	+ }
	10532	+ stream->is_in_vblank = false;
	10533	+ spin_lock_irqsave(&stream->vbq_lock, flags);
	10534	+ if (stream->stopping && stream->dma_en) {
	10535	+ if (stream->dma_en & RKCIF_DMAEN_BY_VICAP)
	10536	+ stream->to_stop_dma = RKCIF_DMAEN_BY_VICAP;
	10537	+ else if (stream->dma_en & RKCIF_DMAEN_BY_ISP)
	10538	+ stream->to_stop_dma = RKCIF_DMAEN_BY_ISP;
	10539	+ stream->is_stop_capture = true;
	10540	+ }
	10541	+ if (stream->to_stop_dma) {
	10542	+ ret = rkcif_stop_dma_capture(stream);
	10543	+ if (!ret)
	10544	+ stream->is_finish_stop_dma = true;
	10545	+ }
	10546	+ if (stream->to_en_dma)
	10547	+ rkcif_enable_dma_capture(stream, false);
	10548	+ spin_unlock_irqrestore(&stream->vbq_lock, flags);
	10549	+ }
	10550	+ if (intstat & CSI_LINE_INTSTAT_V1(i)) {
	10551	+ stream = &cif_dev->stream[i];
	10552	+ if (stream->is_line_inten) {
	10553	+ stream->line_int_cnt++;
	10554	+ if (cif_dev->rdbk_debug > 1 &&
	10555	+ stream->frame_idx < 15)
	10556	+ v4l2_info(&cif_dev->v4l2_dev,
	10557	+ "line int %lld\n",
	10558	+ stream->line_int_cnt);
	10559	+ if (cif_dev->sditf[0] && cif_dev->sditf[0]->mode.rdbk_mode == RKISP_VICAP_RDBK_AUTO)
	10560	+ rkcif_line_wake_up_rdbk(stream, stream->id);
	10561	+ else
	10562	+ rkcif_line_wake_up(stream, stream->id);
	10563	+ rkcif_modify_line_int(stream, false);
	10564	+ stream->is_line_inten = false;
	10565	+ }
	10566	+ v4l2_dbg(3, rkcif_debug, &cif_dev->v4l2_dev,
	10567	+ "%s: id0 cur line:%d\n", __func__, lastline & 0x3fff);
	10568	+ }
	10569	+ }
	10570	+ } else {
	10571	+ struct rkcif_stream *stream;
	10572	+ int ch_id;
	10573	+ int lastline;
	10574	+
	10575	+ intstat = rkcif_read_register(cif_dev, CIF_REG_DVP_INTSTAT);
	10576	+ if (intstat)
	10577	+ rkcif_write_register(cif_dev, CIF_REG_DVP_INTSTAT, intstat);
	10578	+ else
	10579	+ return;
	10580	+ lastline = rkcif_read_register(cif_dev, CIF_REG_DVP_LINE_CNT);
	10581	+ cif_dev->err_state_work.lastline = lastline;
	10582	+ cif_dev->err_state_work.intstat = intstat;
	10583	+ stream = &cif_dev->stream[RKCIF_STREAM_CIF];
	10584	+
	10585	+ if (intstat & DVP_SIZE_ERR) {
	10586	+ cif_dev->irq_stats.dvp_size_err_cnt++;
	10587	+ rkcif_write_register_or(cif_dev, CIF_REG_DVP_CTRL, 0x000A0000);
	10588	+ cif_dev->err_state \|= RKCIF_ERR_SIZE;
	10589	+ }
	10590	+
	10591	+ if (intstat & DVP_FIFO_OVERFLOW) {
	10592	+ cif_dev->irq_stats.dvp_overflow_cnt++;
	10593	+ cif_dev->err_state \|= RKCIF_ERR_OVERFLOW;
	10594	+ }
	10595	+
	10596	+ if (intstat & DVP_BANDWIDTH_LACK) {
	10597	+ cif_dev->irq_stats.dvp_bwidth_lack_cnt++;
	10598	+ cif_dev->err_state \|= RKCIF_ERR_BANDWIDTH_LACK;
	10599	+ }
	10600	+
	10601	+ if (intstat & INTSTAT_ERR_RK3588) {
	10602	+ cif_dev->irq_stats.all_err_cnt++;
	10603	+ }
	10604	+
	10605	+ for (i = 0; i < RKCIF_MAX_STREAM_DVP; i++) {
	10606	+ ch_id = rkcif_dvp_g_ch_id_by_fe(&cif_dev->v4l2_dev, intstat);
	10607	+
	10608	+ if (ch_id < 0)
	10609	+ continue;
	10610	+
	10611	+ stream = &cif_dev->stream[ch_id];
	10612	+ if (!cif_dev->sditf[0] \|\|
	10613	+ cif_dev->sditf[0]->mode.rdbk_mode)
	10614	+ stream->buf_wake_up_cnt++;
	10615	+
	10616	+ if (stream->stopping) {
	10617	+ rkcif_stream_stop(stream);
	10618	+ stream->stopping = false;
	10619	+ wake_up(&stream->wq_stopped);
	10620	+ continue;
	10621	+ }
	10622	+
	10623	+ if (stream->state != RKCIF_STATE_STREAMING)
	10624	+ continue;
	10625	+ stream->is_in_vblank = true;
	10626	+ switch (ch_id) {
	10627	+ case RKCIF_STREAM_MIPI_ID0:
	10628	+ stream->frame_phase = SW_FRM_END_ID0(intstat);
	10629	+ intstat &= ~DVP_ALL_END_ID0;
	10630	+ break;
	10631	+ case RKCIF_STREAM_MIPI_ID1:
	10632	+ stream->frame_phase = SW_FRM_END_ID1(intstat);
	10633	+ intstat &= ~DVP_ALL_END_ID1;
	10634	+ break;
	10635	+ case RKCIF_STREAM_MIPI_ID2:
	10636	+ stream->frame_phase = SW_FRM_END_ID2(intstat);
	10637	+ intstat &= ~DVP_ALL_END_ID2;
	10638	+ break;
	10639	+ case RKCIF_STREAM_MIPI_ID3:
	10640	+ stream->frame_phase = SW_FRM_END_ID3(intstat);
	10641	+ intstat &= ~DVP_ALL_END_ID3;
	10642	+ break;
	10643	+ }
	10644	+ if (stream->dma_en & RKCIF_DMAEN_BY_VICAP) {
	10645	+ if (cif_dev->sync_cfg.type == RKCIF_NOSYNC_MODE)
	10646	+ is_update = true;
	10647	+ else
	10648	+ is_update = rkcif_check_buffer_prepare(stream);
	10649	+ if (is_update)
	10650	+ rkcif_update_stream(cif_dev, stream, ch_id);
	10651	+ } else if (stream->dma_en & RKCIF_DMAEN_BY_ISP) {
	10652	+ rkcif_update_stream_toisp(cif_dev, stream, ch_id);
	10653	+ } else if (stream->dma_en & RKCIF_DMAEN_BY_ROCKIT) {
	10654	+ rkcif_update_stream_rockit(cif_dev, stream, ch_id);
	10655	+ }
	10656	+
	10657	+ if (stream->to_en_dma)
	10658	+ rkcif_enable_dma_capture(stream, false);
	10659	+ if (stream->to_stop_dma) {
	10660	+ rkcif_stop_dma_capture(stream);
	10661	+ wake_up(&stream->wq_stopped);
	10662	+ }
	10663	+ cif_dev->irq_stats.frm_end_cnt[stream->id]++;
	10664	+ }
	10665	+
	10666	+ if (intstat & DVP_FRAME0_START_ID0 \|\| intstat & DVP_FRAME1_START_ID0) {
	10667	+ stream->is_in_vblank = false;
	10668	+ rkcif_deal_sof(cif_dev);
	10669	+ }
	10670	+
	10671	+ if (stream->crop_dyn_en)
	10672	+ rkcif_dynamic_crop(stream);
	10673	+ }
	10674	+}
	10675	+
6072	10676	void rkcif_irq_pingpong(struct rkcif_device *cif_dev)
6073	10677	{
6074	10678	struct rkcif_stream *stream;
6075	10679	struct rkcif_stream *detect_stream = &cif_dev->stream[0];
6076	10680	struct v4l2_mbus_config *mbus;
6077		- unsigned int intstat = 0x0, i = 0xff, bak_intstat = 0x0;
	10681	+ unsigned int intstat = 0x0, i = 0xff;
6078	10682	unsigned long flags;
6079	10683	int ret = 0;
6080	10684
..	..	@@ -6082,7 +10686,8 @@
6082	10686	return;
6083	10687
6084	10688	mbus = &cif_dev->active_sensor->mbus;
6085		- if ((mbus->type == V4L2_MBUS_CSI2 \|\|
	10689	+ if ((mbus->type == V4L2_MBUS_CSI2_DPHY \|\|
	10690	+ mbus->type == V4L2_MBUS_CSI2_CPHY \|\|
6086	10691	mbus->type == V4L2_MBUS_CCP2) &&
6087	10692	(cif_dev->chip_id == CHIP_RK1808_CIF \|\|
6088	10693	cif_dev->chip_id == CHIP_RV1126_CIF \|\|
..	..	@@ -6092,78 +10697,27 @@
6092	10697
6093	10698	intstat = rkcif_read_register(cif_dev, CIF_REG_MIPI_LVDS_INTSTAT);
6094	10699	lastline = rkcif_read_register(cif_dev, CIF_REG_MIPI_LVDS_LINE_LINE_CNT_ID0_1);
	10700	+ cif_dev->err_state_work.lastline = lastline;
	10701	+ cif_dev->err_state_work.intstat = intstat;
6095	10702
6096	10703	/* clear all interrupts that has been triggered */
6097	10704	rkcif_write_register(cif_dev, CIF_REG_MIPI_LVDS_INTSTAT, intstat);
6098	10705
6099	10706	if (intstat & CSI_FIFO_OVERFLOW) {
6100	10707	cif_dev->irq_stats.csi_overflow_cnt++;
6101		- v4l2_err(&cif_dev->v4l2_dev,
6102		- "ERROR: csi fifo overflow, intstat:0x%x, lastline:%d!!\n",
6103		- intstat, lastline);
6104		- return;
	10708	+ cif_dev->err_state \|= RKCIF_ERR_OVERFLOW;
6105	10709	}
6106	10710
6107	10711	if (intstat & CSI_BANDWIDTH_LACK) {
6108	10712	cif_dev->irq_stats.csi_bwidth_lack_cnt++;
6109		- v4l2_err(&cif_dev->v4l2_dev,
6110		- "ERROR: csi bandwidth lack, intstat:0x%x!!\n",
6111		- intstat);
	10713	+ cif_dev->err_state \|= RKCIF_ERR_BANDWIDTH_LACK;
6112	10714	return;
6113	10715	}
6114	10716
6115	10717	if (intstat & CSI_ALL_ERROR_INTEN) {
6116	10718	cif_dev->irq_stats.all_err_cnt++;
6117		- v4l2_err(&cif_dev->v4l2_dev,
6118		- "ERROR: CSI_ALL_ERROR_INTEN:0x%x!!\n", intstat);
6119	10719	return;
6120	10720	}
6121		-
6122		- if ((intstat & (CSI_FRAME0_START_ID0 \| CSI_FRAME1_START_ID0)) ==
6123		- (CSI_FRAME0_START_ID0 \| CSI_FRAME1_START_ID0)) {
6124		- v4l2_err(&cif_dev->v4l2_dev, "%s:ERR: double fs in one fs int\n",
6125		- __func__);
6126		- }
6127		-
6128		- if (intstat & CSI_FRAME0_START_ID0) {
6129		- if (mbus->type == V4L2_MBUS_CSI2)
6130		- rkcif_csi2_event_inc_sof();
6131		- else if (mbus->type == V4L2_MBUS_CCP2)
6132		- rkcif_lvds_event_inc_sof(cif_dev);
6133		- detect_stream->fs_cnt_in_single_frame++;
6134		- spin_lock_irqsave(&detect_stream->fps_lock, flags);
6135		- detect_stream->readout.fs_timestamp = ktime_get_ns();
6136		- spin_unlock_irqrestore(&detect_stream->fps_lock, flags);
6137		- }
6138		-
6139		- if (intstat & CSI_FRAME1_START_ID0) {
6140		- if (mbus->type == V4L2_MBUS_CSI2)
6141		- rkcif_csi2_event_inc_sof();
6142		- else if (mbus->type == V4L2_MBUS_CCP2)
6143		- rkcif_lvds_event_inc_sof(cif_dev);
6144		- detect_stream->fs_cnt_in_single_frame++;
6145		- spin_lock_irqsave(&detect_stream->fps_lock, flags);
6146		- detect_stream->readout.fs_timestamp = ktime_get_ns();
6147		- spin_unlock_irqrestore(&detect_stream->fps_lock, flags);
6148		- }
6149		- for (i = 0; i < RKCIF_MAX_STREAM_MIPI; i++) {
6150		- if (intstat & CSI_LINE_INTSTAT(i)) {
6151		- stream = &cif_dev->stream[i];
6152		- if (stream->is_line_inten) {
6153		- stream->line_int_cnt++;
6154		- rkcif_line_wake_up(stream, stream->id);
6155		- rkcif_modify_line_int(stream, false);
6156		- stream->is_line_inten = false;
6157		- }
6158		- v4l2_dbg(1, rkcif_debug, &cif_dev->v4l2_dev,
6159		- "%s: id0 cur line:%d\n", __func__, lastline & 0x3fff);
6160		- }
6161		- }
6162		-
6163		- /* if do not reach frame dma end, return irq */
6164		- mipi_id = rkcif_csi_g_mipi_id(&cif_dev->v4l2_dev, intstat);
6165		- if (mipi_id < 0)
6166		- return;
6167	10721
6168	10722	for (i = 0; i < RKCIF_MAX_STREAM_MIPI; i++) {
6169	10723	mipi_id = rkcif_csi_g_mipi_id(&cif_dev->v4l2_dev,
..	..	@@ -6206,22 +10760,44 @@
6206	10760
6207	10761	rkcif_update_stream(cif_dev, stream, mipi_id);
6208	10762	rkcif_detect_wake_up_mode_change(stream);
	10763	+ rkcif_monitor_reset_event(cif_dev);
6209	10764	if (mipi_id == RKCIF_STREAM_MIPI_ID0) {
6210	10765	if ((intstat & (CSI_FRAME1_START_ID0 \| CSI_FRAME0_START_ID0)) == 0 &&
6211	10766	detect_stream->fs_cnt_in_single_frame > 1) {
6212		- v4l2_dbg(2, rkcif_debug, &cif_dev->v4l2_dev,
6213		- "%s ERR: multi fs in oneframe, bak_int:0x%x, fs_num:%u\n",
6214		- __func__,
6215		- bak_intstat,
6216		- detect_stream->fs_cnt_in_single_frame);
	10767	+ cif_dev->err_state \|= RKCIF_ERR_ID0_MULTI_FS;
6217	10768	detect_stream->is_fs_fe_not_paired = true;
6218	10769	detect_stream->fs_cnt_in_single_frame = 0;
6219	10770	} else {
6220	10771	detect_stream->fs_cnt_in_single_frame--;
6221	10772	}
6222	10773	}
	10774	+ cif_dev->irq_stats.frm_end_cnt[stream->id]++;
6223	10775	}
6224		- cif_dev->irq_stats.all_frm_end_cnt++;
	10776	+ for (i = 0; i < RKCIF_MAX_STREAM_MIPI; i++) {
	10777	+ if (intstat & CSI_START_INTSTAT(i)) {
	10778	+ stream = &cif_dev->stream[i];
	10779	+ if (i == 0) {
	10780	+ rkcif_deal_sof(cif_dev);
	10781	+ } else {
	10782	+ spin_lock_irqsave(&stream->fps_lock, flags);
	10783	+ stream->readout.fs_timestamp = ktime_get_ns();
	10784	+ stream->frame_idx++;
	10785	+ spin_unlock_irqrestore(&stream->fps_lock, flags);
	10786	+ }
	10787	+ stream->is_in_vblank = false;
	10788	+ }
	10789	+ if (intstat & CSI_LINE_INTSTAT(i)) {
	10790	+ stream = &cif_dev->stream[i];
	10791	+ if (stream->is_line_inten) {
	10792	+ stream->line_int_cnt++;
	10793	+ rkcif_line_wake_up(stream, stream->id);
	10794	+ rkcif_modify_line_int(stream, false);
	10795	+ stream->is_line_inten = false;
	10796	+ }
	10797	+ v4l2_dbg(3, rkcif_debug, &cif_dev->v4l2_dev,
	10798	+ "%s: id0 cur line:%d\n", __func__, lastline & 0x3fff);
	10799	+ }
	10800	+ }
6225	10801	} else {
6226	10802	u32 lastline, lastpix, ctl;
6227	10803	u32 cif_frmst, frmid, int_en;
..	..	@@ -6235,49 +10811,36 @@
6235	10811	lastpix = rkcif_read_register(cif_dev, CIF_REG_DVP_LAST_PIX);
6236	10812	lastpix = CIF_FETCH_Y_LAST_LINE(lastpix);
6237	10813	ctl = rkcif_read_register(cif_dev, CIF_REG_DVP_CTRL);
	10814	+ cif_dev->err_state_work.lastline = lastline;
	10815	+ cif_dev->err_state_work.lastpixel = lastpix;
	10816	+ cif_dev->err_state_work.intstat = intstat;
6238	10817
6239	10818	rkcif_write_register(cif_dev, CIF_REG_DVP_INTSTAT, intstat);
6240	10819
6241	10820	stream = &cif_dev->stream[RKCIF_STREAM_CIF];
6242	10821
6243		- if ((intstat & LINE_INT_END) && !(intstat & FRAME_END) &&
6244		- (cif_dev->dvp_sof_in_oneframe == 0)) {
6245		- if ((intstat & (PRE_INF_FRAME_END \| PST_INF_FRAME_END)) == 0x0) {
6246		- if ((intstat & INTSTAT_ERR) == 0x0) {
6247		- rkcif_dvp_event_inc_sof(cif_dev);
6248		- int_en = rkcif_read_register(cif_dev, CIF_REG_DVP_INTEN);
6249		- int_en &= ~LINE_INT_EN;
6250		- rkcif_write_register(cif_dev, CIF_REG_DVP_INTEN, int_en);
6251		- cif_dev->dvp_sof_in_oneframe = 1;
6252		- }
6253		- }
6254		- }
6255		-
6256	10822	if (intstat & BUS_ERR) {
6257	10823	cif_dev->irq_stats.dvp_bus_err_cnt++;
6258		- v4l2_info(&cif_dev->v4l2_dev, "dvp bus err\n");
	10824	+ cif_dev->err_state \|= RKCIF_ERR_BUS;
6259	10825	}
6260	10826
6261	10827	if (intstat & DVP_ALL_OVERFLOW) {
6262	10828	cif_dev->irq_stats.dvp_overflow_cnt++;
6263		- v4l2_info(&cif_dev->v4l2_dev, "dvp overflow err\n");
	10829	+ cif_dev->err_state \|= RKCIF_ERR_OVERFLOW;
6264	10830	}
6265	10831
6266	10832	if (intstat & LINE_ERR) {
6267	10833	cif_dev->irq_stats.dvp_line_err_cnt++;
6268		- v4l2_info(&cif_dev->v4l2_dev, "dvp line err\n");
	10834	+ cif_dev->err_state \|= RKCIF_ERR_LINE;
6269	10835	}
6270	10836
6271	10837	if (intstat & PIX_ERR) {
6272	10838	cif_dev->irq_stats.dvp_pix_err_cnt++;
6273		- v4l2_info(&cif_dev->v4l2_dev, "dvp pix err\n");
	10839	+ cif_dev->err_state \|= RKCIF_ERR_PIXEL;
6274	10840	}
6275	10841
6276		- if (intstat & INTSTAT_ERR) {
	10842	+ if (intstat & INTSTAT_ERR)
6277	10843	cif_dev->irq_stats.all_err_cnt++;
6278		- v4l2_err(&cif_dev->v4l2_dev,
6279		- "ERROR: DVP_ALL_ERROR_INTEN:0x%x!!\n", intstat);
6280		- }
6281	10844
6282	10845	/* There are two irqs enabled:
6283	10846	* - PST_INF_FRAME_END: cif FIFO is ready,
..	..	@@ -6298,7 +10861,7 @@
6298	10861	stream = &cif_dev->stream[RKCIF_STREAM_CIF];
6299	10862
6300	10863	if ((intstat & FRAME_END)) {
6301		- struct vb2_v4l2_buffer *vb_done = NULL;
	10864	+ struct rkcif_buffer *active_buf = NULL;
6302	10865
6303	10866	int_en = rkcif_read_register(cif_dev, CIF_REG_DVP_INTEN);
6304	10867	int_en \|= LINE_INT_EN;
..	..	@@ -6318,7 +10881,7 @@
6318	10881	v4l2_info(&cif_dev->v4l2_dev, "frmid:%d, frmstat:0x%x\n",
6319	10882	frmid, cif_frmst);
6320	10883	rkcif_write_register(cif_dev, CIF_REG_DVP_FRAME_STATUS,
6321		- cif_frmst & 0x3);
	10884	+ FRAME_STAT_CLS);
6322	10885	}
6323	10886
6324	10887	if (lastline != stream->pixm.height \|\|
..	..	@@ -6334,11 +10897,11 @@
6334	10897
6335	10898	if (cif_frmst & CIF_F0_READY) {
6336	10899	if (stream->curr_buf)
6337		- vb_done = &stream->curr_buf->vb;
	10900	+ active_buf = stream->curr_buf;
6338	10901	stream->frame_phase = CIF_CSI_FRAME0_READY;
6339	10902	} else if (cif_frmst & CIF_F1_READY) {
6340	10903	if (stream->next_buf)
6341		- vb_done = &stream->next_buf->vb;
	10904	+ active_buf = stream->next_buf;
6342	10905	stream->frame_phase = CIF_CSI_FRAME1_READY;
6343	10906	}
6344	10907
..	..	@@ -6352,12 +10915,12 @@
6352	10915	ret = rkcif_assign_new_buffer_oneframe(stream,
6353	10916	RKCIF_YUV_ADDR_STATE_UPDATE);
6354	10917
6355		- if (vb_done && (!ret)) {
6356		- vb_done->sequence = stream->frame_idx;
6357		- rkcif_vb_done_oneframe(stream, vb_done);
	10918	+ if (active_buf && (!ret)) {
	10919	+ active_buf->vb.sequence = stream->frame_idx;
	10920	+ rkcif_vb_done_tasklet(stream, active_buf);
6358	10921	}
6359	10922	stream->frame_idx++;
6360		- cif_dev->irq_stats.all_frm_end_cnt++;
	10923	+ cif_dev->irq_stats.frm_end_cnt[stream->id]++;
6361	10924	}
6362	10925	} else {
6363	10926	for (i = 0; i < RKCIF_MAX_STREAM_DVP; i++) {
..	..	@@ -6406,10 +10969,23 @@
6406	10969	v4l2_info(&cif_dev->v4l2_dev, "frmid:%d, frmstat:0x%x\n",
6407	10970	frmid, cif_frmst);
6408	10971	rkcif_write_register(cif_dev, CIF_REG_DVP_FRAME_STATUS,
6409		- cif_frmst & 0xffff);
	10972	+ FRAME_STAT_CLS);
6410	10973	}
6411	10974	rkcif_update_stream(cif_dev, stream, ch_id);
6412		- cif_dev->irq_stats.all_frm_end_cnt++;
	10975	+ cif_dev->irq_stats.frm_end_cnt[stream->id]++;
	10976	+ }
	10977	+ }
	10978	+
	10979	+ if ((intstat & LINE_INT_END) && !(intstat & FRAME_END) &&
	10980	+ (cif_dev->dvp_sof_in_oneframe == 0)) {
	10981	+ if ((intstat & (PRE_INF_FRAME_END \| PST_INF_FRAME_END)) == 0x0) {
	10982	+ if ((intstat & INTSTAT_ERR) == 0x0) {
	10983	+ rkcif_deal_sof(cif_dev);
	10984	+ int_en = rkcif_read_register(cif_dev, CIF_REG_DVP_INTEN);
	10985	+ int_en &= ~LINE_INT_EN;
	10986	+ rkcif_write_register(cif_dev, CIF_REG_DVP_INTEN, int_en);
	10987	+ cif_dev->dvp_sof_in_oneframe = 1;
	10988	+ }
6413	10989	}
6414	10990	}
6415	10991
..	..	@@ -6431,6 +11007,8 @@
6431	11007
6432	11008	intstat = rkcif_read_register(cif_dev, CIF_REG_MIPI_LVDS_INTSTAT);
6433	11009	lastline = rkcif_read_register(cif_dev, CIF_REG_MIPI_LVDS_LINE_INT_NUM_ID0_1);
	11010	+ cif_dev->err_state_work.lastline = lastline;
	11011	+ cif_dev->err_state_work.intstat = intstat;
6434	11012
6435	11013	/* clear all interrupts that has been triggered */
6436	11014	rkcif_write_register(cif_dev, CIF_REG_MIPI_LVDS_INTSTAT, intstat);
..	..	@@ -6454,18 +11032,6 @@
6454	11032	"ERROR: cif lite lvds all err:0x%x!!\n", intstat);
6455	11033	return;
6456	11034	}
6457		-
6458		- if (intstat & CSI_FRAME0_START_ID0)
6459		- rkcif_lvds_event_inc_sof(cif_dev);
6460		-
6461		-
6462		- if (intstat & CSI_FRAME1_START_ID0)
6463		- rkcif_lvds_event_inc_sof(cif_dev);
6464		-
6465		- /* if do not reach frame dma end, return irq */
6466		- mipi_id = rkcif_csi_g_mipi_id(&cif_dev->v4l2_dev, intstat);
6467		- if (mipi_id < 0)
6468		- return;
6469	11035
6470	11036	for (i = 0; i < RKCIF_MAX_STREAM_MIPI; i++) {
6471	11037	mipi_id = rkcif_csi_g_mipi_id(&cif_dev->v4l2_dev,
..	..	@@ -6505,7 +11071,31 @@
6505	11071	}
6506	11072
6507	11073	rkcif_update_stream(cif_dev, stream, mipi_id);
	11074	+ rkcif_monitor_reset_event(cif_dev);
	11075	+ cif_dev->irq_stats.frm_end_cnt[stream->id]++;
6508	11076	}
6509		- cif_dev->irq_stats.all_frm_end_cnt++;
	11077	+
	11078	+ if (intstat & CSI_FRAME0_START_ID0)
	11079	+ rkcif_lvds_event_inc_sof(cif_dev);
	11080	+
	11081	+ if (intstat & CSI_FRAME1_START_ID0)
	11082	+ rkcif_lvds_event_inc_sof(cif_dev);
6510	11083	}
6511	11084	}
	11085	+
	11086	+int rkcif_sditf_disconnect(struct video_device *vdev)
	11087	+{
	11088	+ struct rkcif_vdev_node *vnode = vdev_to_node(vdev);
	11089	+ struct rkcif_stream *stream = to_rkcif_stream(vnode);
	11090	+ struct rkcif_device *cifdev = stream->cifdev;
	11091	+ struct media_link *link;
	11092	+ int ret;
	11093	+
	11094	+ link = list_first_entry(&cifdev->sditf[0]->sd.entity.links, struct media_link, list);
	11095	+ ret = media_entity_setup_link(link, 0);
	11096	+ if (ret)
	11097	+ dev_err(cifdev->dev, "failed to disable link of sditf with isp");
	11098	+
	11099	+ return ret;
	11100	+}
	11101	+EXPORT_SYMBOL(rkcif_sditf_disconnect);