kernel_5.10 no rt

hc

2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f

 kernel/arch/arm/mach-mmp/pm-mmp2.c
..
..
@@ -1,8 +1,6 @@
1
+// SPDX-License-Identifier: GPL-2.0-only
1
2
 /*
2
3
  * MMP2 Power Management Routines
3
- *
4
- * This software program is licensed subject to the GNU General Public License
5
- * (GPL).Version 2,June 1991, available at http://www.fsf.org/copyleft/gpl.html
6
4
  *
7
5
  * (C) Copyright 2012 Marvell International Ltd.
8
6
  * All Rights Reserved
..
..
@@ -19,7 +17,7 @@
19
17
 #include <linux/interrupt.h>
20
18
 #include <asm/mach-types.h>
21
19
 
22
-#include "cputype.h"
20
+#include <linux/soc/mmp/cputype.h>
23
21
 #include "addr-map.h"
24
22
 #include "pm-mmp2.h"
25
23
 #include "regs-icu.h"
..
..
@@ -125,19 +123,19 @@
125
123
 	case POWER_MODE_SYS_SLEEP:
126
124
 		apcr |= MPMU_PCR_PJ_SLPEN;		/* set the SLPEN bit */
127
125
 		apcr |= MPMU_PCR_PJ_VCTCXOSD;		/* set VCTCXOSD */
128
-		/* fall through */
126
+		fallthrough;
129
127
 	case POWER_MODE_CHIP_SLEEP:
130
128
 		apcr |= MPMU_PCR_PJ_SLPEN;
131
-		/* fall through */
129
+		fallthrough;
132
130
 	case POWER_MODE_APPS_SLEEP:
133
131
 		apcr |= MPMU_PCR_PJ_APBSD;		/* set APBSD */
134
-		/* fall through */
132
+		fallthrough;
135
133
 	case POWER_MODE_APPS_IDLE:
136
134
 		apcr |= MPMU_PCR_PJ_AXISD;		/* set AXISDD bit */
137
135
 		apcr |= MPMU_PCR_PJ_DDRCORSD;		/* set DDRCORSD bit */
138
136
 		idle_cfg |= APMU_PJ_IDLE_CFG_PJ_PWRDWN;	/* PJ power down */
139
137
 		apcr |= MPMU_PCR_PJ_SPSD;
140
-		/* fall through */
138
+		fallthrough;
141
139
 	case POWER_MODE_CORE_EXTIDLE:
142
140
 		idle_cfg |= APMU_PJ_IDLE_CFG_PJ_IDLE;	/* set the IDLE bit */
143
141
 		idle_cfg &= ~APMU_PJ_IDLE_CFG_ISO_MODE_CNTRL_MASK;