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2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f 
 kernel/arch/arm/kernel/entry-armv.S
....@@ -1,13 +1,10 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
12 /*
23  *  linux/arch/arm/kernel/entry-armv.S
34  *
45  *  Copyright (C) 1996,1997,1998 Russell King.
56  *  ARM700 fix by Matthew Godbolt (linux-user@willothewisp.demon.co.uk)
67  *  nommu support by Hyok S. Choi (hyok.choi@samsung.com)
7
- *
8
- * This program is free software; you can redistribute it and/or modify
9
- * it under the terms of the GNU General Public License version 2 as
10
- * published by the Free Software Foundation.
118  *
129  *  Low-level vector interface routines
1310  *
....@@ -207,20 +204,13 @@
207204 	svc_entry
208205 	irq_handler
209206 
210
-#ifdef CONFIG_PREEMPT
207
+#ifdef CONFIG_PREEMPTION
211208 	ldr	r8, [tsk, #TI_PREEMPT]		@ get preempt count
212
-	teq	r8, #0				@ if preempt count != 0
213
-	bne	1f				@ return from exeption
214209 	ldr	r0, [tsk, #TI_FLAGS]		@ get flags
215
-	tst	r0, #_TIF_NEED_RESCHED		@ if NEED_RESCHED is set
216
-	blne	svc_preempt			@ preempt!
217
-
218
-	ldr	r8, [tsk, #TI_PREEMPT_LAZY]	@ get preempt lazy count
219
-	teq	r8, #0				@ if preempt lazy count != 0
210
+	teq	r8, #0				@ if preempt count != 0
220211 	movne	r0, #0				@ force flags to 0
221
-	tst	r0, #_TIF_NEED_RESCHED_LAZY
212
+	tst	r0, #_TIF_NEED_RESCHED
222213 	blne	svc_preempt
223
-1:
224214 #endif
225215 
226216 	svc_exit r5, irq = 1			@ return from exception
....@@ -229,20 +219,14 @@
229219 
230220 	.ltorg
231221 
232
-#ifdef CONFIG_PREEMPT
222
+#ifdef CONFIG_PREEMPTION
233223 svc_preempt:
234224 	mov	r8, lr
235225 1:	bl	preempt_schedule_irq		@ irq en/disable is done inside
236226 	ldr	r0, [tsk, #TI_FLAGS]		@ get new tasks TI_FLAGS
237227 	tst	r0, #_TIF_NEED_RESCHED
238
-	bne	1b
239
-	tst	r0, #_TIF_NEED_RESCHED_LAZY
240228 	reteq	r8				@ go again
241
-	ldr	r0, [tsk, #TI_PREEMPT_LAZY]	@ get preempt lazy count
242
-	teq	r0, #0				@ if preempt lazy count != 0
243
-	beq	1b
244
-	ret	r8				@ go again
245
-
229
+	b	1b
246230 #endif
247231 
248232 __und_fault:
....@@ -268,31 +252,10 @@
268252 #else
269253 	svc_entry
270254 #endif
271
-	@
272
-	@ call emulation code, which returns using r9 if it has emulated
273
-	@ the instruction, or the more conventional lr if we are to treat
274
-	@ this as a real undefined instruction
275
-	@
276
-	@  r0 - instruction
277
-	@
278
-#ifndef CONFIG_THUMB2_KERNEL
279
-	ldr	r0, [r4, #-4]
280
-#else
281
-	mov	r1, #2
282
-	ldrh	r0, [r4, #-2]			@ Thumb instruction at LR - 2
283
-	cmp	r0, #0xe800			@ 32-bit instruction if xx >= 0
284
-	blo	__und_svc_fault
285
-	ldrh	r9, [r4]			@ bottom 16 bits
286
-	add	r4, r4, #2
287
-	str	r4, [sp, #S_PC]
288
-	orr	r0, r9, r0, lsl #16
289
-#endif
290
-	badr	r9, __und_svc_finish
291
-	mov	r2, r4
292
-	bl	call_fpe
293255 
294256 	mov	r1, #4				@ PC correction to apply
295
-__und_svc_fault:
257
+ THUMB(	tst	r5, #PSR_T_BIT		)	@ exception taken in Thumb mode?
258
+ THUMB(	movne	r1, #2			)	@ if so, fix up PC correction
296259 	mov	r0, sp				@ struct pt_regs *regs
297260 	bl	__und_fault
298261 
....@@ -640,7 +603,7 @@
640603 	@ Test if we need to give access to iWMMXt coprocessors
641604 	ldr	r5, [r10, #TI_FLAGS]
642605 	rsbs	r7, r8, #(1 << 8)		@ CP 0 or 1 only
643
-	movcss	r7, r5, lsr #(TIF_USING_IWMMXT + 1)
606
+	movscs	r7, r5, lsr #(TIF_USING_IWMMXT + 1)
644607 	bcs	iwmmxt_task_enable
645608 #endif
646609  ARM(	add	pc, pc, r8, lsr #6	)
....@@ -833,7 +796,7 @@
833796  * existing ones.  This mechanism should be used only for things that are
834797  * really small and justified, and not be abused freely.
835798  *
836
- * See Documentation/arm/kernel_user_helpers.txt for formal definitions.
799
+ * See Documentation/arm/kernel_user_helpers.rst for formal definitions.
837800  */
838801  THUMB(	.arm	)
839802 
....@@ -876,7 +839,7 @@
876839 	smp_dmb	arm
877840 1:	ldrexd	r0, r1, [r2]			@ load current val
878841 	eors	r3, r0, r4			@ compare with oldval (1)
879
-	eoreqs	r3, r1, r5			@ compare with oldval (2)
842
+	eorseq	r3, r1, r5			@ compare with oldval (2)
880843 	strexdeq r3, r6, r7, [r2]		@ store newval if eq
881844 	teqeq	r3, #1				@ success?
882845 	beq	1b				@ if no then retry
....@@ -900,8 +863,8 @@
900863 	ldmia	r1, {r6, lr}			@ load new val
901864 1:	ldmia	r2, {r0, r1}			@ load current val
902865 	eors	r3, r0, r4			@ compare with oldval (1)
903
-	eoreqs	r3, r1, r5			@ compare with oldval (2)
904
-2:	stmeqia	r2, {r6, lr}			@ store newval if eq
866
+	eorseq	r3, r1, r5			@ compare with oldval (2)
867
+2:	stmiaeq	r2, {r6, lr}			@ store newval if eq
905868 	rsbs	r0, r3, #0			@ set return val and C flag
906869 	ldmfd	sp!, {r4, r5, r6, pc}
907870 
....@@ -915,7 +878,7 @@
915878 	mov	r7, #0xffff0fff
916879 	sub	r7, r7, #(0xffff0fff - (0xffff0f60 + (1b - __kuser_cmpxchg64)))
917880 	subs	r8, r4, r7
918
-	rsbcss	r8, r8, #(2b - 1b)
881
+	rsbscs	r8, r8, #(2b - 1b)
919882 	strcs	r7, [sp, #S_PC]
920883 #if __LINUX_ARM_ARCH__ < 6
921884 	bcc	kuser_cmpxchg32_fixup
....@@ -973,7 +936,7 @@
973936 	mov	r7, #0xffff0fff
974937 	sub	r7, r7, #(0xffff0fff - (0xffff0fc0 + (1b - __kuser_cmpxchg)))
975938 	subs	r8, r4, r7
976
-	rsbcss	r8, r8, #(2b - 1b)
939
+	rsbscs	r8, r8, #(2b - 1b)
977940 	strcs	r7, [sp, #S_PC]
978941 	ret	lr
979942 	.previous
....@@ -1042,12 +1005,11 @@
10421005 	sub	lr, lr, #\correction
10431006 	.endif
10441007 
1045
-	@
1046
-	@ Save r0, lr_<exception> (parent PC) and spsr_<exception>
1047
-	@ (parent CPSR)
1048
-	@
1008
+	@ Save r0, lr_<exception> (parent PC)
10491009 	stmia	sp, {r0, lr}		@ save r0, lr
1050
-	mrs	lr, spsr
1010
+
1011
+	@ Save spsr_<exception> (parent CPSR)
1012
+2:	mrs	lr, spsr
10511013 	str	lr, [sp, #8]		@ save spsr
10521014 
10531015 	@
....@@ -1068,6 +1030,44 @@
10681030 	movs	pc, lr			@ branch to handler in SVC mode
10691031 ENDPROC(vector_\name)
10701032 
1033
+#ifdef CONFIG_HARDEN_BRANCH_HISTORY
1034
+	.subsection 1
1035
+	.align 5
1036
+vector_bhb_loop8_\name:
1037
+	.if \correction
1038
+	sub	lr, lr, #\correction
1039
+	.endif
1040
+
1041
+	@ Save r0, lr_<exception> (parent PC)
1042
+	stmia	sp, {r0, lr}
1043
+
1044
+	@ bhb workaround
1045
+	mov	r0, #8
1046
+3:	W(b)	. + 4
1047
+	subs	r0, r0, #1
1048
+	bne	3b
1049
+	dsb
1050
+	isb
1051
+	b	2b
1052
+ENDPROC(vector_bhb_loop8_\name)
1053
+
1054
+vector_bhb_bpiall_\name:
1055
+	.if \correction
1056
+	sub	lr, lr, #\correction
1057
+	.endif
1058
+
1059
+	@ Save r0, lr_<exception> (parent PC)
1060
+	stmia	sp, {r0, lr}
1061
+
1062
+	@ bhb workaround
1063
+	mcr	p15, 0, r0, c7, c5, 6	@ BPIALL
1064
+	@ isb not needed due to "movs pc, lr" in the vector stub
1065
+	@ which gives a "context synchronisation".
1066
+	b	2b
1067
+ENDPROC(vector_bhb_bpiall_\name)
1068
+	.previous
1069
+#endif
1070
+
10711071 	.align	2
10721072 	@ handler addresses follow this label
10731073 1:
....@@ -1076,6 +1076,10 @@
10761076 	.section .stubs, "ax", %progbits
10771077 	@ This must be the first word
10781078 	.word	vector_swi
1079
+#ifdef CONFIG_HARDEN_BRANCH_HISTORY
1080
+	.word	vector_bhb_loop8_swi
1081
+	.word	vector_bhb_bpiall_swi
1082
+#endif
10791083 
10801084 vector_rst:
10811085  ARM(	swi	SYS_ERROR0	)
....@@ -1190,8 +1194,10 @@
11901194  * FIQ "NMI" handler
11911195  *-----------------------------------------------------------------------------
11921196  * Handle a FIQ using the SVC stack allowing FIQ act like NMI on x86
1193
- * systems.
1197
+ * systems. This must be the last vector stub, so lets place it in its own
1198
+ * subsection.
11941199  */
1200
+	.subsection 2
11951201 	vector_stub	fiq, FIQ_MODE, 4
11961202 
11971203 	.long	__fiq_usr			@  0  (USR_26 / USR_32)
....@@ -1224,6 +1230,30 @@
12241230 	W(b)	vector_irq
12251231 	W(b)	vector_fiq
12261232 
1233
+#ifdef CONFIG_HARDEN_BRANCH_HISTORY
1234
+	.section .vectors.bhb.loop8, "ax", %progbits
1235
+.L__vectors_bhb_loop8_start:
1236
+	W(b)	vector_rst
1237
+	W(b)	vector_bhb_loop8_und
1238
+	W(ldr)	pc, .L__vectors_bhb_loop8_start + 0x1004
1239
+	W(b)	vector_bhb_loop8_pabt
1240
+	W(b)	vector_bhb_loop8_dabt
1241
+	W(b)	vector_addrexcptn
1242
+	W(b)	vector_bhb_loop8_irq
1243
+	W(b)	vector_bhb_loop8_fiq
1244
+
1245
+	.section .vectors.bhb.bpiall, "ax", %progbits
1246
+.L__vectors_bhb_bpiall_start:
1247
+	W(b)	vector_rst
1248
+	W(b)	vector_bhb_bpiall_und
1249
+	W(ldr)	pc, .L__vectors_bhb_bpiall_start + 0x1008
1250
+	W(b)	vector_bhb_bpiall_pabt
1251
+	W(b)	vector_bhb_bpiall_dabt
1252
+	W(b)	vector_addrexcptn
1253
+	W(b)	vector_bhb_bpiall_irq
1254
+	W(b)	vector_bhb_bpiall_fiq
1255
+#endif
1256
+
12271257 	.data
12281258 	.align	2
12291259