kernel_5.10 no rt

hc

2023-12-11 6778948f9de86c3cfaf36725a7c87dcff9ba247f

 kernel/arch/arm/boot/dts/tegra20.dtsi
..
..
@@ -4,6 +4,7 @@
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 #include <dt-bindings/memory/tegra20-mc.h>
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 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
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 #include <dt-bindings/interrupt-controller/arm-gic.h>
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+#include <dt-bindings/soc/tegra-pmc.h>
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 / {
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 	compatible = "nvidia,tegra20";
..
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@@ -16,25 +17,27 @@
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 		reg = <0 0>;
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 	};
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19
 
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-	iram@40000000 {
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+	sram@40000000 {
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 		compatible = "mmio-sram";
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 		reg = <0x40000000 0x40000>;
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 		#address-cells = <1>;
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 		#size-cells = <1>;
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 		ranges = <0 0x40000000 0x40000>;
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-		vde_pool: vde@400 {
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+		vde_pool: sram@400 {
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 			reg = <0x400 0x3fc00>;
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 			pool;
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 		};
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 	};
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 	host1x@50000000 {
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-		compatible = "nvidia,tegra20-host1x", "simple-bus";
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+		compatible = "nvidia,tegra20-host1x";
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 		reg = <0x50000000 0x00024000>;
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 		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
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 			     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
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+		interrupt-names = "syncpt", "host1x";
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 		clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
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+		clock-names = "host1x";
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 		resets = <&tegra_car 28>;
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 		reset-names = "host1x";
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..
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@@ -153,7 +156,9 @@
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 		dsi@54300000 {
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 			compatible = "nvidia,tegra20-dsi";
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 			reg = <0x54300000 0x00040000>;
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-			clocks = <&tegra_car TEGRA20_CLK_DSI>;
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+			clocks = <&tegra_car TEGRA20_CLK_DSI>,
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+				 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
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+			clock-names = "dsi", "parent";
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 			resets = <&tegra_car 48>;
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 			reset-names = "dsi";
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 			status = "disabled";
..
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@@ -171,8 +176,8 @@
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 	intc: interrupt-controller@50041000 {
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 		compatible = "arm,cortex-a9-gic";
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-		reg = <0x50041000 0x1000
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-		       0x50040100 0x0100>;
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+		reg = <0x50041000 0x1000>,
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+		      <0x50040100 0x0100>;
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 		interrupt-controller;
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 		#interrupt-cells = <3>;
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 		interrupt-parent = <&intc>;
..
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@@ -271,15 +276,15 @@
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276
 
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 	vde@6001a000 {
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 		compatible = "nvidia,tegra20-vde";
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-		reg = <0x6001a000 0x1000   /* Syntax Engine */
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-		       0x6001b000 0x1000   /* Video Bitstream Engine */
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-		       0x6001c000  0x100   /* Macroblock Engine */
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-		       0x6001c200  0x100   /* Post-processing Engine */
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-		       0x6001c400  0x100   /* Motion Compensation Engine */
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-		       0x6001c600  0x100   /* Transform Engine */
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-		       0x6001c800  0x100   /* Pixel prediction block */
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-		       0x6001ca00  0x100   /* Video DMA */
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-		       0x6001d800  0x300>; /* Video frame controls */
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+		reg = <0x6001a000 0x1000>, /* Syntax Engine */
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+		      <0x6001b000 0x1000>, /* Video Bitstream Engine */
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+		      <0x6001c000  0x100>, /* Macroblock Engine */
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+		      <0x6001c200  0x100>, /* Post-processing Engine */
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+		      <0x6001c400  0x100>, /* Motion Compensation Engine */
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+		      <0x6001c600  0x100>, /* Transform Engine */
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+		      <0x6001c800  0x100>, /* Pixel prediction block */
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+		      <0x6001ca00  0x100>, /* Video DMA */
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+		      <0x6001d800  0x300>; /* Video frame controls */
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 		reg-names = "sxe", "bsev", "mbe", "ppe", "mce",
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 			    "tfe", "ppb", "vdma", "frameid";
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 		iram = <&vde_pool>; /* IRAM region */
..
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@@ -294,16 +299,16 @@
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 	apbmisc@70000800 {
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 		compatible = "nvidia,tegra20-apbmisc";
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-		reg = <0x70000800 0x64   /* Chip revision */
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-		       0x70000008 0x04>; /* Strapping options */
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+		reg = <0x70000800 0x64>, /* Chip revision */
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+		      <0x70000008 0x04>; /* Strapping options */
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 	};
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 	pinmux: pinmux@70000014 {
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 		compatible = "nvidia,tegra20-pinmux";
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-		reg = <0x70000014 0x10   /* Tri-state registers */
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-		       0x70000080 0x20   /* Mux registers */
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-		       0x700000a0 0x14   /* Pull-up/down registers */
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-		       0x70000868 0xa8>; /* Pad control registers */
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+		reg = <0x70000014 0x10>, /* Tri-state registers */
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+		      <0x70000080 0x20>, /* Mux registers */
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+		      <0x700000a0 0x14>, /* Pull-up/down registers */
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+		      <0x70000868 0xa8>; /* Pad control registers */
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 	};
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 	das@70000c00 {
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@@ -608,30 +613,30 @@
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 		status = "disabled";
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 	};
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615
 
611
-	pmc@7000e400 {
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+	tegra_pmc: pmc@7000e400 {
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 		compatible = "nvidia,tegra20-pmc";
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 		reg = <0x7000e400 0x400>;
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 		clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>;
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 		clock-names = "pclk", "clk32k_in";
621
+		#clock-cells = <1>;
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 	};
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623
 
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 	mc: memory-controller@7000f000 {
619
-		compatible = "nvidia,tegra20-mc";
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-		reg = <0x7000f000 0x024
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-		       0x7000f03c 0x3c4>;
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+		compatible = "nvidia,tegra20-mc-gart";
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+		reg = <0x7000f000 0x00000400>, /* controller registers */
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+		      <0x58000000 0x02000000>; /* GART aperture */
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+		clocks = <&tegra_car TEGRA20_CLK_MC>;
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+		clock-names = "mc";
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 		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
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 		#reset-cells = <1>;
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-	};
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-
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-	iommu@7000f024 {
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-		compatible = "nvidia,tegra20-gart";
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-		reg = <0x7000f024 0x00000018	/* controller registers */
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-		       0x58000000 0x02000000>;	/* GART aperture */
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+		#iommu-cells = <0>;
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 	};
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 	memory-controller@7000f400 {
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 		compatible = "nvidia,tegra20-emc";
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 		reg = <0x7000f400 0x200>;
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+		interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
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+		clocks = <&tegra_car TEGRA20_CLK_EMC>;
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 		#address-cells = <1>;
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 		#size-cells = <0>;
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 	};
..
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@@ -648,12 +653,12 @@
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 	pcie@80003000 {
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 		compatible = "nvidia,tegra20-pcie";
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 		device_type = "pci";
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-		reg = <0x80003000 0x00000800   /* PADS registers */
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-		       0x80003800 0x00000200   /* AFI registers */
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-		       0x90000000 0x10000000>; /* configuration space */
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+		reg = <0x80003000 0x00000800>, /* PADS registers */
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+		      <0x80003800 0x00000200>, /* AFI registers */
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+		      <0x90000000 0x10000000>; /* configuration space */
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 		reg-names = "pads", "afi", "cs";
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-		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH   /* controller interrupt */
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-			      GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
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+		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */
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+			     <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
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 		interrupt-names = "intr", "msi";
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 		#interrupt-cells = <1>;
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@@ -664,11 +669,11 @@
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 		#address-cells = <3>;
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 		#size-cells = <2>;
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-		ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000   /* port 0 registers */
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-			  0x82000000 0 0x80001000 0x80001000 0 0x00001000   /* port 1 registers */
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-			  0x81000000 0 0          0x82000000 0 0x00010000   /* downstream I/O */
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-			  0x82000000 0 0xa0000000 0xa0000000 0 0x08000000   /* non-prefetchable memory */
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-			  0xc2000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */
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+		ranges = <0x02000000 0 0x80000000 0x80000000 0 0x00001000>, /* port 0 registers */
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+			 <0x02000000 0 0x80001000 0x80001000 0 0x00001000>, /* port 1 registers */
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+			 <0x01000000 0 0          0x82000000 0 0x00010000>, /* downstream I/O */
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+			 <0x02000000 0 0xa0000000 0xa0000000 0 0x08000000>, /* non-prefetchable memory */
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+			 <0x42000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */
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 		clocks = <&tegra_car TEGRA20_CLK_PEX>,
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 			 <&tegra_car TEGRA20_CLK_AFI>,
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@@ -725,7 +730,8 @@
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 	phy1: usb-phy@c5000000 {
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 		compatible = "nvidia,tegra20-usb-phy";
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-		reg = <0xc5000000 0x4000 0xc5000000 0x4000>;
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+		reg = <0xc5000000 0x4000>,
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+		      <0xc5000000 0x4000>;
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 		phy_type = "utmi";
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 		clocks = <&tegra_car TEGRA20_CLK_USBD>,
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 			 <&tegra_car TEGRA20_CLK_PLL_U>,
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@@ -734,6 +740,7 @@
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 		clock-names = "reg", "pll_u", "timer", "utmi-pads";
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 		resets = <&tegra_car 22>, <&tegra_car 22>;
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 		reset-names = "usb", "utmi-pads";
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+		#phy-cells = <0>;
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 		nvidia,has-legacy-mode;
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 		nvidia,hssync-start-delay = <9>;
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 		nvidia,idle-wait-delay = <17>;
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@@ -768,6 +775,7 @@
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 		clock-names = "reg", "pll_u", "ulpi-link";
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 		resets = <&tegra_car 58>, <&tegra_car 22>;
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 		reset-names = "usb", "utmi-pads";
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+		#phy-cells = <0>;
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 		status = "disabled";
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 	};
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..
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@@ -785,7 +793,8 @@
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 	phy3: usb-phy@c5008000 {
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 		compatible = "nvidia,tegra20-usb-phy";
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-		reg = <0xc5008000 0x4000 0xc5000000 0x4000>;
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+		reg = <0xc5008000 0x4000>,
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+		      <0xc5000000 0x4000>;
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 		phy_type = "utmi";
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 		clocks = <&tegra_car TEGRA20_CLK_USB3>,
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 			 <&tegra_car TEGRA20_CLK_PLL_U>,
..
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@@ -794,6 +803,7 @@
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 		clock-names = "reg", "pll_u", "timer", "utmi-pads";
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 		resets = <&tegra_car 59>, <&tegra_car 22>;
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 		reset-names = "usb", "utmi-pads";
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+		#phy-cells = <0>;
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 		nvidia,hssync-start-delay = <9>;
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 		nvidia,idle-wait-delay = <17>;
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 		nvidia,elastic-limit = <16>;
..
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@@ -804,41 +814,45 @@
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 		status = "disabled";
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 	};
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-	sdhci@c8000000 {
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+	mmc@c8000000 {
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 		compatible = "nvidia,tegra20-sdhci";
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 		reg = <0xc8000000 0x200>;
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 		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
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 		clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
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+		clock-names = "sdhci";
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 		resets = <&tegra_car 14>;
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 		reset-names = "sdhci";
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 		status = "disabled";
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 	};
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827
 
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-	sdhci@c8000200 {
828
+	mmc@c8000200 {
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 		compatible = "nvidia,tegra20-sdhci";
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 		reg = <0xc8000200 0x200>;
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 		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
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 		clocks = <&tegra_car TEGRA20_CLK_SDMMC2>;
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+		clock-names = "sdhci";
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 		resets = <&tegra_car 9>;
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 		reset-names = "sdhci";
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 		status = "disabled";
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 	};
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838
 
827
-	sdhci@c8000400 {
839
+	mmc@c8000400 {
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 		compatible = "nvidia,tegra20-sdhci";
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 		reg = <0xc8000400 0x200>;
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 		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
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 		clocks = <&tegra_car TEGRA20_CLK_SDMMC3>;
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+		clock-names = "sdhci";
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 		resets = <&tegra_car 69>;
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 		reset-names = "sdhci";
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 		status = "disabled";
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 	};
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849
 
837
-	sdhci@c8000600 {
850
+	mmc@c8000600 {
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 		compatible = "nvidia,tegra20-sdhci";
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 		reg = <0xc8000600 0x200>;
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 		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
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 		clocks = <&tegra_car TEGRA20_CLK_SDMMC4>;
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+		clock-names = "sdhci";
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 		resets = <&tegra_car 15>;
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 		reset-names = "sdhci";
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 		status = "disabled";
..
..
@@ -852,12 +866,14 @@
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 			device_type = "cpu";
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867
 			compatible = "arm,cortex-a9";
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 			reg = <0>;
869
+			clocks = <&tegra_car TEGRA20_CLK_CCLK>;
855
870
 		};
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871
 
857
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 		cpu@1 {
858
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 			device_type = "cpu";
859
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 			compatible = "arm,cortex-a9";
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 			reg = <1>;
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+			clocks = <&tegra_car TEGRA20_CLK_CCLK>;
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 		};
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 	};
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..
..
@@ -865,5 +881,7 @@
865
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 		compatible = "arm,cortex-a9-pmu";
866
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 		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
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 			     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
884
+		interrupt-affinity = <&{/cpus/cpu@0}>,
885
+				     <&{/cpus/cpu@1}>;
868
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 	};
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 };