.. | .. |
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1 | | -/* |
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2 | | - * Copyright 2011 Freescale Semiconductor, Inc. |
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3 | | - * Copyright 2011 Linaro Ltd. |
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4 | | - * |
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5 | | - * The code contained herein is licensed under the GNU General Public |
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6 | | - * License. You may obtain a copy of the GNU General Public License |
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7 | | - * Version 2 or later at the following locations: |
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8 | | - * |
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9 | | - * http://www.opensource.org/licenses/gpl-license.html |
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10 | | - * http://www.gnu.org/copyleft/gpl.html |
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11 | | - */ |
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| 1 | +// SPDX-License-Identifier: GPL-2.0+ |
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| 2 | +// |
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| 3 | +// Copyright 2011 Freescale Semiconductor, Inc. |
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| 4 | +// Copyright 2011 Linaro Ltd. |
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12 | 5 | |
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13 | 6 | #include "imx53-pinfunc.h" |
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14 | 7 | #include <dt-bindings/clock/imx5-clock.h> |
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.. | .. |
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38 | 31 | i2c0 = &i2c1; |
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39 | 32 | i2c1 = &i2c2; |
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40 | 33 | i2c2 = &i2c3; |
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| 34 | + ipu0 = &ipu; |
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41 | 35 | mmc0 = &esdhc1; |
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42 | 36 | mmc1 = &esdhc2; |
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43 | 37 | mmc2 = &esdhc3; |
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.. | .. |
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76 | 70 | display-subsystem { |
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77 | 71 | compatible = "fsl,imx-display-subsystem"; |
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78 | 72 | ports = <&ipu_di0>, <&ipu_di1>; |
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| 73 | + }; |
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| 74 | + |
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| 75 | + capture_subsystem { |
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| 76 | + compatible = "fsl,imx-capture-subsystem"; |
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| 77 | + ports = <&ipu_csi0>, <&ipu_csi1>; |
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79 | 78 | }; |
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80 | 79 | |
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81 | 80 | tzic: tz-interrupt-controller@fffc000 { |
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.. | .. |
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165 | 164 | |
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166 | 165 | ipu_csi0: port@0 { |
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167 | 166 | reg = <0>; |
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| 167 | + |
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| 168 | + ipu_csi0_from_parallel_sensor: endpoint { |
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| 169 | + }; |
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168 | 170 | }; |
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169 | 171 | |
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170 | 172 | ipu_csi1: port@1 { |
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171 | 173 | reg = <1>; |
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| 174 | + |
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| 175 | + ipu_csi1_from_parallel_sensor: endpoint { |
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| 176 | + }; |
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172 | 177 | }; |
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173 | 178 | |
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174 | 179 | ipu_di0: port@2 { |
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.. | .. |
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207 | 212 | }; |
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208 | 213 | }; |
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209 | 214 | |
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210 | | - aips@50000000 { /* AIPS1 */ |
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| 215 | + gpu: gpu@30000000 { |
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| 216 | + compatible = "amd,imageon-200.0", "amd,imageon"; |
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| 217 | + reg = <0x30000000 0x20000>; |
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| 218 | + reg-names = "kgsl_3d0_reg_memory"; |
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| 219 | + interrupts = <12>; |
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| 220 | + interrupt-names = "kgsl_3d0_irq"; |
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| 221 | + clocks = <&clks IMX5_CLK_GPU3D_GATE>, <&clks IMX5_CLK_GARB_GATE>; |
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| 222 | + clock-names = "core_clk", "mem_iface_clk"; |
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| 223 | + }; |
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| 224 | + |
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| 225 | + bus@50000000 { /* AIPS1 */ |
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211 | 226 | compatible = "fsl,aips-bus", "simple-bus"; |
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212 | 227 | #address-cells = <1>; |
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213 | 228 | #size-cells = <1>; |
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.. | .. |
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221 | 236 | reg = <0x50000000 0x40000>; |
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222 | 237 | ranges; |
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223 | 238 | |
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224 | | - esdhc1: esdhc@50004000 { |
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| 239 | + esdhc1: mmc@50004000 { |
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225 | 240 | compatible = "fsl,imx53-esdhc"; |
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226 | 241 | reg = <0x50004000 0x4000>; |
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227 | 242 | interrupts = <1>; |
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.. | .. |
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233 | 248 | status = "disabled"; |
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234 | 249 | }; |
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235 | 250 | |
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236 | | - esdhc2: esdhc@50008000 { |
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| 251 | + esdhc2: mmc@50008000 { |
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237 | 252 | compatible = "fsl,imx53-esdhc"; |
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238 | 253 | reg = <0x50008000 0x4000>; |
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239 | 254 | interrupts = <2>; |
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.. | .. |
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257 | 272 | status = "disabled"; |
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258 | 273 | }; |
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259 | 274 | |
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260 | | - ecspi1: ecspi@50010000 { |
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| 275 | + ecspi1: spi@50010000 { |
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261 | 276 | #address-cells = <1>; |
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262 | 277 | #size-cells = <0>; |
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263 | 278 | compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; |
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.. | .. |
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286 | 301 | status = "disabled"; |
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287 | 302 | }; |
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288 | 303 | |
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289 | | - esdhc3: esdhc@50020000 { |
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| 304 | + esdhc3: mmc@50020000 { |
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290 | 305 | compatible = "fsl,imx53-esdhc"; |
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291 | 306 | reg = <0x50020000 0x4000>; |
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292 | 307 | interrupts = <3>; |
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.. | .. |
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298 | 313 | status = "disabled"; |
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299 | 314 | }; |
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300 | 315 | |
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301 | | - esdhc4: esdhc@50024000 { |
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| 316 | + esdhc4: mmc@50024000 { |
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302 | 317 | compatible = "fsl,imx53-esdhc"; |
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303 | 318 | reg = <0x50024000 0x4000>; |
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304 | 319 | interrupts = <4>; |
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.. | .. |
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510 | 525 | }; |
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511 | 526 | |
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512 | 527 | pwm1: pwm@53fb4000 { |
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513 | | - #pwm-cells = <2>; |
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| 528 | + #pwm-cells = <3>; |
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514 | 529 | compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; |
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515 | 530 | reg = <0x53fb4000 0x4000>; |
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516 | 531 | clocks = <&clks IMX5_CLK_PWM1_IPG_GATE>, |
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.. | .. |
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520 | 535 | }; |
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521 | 536 | |
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522 | 537 | pwm2: pwm@53fb8000 { |
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523 | | - #pwm-cells = <2>; |
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| 538 | + #pwm-cells = <3>; |
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524 | 539 | compatible = "fsl,imx53-pwm", "fsl,imx27-pwm"; |
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525 | 540 | reg = <0x53fb8000 0x4000>; |
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526 | 541 | clocks = <&clks IMX5_CLK_PWM2_IPG_GATE>, |
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.. | .. |
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573 | 588 | status = "disabled"; |
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574 | 589 | }; |
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575 | 590 | |
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576 | | - src: src@53fd0000 { |
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| 591 | + src: reset-controller@53fd0000 { |
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577 | 592 | compatible = "fsl,imx53-src", "fsl,imx51-src"; |
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578 | 593 | reg = <0x53fd0000 0x4000>; |
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| 594 | + interrupts = <75>; |
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579 | 595 | #reset-cells = <1>; |
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580 | 596 | }; |
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581 | 597 | |
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.. | .. |
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639 | 655 | }; |
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640 | 656 | }; |
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641 | 657 | |
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642 | | - aips@60000000 { /* AIPS2 */ |
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| 658 | + bus@60000000 { /* AIPS2 */ |
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643 | 659 | compatible = "fsl,aips-bus", "simple-bus"; |
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644 | 660 | #address-cells = <1>; |
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645 | 661 | #size-cells = <1>; |
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.. | .. |
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651 | 667 | reg = <0x63f00000 0x60>; |
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652 | 668 | }; |
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653 | 669 | |
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654 | | - iim: iim@63f98000 { |
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| 670 | + iim: efuse@63f98000 { |
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655 | 671 | compatible = "fsl,imx53-iim", "fsl,imx27-iim"; |
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656 | 672 | reg = <0x63f98000 0x4000>; |
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657 | 673 | interrupts = <69>; |
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.. | .. |
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682 | 698 | status = "disabled"; |
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683 | 699 | }; |
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684 | 700 | |
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685 | | - ecspi2: ecspi@63fac000 { |
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| 701 | + ecspi2: spi@63fac000 { |
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686 | 702 | #address-cells = <1>; |
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687 | 703 | #size-cells = <0>; |
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688 | 704 | compatible = "fsl,imx53-ecspi", "fsl,imx51-ecspi"; |
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.. | .. |
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705 | 721 | fsl,sdma-ram-script-name = "imx/sdma/sdma-imx53.bin"; |
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706 | 722 | }; |
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707 | 723 | |
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708 | | - cspi: cspi@63fc0000 { |
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| 724 | + cspi: spi@63fc0000 { |
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709 | 725 | #address-cells = <1>; |
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710 | 726 | #size-cells = <0>; |
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711 | 727 | compatible = "fsl,imx53-cspi", "fsl,imx35-cspi"; |
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