~ljy/RK356X_SDK_RELEASE.git

..	..	@@ -7,11 +7,15 @@
7	7	* Mika Westerberg <mika.westerberg@linux.intel.com>
8	8	*/
9	9
10		-#include <linux/module.h>
11		-#include <linux/interrupt.h>
	10	+#include <linux/acpi.h>
12	11	#include <linux/gpio/driver.h>
	12	+#include <linux/interrupt.h>
13	13	#include <linux/log2.h>
	14	+#include <linux/module.h>
14	15	#include <linux/platform_device.h>
	16	+#include <linux/property.h>
	17	+#include <linux/time.h>
	18	+
15	19	#include <linux/pinctrl/pinctrl.h>
16	20	#include <linux/pinctrl/pinmux.h>
17	21	#include <linux/pinctrl/pinconf.h>
..	..	@@ -26,17 +30,16 @@
26	30	#define REVID_MASK GENMASK(31, 16)
27	31
28	32	#define PADBAR 0x00c
29		-#define GPI_IS 0x100
30	33
31	34	#define PADOWN_BITS 4
32	35	#define PADOWN_SHIFT(p) ((p) % 8 * PADOWN_BITS)
33		-#define PADOWN_MASK(p) (0xf << PADOWN_SHIFT(p))
	36	+#define PADOWN_MASK(p) (GENMASK(3, 0) << PADOWN_SHIFT(p))
34	37	#define PADOWN_GPP(p) ((p) / 8)
35	38
36	39	/* Offset from pad_regs */
37	40	#define PADCFG0 0x000
38	41	#define PADCFG0_RXEVCFG_SHIFT 25
39		-#define PADCFG0_RXEVCFG_MASK (3 << PADCFG0_RXEVCFG_SHIFT)
	42	+#define PADCFG0_RXEVCFG_MASK GENMASK(26, 25)
40	43	#define PADCFG0_RXEVCFG_LEVEL 0
41	44	#define PADCFG0_RXEVCFG_EDGE 1
42	45	#define PADCFG0_RXEVCFG_DISABLED 2
..	..	@@ -48,7 +51,7 @@
48	51	#define PADCFG0_GPIROUTSMI BIT(18)
49	52	#define PADCFG0_GPIROUTNMI BIT(17)
50	53	#define PADCFG0_PMODE_SHIFT 10
51		-#define PADCFG0_PMODE_MASK (0xf << PADCFG0_PMODE_SHIFT)
	54	+#define PADCFG0_PMODE_MASK GENMASK(13, 10)
52	55	#define PADCFG0_PMODE_GPIO 0
53	56	#define PADCFG0_GPIORXDIS BIT(9)
54	57	#define PADCFG0_GPIOTXDIS BIT(8)
..	..	@@ -58,18 +61,18 @@
58	61	#define PADCFG1 0x004
59	62	#define PADCFG1_TERM_UP BIT(13)
60	63	#define PADCFG1_TERM_SHIFT 10
61		-#define PADCFG1_TERM_MASK (7 << PADCFG1_TERM_SHIFT)
62		-#define PADCFG1_TERM_20K 4
63		-#define PADCFG1_TERM_2K 3
64		-#define PADCFG1_TERM_5K 2
65		-#define PADCFG1_TERM_1K 1
	64	+#define PADCFG1_TERM_MASK GENMASK(12, 10)
	65	+#define PADCFG1_TERM_20K BIT(2)
	66	+#define PADCFG1_TERM_5K BIT(1)
	67	+#define PADCFG1_TERM_1K BIT(0)
	68	+#define PADCFG1_TERM_833 (BIT(1) \| BIT(0))
66	69
67	70	#define PADCFG2 0x008
68	71	#define PADCFG2_DEBEN BIT(0)
69	72	#define PADCFG2_DEBOUNCE_SHIFT 1
70	73	#define PADCFG2_DEBOUNCE_MASK GENMASK(4, 1)
71	74
72		-#define DEBOUNCE_PERIOD 31250 /* ns */
	75	+#define DEBOUNCE_PERIOD_NSEC 31250
73	76
74	77	struct intel_pad_context {
75	78	u32 padcfg0;
..	..	@@ -79,44 +82,14 @@
79	82
80	83	struct intel_community_context {
81	84	u32 *intmask;
82		-};
83		-
84		-struct intel_pinctrl_context {
85		- struct intel_pad_context *pads;
86		- struct intel_community_context *communities;
87		-};
88		-
89		-/**
90		- * struct intel_pinctrl - Intel pinctrl private structure
91		- * @dev: Pointer to the device structure
92		- * @lock: Lock to serialize register access
93		- * @pctldesc: Pin controller description
94		- * @pctldev: Pointer to the pin controller device
95		- * @chip: GPIO chip in this pin controller
96		- * @soc: SoC/PCH specific pin configuration data
97		- * @communities: All communities in this pin controller
98		- * @ncommunities: Number of communities in this pin controller
99		- * @context: Configuration saved over system sleep
100		- * @irq: pinctrl/GPIO chip irq number
101		- */
102		-struct intel_pinctrl {
103		- struct device *dev;
104		- raw_spinlock_t lock;
105		- struct pinctrl_desc pctldesc;
106		- struct pinctrl_dev *pctldev;
107		- struct gpio_chip chip;
108		- const struct intel_pinctrl_soc_data *soc;
109		- struct intel_community *communities;
110		- size_t ncommunities;
111		- struct intel_pinctrl_context context;
112		- int irq;
	85	+ u32 *hostown;
113	86	};
114	87
115	88	#define pin_to_padno(c, p) ((p) - (c)->pin_base)
116	89	#define padgroup_offset(g, p) ((p) - (g)->base)
117	90
118	91	static struct intel_community intel_get_community(struct intel_pinctrl pctrl,
119		- unsigned pin)
	92	+ unsigned int pin)
120	93	{
121	94	struct intel_community *community;
122	95	int i;
..	..	@@ -134,7 +107,7 @@
134	107
135	108	static const struct intel_padgroup *
136	109	intel_community_get_padgroup(const struct intel_community *community,
137		- unsigned pin)
	110	+ unsigned int pin)
138	111	{
139	112	int i;
140	113
..	..	@@ -148,11 +121,11 @@
148	121	return NULL;
149	122	}
150	123
151		-static void __iomem intel_get_padcfg(struct intel_pinctrl pctrl, unsigned pin,
152		- unsigned reg)
	124	+static void __iomem intel_get_padcfg(struct intel_pinctrl pctrl,
	125	+ unsigned int pin, unsigned int reg)
153	126	{
154	127	const struct intel_community *community;
155		- unsigned padno;
	128	+ unsigned int padno;
156	129	size_t nregs;
157	130
158	131	community = intel_get_community(pctrl, pin);
..	..	@@ -162,17 +135,17 @@
162	135	padno = pin_to_padno(community, pin);
163	136	nregs = (community->features & PINCTRL_FEATURE_DEBOUNCE) ? 4 : 2;
164	137
165		- if (reg == PADCFG2 && !(community->features & PINCTRL_FEATURE_DEBOUNCE))
	138	+ if (reg >= nregs * 4)
166	139	return NULL;
167	140
168	141	return community->pad_regs + reg + padno * nregs * 4;
169	142	}
170	143
171		-static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned pin)
	144	+static bool intel_pad_owned_by_host(struct intel_pinctrl *pctrl, unsigned int pin)
172	145	{
173	146	const struct intel_community *community;
174	147	const struct intel_padgroup *padgrp;
175		- unsigned gpp, offset, gpp_offset;
	148	+ unsigned int gpp, offset, gpp_offset;
176	149	void __iomem *padown;
177	150
178	151	community = intel_get_community(pctrl, pin);
..	..	@@ -193,11 +166,11 @@
193	166	return !(readl(padown) & PADOWN_MASK(gpp_offset));
194	167	}
195	168
196		-static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned pin)
	169	+static bool intel_pad_acpi_mode(struct intel_pinctrl *pctrl, unsigned int pin)
197	170	{
198	171	const struct intel_community *community;
199	172	const struct intel_padgroup *padgrp;
200		- unsigned offset, gpp_offset;
	173	+ unsigned int offset, gpp_offset;
201	174	void __iomem *hostown;
202	175
203	176	community = intel_get_community(pctrl, pin);
..	..	@@ -217,47 +190,71 @@
217	190	return !(readl(hostown) & BIT(gpp_offset));
218	191	}
219	192
220		-static bool intel_pad_locked(struct intel_pinctrl *pctrl, unsigned pin)
	193	+/**
	194	+ * enum - Locking variants of the pad configuration
	195	+ *
	196	+ * @PAD_UNLOCKED: pad is fully controlled by the configuration registers
	197	+ * @PAD_LOCKED: pad configuration registers, except TX state, are locked
	198	+ * @PAD_LOCKED_TX: pad configuration TX state is locked
	199	+ * @PAD_LOCKED_FULL: pad configuration registers are locked completely
	200	+ *
	201	+ * Locking is considered as read-only mode for corresponding registers and
	202	+ * their respective fields. That said, TX state bit is locked separately from
	203	+ * the main locking scheme.
	204	+ */
	205	+enum {
	206	+ PAD_UNLOCKED = 0,
	207	+ PAD_LOCKED = 1,
	208	+ PAD_LOCKED_TX = 2,
	209	+ PAD_LOCKED_FULL = PAD_LOCKED \| PAD_LOCKED_TX,
	210	+};
	211	+
	212	+static int intel_pad_locked(struct intel_pinctrl *pctrl, unsigned int pin)
221	213	{
222	214	struct intel_community *community;
223	215	const struct intel_padgroup *padgrp;
224		- unsigned offset, gpp_offset;
	216	+ unsigned int offset, gpp_offset;
225	217	u32 value;
	218	+ int ret = PAD_UNLOCKED;
226	219
227	220	community = intel_get_community(pctrl, pin);
228	221	if (!community)
229		- return true;
	222	+ return PAD_LOCKED_FULL;
230	223	if (!community->padcfglock_offset)
231		- return false;
	224	+ return PAD_UNLOCKED;
232	225
233	226	padgrp = intel_community_get_padgroup(community, pin);
234	227	if (!padgrp)
235		- return true;
	228	+ return PAD_LOCKED_FULL;
236	229
237	230	gpp_offset = padgroup_offset(padgrp, pin);
238	231
239	232	/*
240	233	* If PADCFGLOCK and PADCFGLOCKTX bits are both clear for this pad,
241	234	* the pad is considered unlocked. Any other case means that it is
242		- * either fully or partially locked and we don't touch it.
	235	+ * either fully or partially locked.
243	236	*/
244		- offset = community->padcfglock_offset + padgrp->reg_num * 8;
	237	+ offset = community->padcfglock_offset + 0 + padgrp->reg_num * 8;
245	238	value = readl(community->regs + offset);
246	239	if (value & BIT(gpp_offset))
247		- return true;
	240	+ ret \|= PAD_LOCKED;
248	241
249	242	offset = community->padcfglock_offset + 4 + padgrp->reg_num * 8;
250	243	value = readl(community->regs + offset);
251	244	if (value & BIT(gpp_offset))
252		- return true;
	245	+ ret \|= PAD_LOCKED_TX;
253	246
254		- return false;
	247	+ return ret;
255	248	}
256	249
257		-static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned pin)
	250	+static bool intel_pad_is_unlocked(struct intel_pinctrl *pctrl, unsigned int pin)
258	251	{
259		- return intel_pad_owned_by_host(pctrl, pin) &&
260		- !intel_pad_locked(pctrl, pin);
	252	+ return (intel_pad_locked(pctrl, pin) & PAD_LOCKED) == PAD_UNLOCKED;
	253	+}
	254	+
	255	+static bool intel_pad_usable(struct intel_pinctrl *pctrl, unsigned int pin)
	256	+{
	257	+ return intel_pad_owned_by_host(pctrl, pin) && intel_pad_is_unlocked(pctrl, pin);
261	258	}
262	259
263	260	static int intel_get_groups_count(struct pinctrl_dev *pctldev)
..	..	@@ -268,15 +265,15 @@
268	265	}
269	266
270	267	static const char intel_get_group_name(struct pinctrl_dev pctldev,
271		- unsigned group)
	268	+ unsigned int group)
272	269	{
273	270	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
274	271
275	272	return pctrl->soc->groups[group].name;
276	273	}
277	274
278		-static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned group,
279		- const unsigned *pins, unsigned npins)
	275	+static int intel_get_group_pins(struct pinctrl_dev *pctldev, unsigned int group,
	276	+ const unsigned int *pins, unsigned int npins)
280	277	{
281	278	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
282	279
..	..	@@ -286,12 +283,13 @@
286	283	}
287	284
288	285	static void intel_pin_dbg_show(struct pinctrl_dev pctldev, struct seq_file s,
289		- unsigned pin)
	286	+ unsigned int pin)
290	287	{
291	288	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
292	289	void __iomem *padcfg;
293	290	u32 cfg0, cfg1, mode;
294		- bool locked, acpi;
	291	+ int locked;
	292	+ bool acpi;
295	293
296	294	if (!intel_pad_owned_by_host(pctrl, pin)) {
297	295	seq_puts(s, "not available");
..	..	@@ -319,11 +317,16 @@
319	317
320	318	if (locked \|\| acpi) {
321	319	seq_puts(s, " [");
322		- if (locked) {
	320	+ if (locked)
323	321	seq_puts(s, "LOCKED");
324		- if (acpi)
325		- seq_puts(s, ", ");
326		- }
	322	+ if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_TX)
	323	+ seq_puts(s, " tx");
	324	+ else if ((locked & PAD_LOCKED_FULL) == PAD_LOCKED_FULL)
	325	+ seq_puts(s, " full");
	326	+
	327	+ if (locked && acpi)
	328	+ seq_puts(s, ", ");
	329	+
327	330	if (acpi)
328	331	seq_puts(s, "ACPI");
329	332	seq_puts(s, "]");
..	..	@@ -345,7 +348,7 @@
345	348	}
346	349
347	350	static const char intel_get_function_name(struct pinctrl_dev pctldev,
348		- unsigned function)
	351	+ unsigned int function)
349	352	{
350	353	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
351	354
..	..	@@ -353,9 +356,9 @@
353	356	}
354	357
355	358	static int intel_get_function_groups(struct pinctrl_dev *pctldev,
356		- unsigned function,
	359	+ unsigned int function,
357	360	const char * const **groups,
358		- unsigned * const ngroups)
	361	+ unsigned int * const ngroups)
359	362	{
360	363	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
361	364
..	..	@@ -364,8 +367,8 @@
364	367	return 0;
365	368	}
366	369
367		-static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev, unsigned function,
368		- unsigned group)
	370	+static int intel_pinmux_set_mux(struct pinctrl_dev *pctldev,
	371	+ unsigned int function, unsigned int group)
369	372	{
370	373	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
371	374	const struct intel_pingroup *grp = &pctrl->soc->groups[group];
..	..	@@ -423,39 +426,58 @@
423	426	writel(value, padcfg0);
424	427	}
425	428
	429	+static int __intel_gpio_get_gpio_mode(u32 value)
	430	+{
	431	+ return (value & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
	432	+}
	433	+
426	434	static int intel_gpio_get_gpio_mode(void __iomem *padcfg0)
427	435	{
428		- return (readl(padcfg0) & PADCFG0_PMODE_MASK) >> PADCFG0_PMODE_SHIFT;
	436	+ return __intel_gpio_get_gpio_mode(readl(padcfg0));
429	437	}
430	438
431	439	static void intel_gpio_set_gpio_mode(void __iomem *padcfg0)
432	440	{
433	441	u32 value;
434	442
	443	+ value = readl(padcfg0);
	444	+
435	445	/* Put the pad into GPIO mode */
436		- value = readl(padcfg0) & ~PADCFG0_PMODE_MASK;
	446	+ value &= ~PADCFG0_PMODE_MASK;
	447	+ value \|= PADCFG0_PMODE_GPIO;
	448	+
	449	+ /* Disable TX buffer and enable RX (this will be input) */
	450	+ value &= ~PADCFG0_GPIORXDIS;
	451	+ value \|= PADCFG0_GPIOTXDIS;
	452	+
437	453	/* Disable SCI/SMI/NMI generation */
438	454	value &= ~(PADCFG0_GPIROUTIOXAPIC \| PADCFG0_GPIROUTSCI);
439	455	value &= ~(PADCFG0_GPIROUTSMI \| PADCFG0_GPIROUTNMI);
	456	+
440	457	writel(value, padcfg0);
441	458	}
442	459
443	460	static int intel_gpio_request_enable(struct pinctrl_dev *pctldev,
444	461	struct pinctrl_gpio_range *range,
445		- unsigned pin)
	462	+ unsigned int pin)
446	463	{
447	464	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
448	465	void __iomem *padcfg0;
449	466	unsigned long flags;
450	467
	468	+ padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
	469	+
451	470	raw_spin_lock_irqsave(&pctrl->lock, flags);
452	471
453		- if (!intel_pad_usable(pctrl, pin)) {
	472	+ if (!intel_pad_owned_by_host(pctrl, pin)) {
454	473	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
455	474	return -EBUSY;
456	475	}
457	476
458		- padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
	477	+ if (!intel_pad_is_unlocked(pctrl, pin)) {
	478	+ raw_spin_unlock_irqrestore(&pctrl->lock, flags);
	479	+ return 0;
	480	+ }
459	481
460	482	/*
461	483	* If pin is already configured in GPIO mode, we assume that
..	..	@@ -470,9 +492,6 @@
470	492
471	493	intel_gpio_set_gpio_mode(padcfg0);
472	494
473		- /* Disable TX buffer and enable RX (this will be input) */
474		- __intel_gpio_set_direction(padcfg0, true);
475		-
476	495	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
477	496
478	497	return 0;
..	..	@@ -480,17 +499,16 @@
480	499
481	500	static int intel_gpio_set_direction(struct pinctrl_dev *pctldev,
482	501	struct pinctrl_gpio_range *range,
483		- unsigned pin, bool input)
	502	+ unsigned int pin, bool input)
484	503	{
485	504	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
486	505	void __iomem *padcfg0;
487	506	unsigned long flags;
488	507
489		- raw_spin_lock_irqsave(&pctrl->lock, flags);
490		-
491	508	padcfg0 = intel_get_padcfg(pctrl, pin, PADCFG0);
492		- __intel_gpio_set_direction(padcfg0, input);
493	509
	510	+ raw_spin_lock_irqsave(&pctrl->lock, flags);
	511	+ __intel_gpio_set_direction(padcfg0, input);
494	512	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
495	513
496	514	return 0;
..	..	@@ -505,20 +523,21 @@
505	523	.gpio_set_direction = intel_gpio_set_direction,
506	524	};
507	525
508		-static int intel_config_get(struct pinctrl_dev *pctldev, unsigned pin,
509		- unsigned long *config)
	526	+static int intel_config_get_pull(struct intel_pinctrl *pctrl, unsigned int pin,
	527	+ enum pin_config_param param, u32 *arg)
510	528	{
511		- struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
512		- enum pin_config_param param = pinconf_to_config_param(*config);
513	529	const struct intel_community *community;
	530	+ void __iomem *padcfg1;
	531	+ unsigned long flags;
514	532	u32 value, term;
515		- u32 arg = 0;
516		-
517		- if (!intel_pad_owned_by_host(pctrl, pin))
518		- return -ENOTSUPP;
519	533
520	534	community = intel_get_community(pctrl, pin);
521		- value = readl(intel_get_padcfg(pctrl, pin, PADCFG1));
	535	+ padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
	536	+
	537	+ raw_spin_lock_irqsave(&pctrl->lock, flags);
	538	+ value = readl(padcfg1);
	539	+ raw_spin_unlock_irqrestore(&pctrl->lock, flags);
	540	+
522	541	term = (value & PADCFG1_TERM_MASK) >> PADCFG1_TERM_SHIFT;
523	542
524	543	switch (param) {
..	..	@@ -532,17 +551,17 @@
532	551	return -EINVAL;
533	552
534	553	switch (term) {
535		- case PADCFG1_TERM_1K:
536		- arg = 1000;
	554	+ case PADCFG1_TERM_833:
	555	+ *arg = 833;
537	556	break;
538		- case PADCFG1_TERM_2K:
539		- arg = 2000;
	557	+ case PADCFG1_TERM_1K:
	558	+ *arg = 1000;
540	559	break;
541	560	case PADCFG1_TERM_5K:
542		- arg = 5000;
	561	+ *arg = 5000;
543	562	break;
544	563	case PADCFG1_TERM_20K:
545		- arg = 20000;
	564	+ *arg = 20000;
546	565	break;
547	566	}
548	567
..	..	@@ -553,38 +572,82 @@
553	572	return -EINVAL;
554	573
555	574	switch (term) {
	575	+ case PADCFG1_TERM_833:
	576	+ if (!(community->features & PINCTRL_FEATURE_1K_PD))
	577	+ return -EINVAL;
	578	+ *arg = 833;
	579	+ break;
556	580	case PADCFG1_TERM_1K:
557	581	if (!(community->features & PINCTRL_FEATURE_1K_PD))
558	582	return -EINVAL;
559		- arg = 1000;
	583	+ *arg = 1000;
560	584	break;
561	585	case PADCFG1_TERM_5K:
562		- arg = 5000;
	586	+ *arg = 5000;
563	587	break;
564	588	case PADCFG1_TERM_20K:
565		- arg = 20000;
	589	+ *arg = 20000;
566	590	break;
567	591	}
568	592
569	593	break;
570	594
571		- case PIN_CONFIG_INPUT_DEBOUNCE: {
572		- void __iomem *padcfg2;
573		- u32 v;
574		-
575		- padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
576		- if (!padcfg2)
577		- return -ENOTSUPP;
578		-
579		- v = readl(padcfg2);
580		- if (!(v & PADCFG2_DEBEN))
581		- return -EINVAL;
582		-
583		- v = (v & PADCFG2_DEBOUNCE_MASK) >> PADCFG2_DEBOUNCE_SHIFT;
584		- arg = BIT(v) * DEBOUNCE_PERIOD / 1000;
585		-
586		- break;
	595	+ default:
	596	+ return -EINVAL;
587	597	}
	598	+
	599	+ return 0;
	600	+}
	601	+
	602	+static int intel_config_get_debounce(struct intel_pinctrl *pctrl, unsigned int pin,
	603	+ enum pin_config_param param, u32 *arg)
	604	+{
	605	+ void __iomem *padcfg2;
	606	+ unsigned long flags;
	607	+ unsigned long v;
	608	+ u32 value2;
	609	+
	610	+ padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
	611	+ if (!padcfg2)
	612	+ return -ENOTSUPP;
	613	+
	614	+ raw_spin_lock_irqsave(&pctrl->lock, flags);
	615	+ value2 = readl(padcfg2);
	616	+ raw_spin_unlock_irqrestore(&pctrl->lock, flags);
	617	+ if (!(value2 & PADCFG2_DEBEN))
	618	+ return -EINVAL;
	619	+
	620	+ v = (value2 & PADCFG2_DEBOUNCE_MASK) >> PADCFG2_DEBOUNCE_SHIFT;
	621	+ arg = BIT(v) DEBOUNCE_PERIOD_NSEC / NSEC_PER_USEC;
	622	+
	623	+ return 0;
	624	+}
	625	+
	626	+static int intel_config_get(struct pinctrl_dev *pctldev, unsigned int pin,
	627	+ unsigned long *config)
	628	+{
	629	+ struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
	630	+ enum pin_config_param param = pinconf_to_config_param(*config);
	631	+ u32 arg = 0;
	632	+ int ret;
	633	+
	634	+ if (!intel_pad_owned_by_host(pctrl, pin))
	635	+ return -ENOTSUPP;
	636	+
	637	+ switch (param) {
	638	+ case PIN_CONFIG_BIAS_DISABLE:
	639	+ case PIN_CONFIG_BIAS_PULL_UP:
	640	+ case PIN_CONFIG_BIAS_PULL_DOWN:
	641	+ ret = intel_config_get_pull(pctrl, pin, param, &arg);
	642	+ if (ret)
	643	+ return ret;
	644	+ break;
	645	+
	646	+ case PIN_CONFIG_INPUT_DEBOUNCE:
	647	+ ret = intel_config_get_debounce(pctrl, pin, param, &arg);
	648	+ if (ret)
	649	+ return ret;
	650	+ break;
588	651
589	652	default:
590	653	return -ENOTSUPP;
..	..	@@ -594,21 +657,22 @@
594	657	return 0;
595	658	}
596	659
597		-static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned pin,
	660	+static int intel_config_set_pull(struct intel_pinctrl *pctrl, unsigned int pin,
598	661	unsigned long config)
599	662	{
600		- unsigned param = pinconf_to_config_param(config);
601		- unsigned arg = pinconf_to_config_argument(config);
	663	+ unsigned int param = pinconf_to_config_param(config);
	664	+ unsigned int arg = pinconf_to_config_argument(config);
602	665	const struct intel_community *community;
603	666	void __iomem *padcfg1;
604	667	unsigned long flags;
605	668	int ret = 0;
606	669	u32 value;
607	670
608		- raw_spin_lock_irqsave(&pctrl->lock, flags);
609		-
610	671	community = intel_get_community(pctrl, pin);
611	672	padcfg1 = intel_get_padcfg(pctrl, pin, PADCFG1);
	673	+
	674	+ raw_spin_lock_irqsave(&pctrl->lock, flags);
	675	+
612	676	value = readl(padcfg1);
613	677
614	678	switch (param) {
..	..	@@ -632,11 +696,11 @@
632	696	case 5000:
633	697	value \|= PADCFG1_TERM_5K << PADCFG1_TERM_SHIFT;
634	698	break;
635		- case 2000:
636		- value \|= PADCFG1_TERM_2K << PADCFG1_TERM_SHIFT;
637		- break;
638	699	case 1000:
639	700	value \|= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
	701	+ break;
	702	+ case 833:
	703	+ value \|= PADCFG1_TERM_833 << PADCFG1_TERM_SHIFT;
640	704	break;
641	705	default:
642	706	ret = -EINVAL;
..	..	@@ -665,6 +729,13 @@
665	729	}
666	730	value \|= PADCFG1_TERM_1K << PADCFG1_TERM_SHIFT;
667	731	break;
	732	+ case 833:
	733	+ if (!(community->features & PINCTRL_FEATURE_1K_PD)) {
	734	+ ret = -EINVAL;
	735	+ break;
	736	+ }
	737	+ value \|= PADCFG1_TERM_833 << PADCFG1_TERM_SHIFT;
	738	+ break;
668	739	default:
669	740	ret = -EINVAL;
670	741	}
..	..	@@ -680,13 +751,12 @@
680	751	return ret;
681	752	}
682	753
683		-static int intel_config_set_debounce(struct intel_pinctrl *pctrl, unsigned pin,
684		- unsigned debounce)
	754	+static int intel_config_set_debounce(struct intel_pinctrl *pctrl,
	755	+ unsigned int pin, unsigned int debounce)
685	756	{
686	757	void __iomem padcfg0, padcfg2;
687	758	unsigned long flags;
688	759	u32 value0, value2;
689		- int ret = 0;
690	760
691	761	padcfg2 = intel_get_padcfg(pctrl, pin, PADCFG2);
692	762	if (!padcfg2)
..	..	@@ -706,29 +776,28 @@
706	776	if (debounce) {
707	777	unsigned long v;
708	778
709		- v = order_base_2(debounce * 1000 / DEBOUNCE_PERIOD);
	779	+ v = order_base_2(debounce * NSEC_PER_USEC / DEBOUNCE_PERIOD_NSEC);
710	780	if (v < 3 \|\| v > 15) {
711		- ret = -EINVAL;
712		- goto exit_unlock;
713		- } else {
714		- /* Enable glitch filter and debouncer */
715		- value0 \|= PADCFG0_PREGFRXSEL;
716		- value2 \|= v << PADCFG2_DEBOUNCE_SHIFT;
717		- value2 \|= PADCFG2_DEBEN;
	781	+ raw_spin_unlock_irqrestore(&pctrl->lock, flags);
	782	+ return -EINVAL;
718	783	}
	784	+
	785	+ /* Enable glitch filter and debouncer */
	786	+ value0 \|= PADCFG0_PREGFRXSEL;
	787	+ value2 \|= v << PADCFG2_DEBOUNCE_SHIFT;
	788	+ value2 \|= PADCFG2_DEBEN;
719	789	}
720	790
721	791	writel(value0, padcfg0);
722	792	writel(value2, padcfg2);
723	793
724		-exit_unlock:
725	794	raw_spin_unlock_irqrestore(&pctrl->lock, flags);
726	795
727		- return ret;
	796	+ return 0;
728	797	}
729	798
730		-static int intel_config_set(struct pinctrl_dev *pctldev, unsigned pin,
731		- unsigned long *configs, unsigned nconfigs)
	799	+static int intel_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
	800	+ unsigned long *configs, unsigned int nconfigs)
732	801	{
733	802	struct intel_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
734	803	int i, ret;
..	..	@@ -778,14 +847,14 @@
778	847	* intel_gpio_to_pin() - Translate from GPIO offset to pin number
779	848	* @pctrl: Pinctrl structure
780	849	* @offset: GPIO offset from gpiolib
781		- * @commmunity: Community is filled here if not %NULL
	850	+ * @community: Community is filled here if not %NULL
782	851	* @padgrp: Pad group is filled here if not %NULL
783	852	*
784	853	* When coming through gpiolib irqchip, the GPIO offset is not
785	854	* automatically translated to pinctrl pin number. This function can be
786	855	* used to find out the corresponding pinctrl pin.
787	856	*/
788		-static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned offset,
	857	+static int intel_gpio_to_pin(struct intel_pinctrl *pctrl, unsigned int offset,
789	858	const struct intel_community **community,
790	859	const struct intel_padgroup **padgrp)
791	860	{
..	..	@@ -798,7 +867,7 @@
798	867	for (j = 0; j < comm->ngpps; j++) {
799	868	const struct intel_padgroup *pgrp = &comm->gpps[j];
800	869
801		- if (pgrp->gpio_base < 0)
	870	+ if (pgrp->gpio_base == INTEL_GPIO_BASE_NOMAP)
802	871	continue;
803	872
804	873	if (offset >= pgrp->gpio_base &&
..	..	@@ -819,7 +888,30 @@
819	888	return -EINVAL;
820	889	}
821	890
822		-static int intel_gpio_get(struct gpio_chip *chip, unsigned offset)
	891	+/**
	892	+ * intel_pin_to_gpio() - Translate from pin number to GPIO offset
	893	+ * @pctrl: Pinctrl structure
	894	+ * @pin: pin number
	895	+ *
	896	+ * Translate the pin number of pinctrl to GPIO offset
	897	+ */
	898	+static __maybe_unused int intel_pin_to_gpio(struct intel_pinctrl *pctrl, int pin)
	899	+{
	900	+ const struct intel_community *community;
	901	+ const struct intel_padgroup *padgrp;
	902	+
	903	+ community = intel_get_community(pctrl, pin);
	904	+ if (!community)
	905	+ return -EINVAL;
	906	+
	907	+ padgrp = intel_community_get_padgroup(community, pin);
	908	+ if (!padgrp)
	909	+ return -EINVAL;
	910	+
	911	+ return pin - padgrp->base + padgrp->gpio_base;
	912	+}
	913	+
	914	+static int intel_gpio_get(struct gpio_chip *chip, unsigned int offset)
823	915	{
824	916	struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
825	917	void __iomem *reg;
..	..	@@ -841,7 +933,8 @@
841	933	return !!(padcfg0 & PADCFG0_GPIORXSTATE);
842	934	}
843	935
844		-static void intel_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
	936	+static void intel_gpio_set(struct gpio_chip *chip, unsigned int offset,
	937	+ int value)
845	938	{
846	939	struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
847	940	unsigned long flags;
..	..	@@ -870,6 +963,7 @@
870	963	static int intel_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
871	964	{
872	965	struct intel_pinctrl *pctrl = gpiochip_get_data(chip);
	966	+ unsigned long flags;
873	967	void __iomem *reg;
874	968	u32 padcfg0;
875	969	int pin;
..	..	@@ -882,20 +976,24 @@
882	976	if (!reg)
883	977	return -EINVAL;
884	978
	979	+ raw_spin_lock_irqsave(&pctrl->lock, flags);
885	980	padcfg0 = readl(reg);
886		-
	981	+ raw_spin_unlock_irqrestore(&pctrl->lock, flags);
887	982	if (padcfg0 & PADCFG0_PMODE_MASK)
888	983	return -EINVAL;
889	984
890		- return !!(padcfg0 & PADCFG0_GPIOTXDIS);
	985	+ if (padcfg0 & PADCFG0_GPIOTXDIS)
	986	+ return GPIO_LINE_DIRECTION_IN;
	987	+
	988	+ return GPIO_LINE_DIRECTION_OUT;
891	989	}
892	990
893		-static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
	991	+static int intel_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
894	992	{
895	993	return pinctrl_gpio_direction_input(chip->base + offset);
896	994	}
897	995
898		-static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
	996	+static int intel_gpio_direction_output(struct gpio_chip *chip, unsigned int offset,
899	997	int value)
900	998	{
901	999	intel_gpio_set(chip, offset, value);
..	..	@@ -924,7 +1022,7 @@
924	1022
925	1023	pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
926	1024	if (pin >= 0) {
927		- unsigned gpp, gpp_offset, is_offset;
	1025	+ unsigned int gpp, gpp_offset, is_offset;
928	1026
929	1027	gpp = padgrp->reg_num;
930	1028	gpp_offset = padgroup_offset(padgrp, pin);
..	..	@@ -933,35 +1031,6 @@
933	1031	raw_spin_lock(&pctrl->lock);
934	1032	writel(BIT(gpp_offset), community->regs + is_offset);
935	1033	raw_spin_unlock(&pctrl->lock);
936		- }
937		-}
938		-
939		-static void intel_gpio_irq_enable(struct irq_data *d)
940		-{
941		- struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
942		- struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
943		- const struct intel_community *community;
944		- const struct intel_padgroup *padgrp;
945		- int pin;
946		-
947		- pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
948		- if (pin >= 0) {
949		- unsigned gpp, gpp_offset, is_offset;
950		- unsigned long flags;
951		- u32 value;
952		-
953		- gpp = padgrp->reg_num;
954		- gpp_offset = padgroup_offset(padgrp, pin);
955		- is_offset = community->is_offset + gpp * 4;
956		-
957		- raw_spin_lock_irqsave(&pctrl->lock, flags);
958		- /* Clear interrupt status first to avoid unexpected interrupt */
959		- writel(BIT(gpp_offset), community->regs + is_offset);
960		-
961		- value = readl(community->regs + community->ie_offset + gpp * 4);
962		- value \|= BIT(gpp_offset);
963		- writel(value, community->regs + community->ie_offset + gpp * 4);
964		- raw_spin_unlock_irqrestore(&pctrl->lock, flags);
965	1034	}
966	1035	}
967	1036
..	..	@@ -975,17 +1044,22 @@
975	1044
976	1045	pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), &community, &padgrp);
977	1046	if (pin >= 0) {
978		- unsigned gpp, gpp_offset;
	1047	+ unsigned int gpp, gpp_offset;
979	1048	unsigned long flags;
980		- void __iomem *reg;
	1049	+ void __iomem reg, is;
981	1050	u32 value;
982	1051
983	1052	gpp = padgrp->reg_num;
984	1053	gpp_offset = padgroup_offset(padgrp, pin);
985	1054
986	1055	reg = community->regs + community->ie_offset + gpp * 4;
	1056	+ is = community->regs + community->is_offset + gpp * 4;
987	1057
988	1058	raw_spin_lock_irqsave(&pctrl->lock, flags);
	1059	+
	1060	+ /* Clear interrupt status first to avoid unexpected interrupt */
	1061	+ writel(BIT(gpp_offset), is);
	1062	+
989	1063	value = readl(reg);
990	1064	if (mask)
991	1065	value &= ~BIT(gpp_offset);
..	..	@@ -1006,11 +1080,11 @@
1006	1080	intel_gpio_irq_mask_unmask(d, false);
1007	1081	}
1008	1082
1009		-static int intel_gpio_irq_type(struct irq_data *d, unsigned type)
	1083	+static int intel_gpio_irq_type(struct irq_data *d, unsigned int type)
1010	1084	{
1011	1085	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1012	1086	struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1013		- unsigned pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
	1087	+ unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
1014	1088	unsigned long flags;
1015	1089	void __iomem *reg;
1016	1090	u32 value;
..	..	@@ -1067,7 +1141,7 @@
1067	1141	{
1068	1142	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1069	1143	struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
1070		- unsigned pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
	1144	+ unsigned int pin = intel_gpio_to_pin(pctrl, irqd_to_hwirq(d), NULL, NULL);
1071	1145
1072	1146	if (on)
1073	1147	enable_irq_wake(pctrl->irq);
..	..	@@ -1078,34 +1152,39 @@
1078	1152	return 0;
1079	1153	}
1080	1154
1081		-static irqreturn_t intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
1082		- const struct intel_community *community)
	1155	+static int intel_gpio_community_irq_handler(struct intel_pinctrl *pctrl,
	1156	+ const struct intel_community *community)
1083	1157	{
1084	1158	struct gpio_chip *gc = &pctrl->chip;
1085		- irqreturn_t ret = IRQ_NONE;
1086		- int gpp;
	1159	+ unsigned int gpp;
	1160	+ int ret = 0;
1087	1161
1088	1162	for (gpp = 0; gpp < community->ngpps; gpp++) {
1089	1163	const struct intel_padgroup *padgrp = &community->gpps[gpp];
1090	1164	unsigned long pending, enabled, gpp_offset;
	1165	+ unsigned long flags;
	1166	+
	1167	+ raw_spin_lock_irqsave(&pctrl->lock, flags);
1091	1168
1092	1169	pending = readl(community->regs + community->is_offset +
1093	1170	padgrp->reg_num * 4);
1094	1171	enabled = readl(community->regs + community->ie_offset +
1095	1172	padgrp->reg_num * 4);
1096	1173
	1174	+ raw_spin_unlock_irqrestore(&pctrl->lock, flags);
	1175	+
1097	1176	/* Only interrupts that are enabled */
1098	1177	pending &= enabled;
1099	1178
1100	1179	for_each_set_bit(gpp_offset, &pending, padgrp->size) {
1101		- unsigned irq;
	1180	+ unsigned int irq;
1102	1181
1103	1182	irq = irq_find_mapping(gc->irq.domain,
1104	1183	padgrp->gpio_base + gpp_offset);
1105	1184	generic_handle_irq(irq);
1106		-
1107		- ret \|= IRQ_HANDLED;
1108	1185	}
	1186	+
	1187	+ ret += pending ? 1 : 0;
1109	1188	}
1110	1189
1111	1190	return ret;
..	..	@@ -1115,38 +1194,60 @@
1115	1194	{
1116	1195	const struct intel_community *community;
1117	1196	struct intel_pinctrl *pctrl = data;
1118		- irqreturn_t ret = IRQ_NONE;
1119		- int i;
	1197	+ unsigned int i;
	1198	+ int ret = 0;
1120	1199
1121	1200	/* Need to check all communities for pending interrupts */
1122	1201	for (i = 0; i < pctrl->ncommunities; i++) {
1123	1202	community = &pctrl->communities[i];
1124		- ret \|= intel_gpio_community_irq_handler(pctrl, community);
	1203	+ ret += intel_gpio_community_irq_handler(pctrl, community);
1125	1204	}
1126	1205
1127		- return ret;
	1206	+ return IRQ_RETVAL(ret);
1128	1207	}
1129	1208
1130		-static struct irq_chip intel_gpio_irqchip = {
1131		- .name = "intel-gpio",
1132		- .irq_enable = intel_gpio_irq_enable,
1133		- .irq_ack = intel_gpio_irq_ack,
1134		- .irq_mask = intel_gpio_irq_mask,
1135		- .irq_unmask = intel_gpio_irq_unmask,
1136		- .irq_set_type = intel_gpio_irq_type,
1137		- .irq_set_wake = intel_gpio_irq_wake,
1138		- .flags = IRQCHIP_MASK_ON_SUSPEND,
1139		-};
	1209	+static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
	1210	+{
	1211	+ int i;
1140	1212
1141		-static int intel_gpio_add_pin_ranges(struct intel_pinctrl *pctrl,
1142		- const struct intel_community *community)
	1213	+ for (i = 0; i < pctrl->ncommunities; i++) {
	1214	+ const struct intel_community *community;
	1215	+ void __iomem *base;
	1216	+ unsigned int gpp;
	1217	+
	1218	+ community = &pctrl->communities[i];
	1219	+ base = community->regs;
	1220	+
	1221	+ for (gpp = 0; gpp < community->ngpps; gpp++) {
	1222	+ /* Mask and clear all interrupts */
	1223	+ writel(0, base + community->ie_offset + gpp * 4);
	1224	+ writel(0xffff, base + community->is_offset + gpp * 4);
	1225	+ }
	1226	+ }
	1227	+}
	1228	+
	1229	+static int intel_gpio_irq_init_hw(struct gpio_chip *gc)
	1230	+{
	1231	+ struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
	1232	+
	1233	+ /*
	1234	+ * Make sure the interrupt lines are in a proper state before
	1235	+ * further configuration.
	1236	+ */
	1237	+ intel_gpio_irq_init(pctrl);
	1238	+
	1239	+ return 0;
	1240	+}
	1241	+
	1242	+static int intel_gpio_add_community_ranges(struct intel_pinctrl *pctrl,
	1243	+ const struct intel_community *community)
1143	1244	{
1144	1245	int ret = 0, i;
1145	1246
1146	1247	for (i = 0; i < community->ngpps; i++) {
1147	1248	const struct intel_padgroup *gpp = &community->gpps[i];
1148	1249
1149		- if (gpp->gpio_base < 0)
	1250	+ if (gpp->gpio_base == INTEL_GPIO_BASE_NOMAP)
1150	1251	continue;
1151	1252
1152	1253	ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev),
..	..	@@ -1159,10 +1260,28 @@
1159	1260	return ret;
1160	1261	}
1161	1262
1162		-static unsigned intel_gpio_ngpio(const struct intel_pinctrl *pctrl)
	1263	+static int intel_gpio_add_pin_ranges(struct gpio_chip *gc)
	1264	+{
	1265	+ struct intel_pinctrl *pctrl = gpiochip_get_data(gc);
	1266	+ int ret, i;
	1267	+
	1268	+ for (i = 0; i < pctrl->ncommunities; i++) {
	1269	+ struct intel_community *community = &pctrl->communities[i];
	1270	+
	1271	+ ret = intel_gpio_add_community_ranges(pctrl, community);
	1272	+ if (ret) {
	1273	+ dev_err(pctrl->dev, "failed to add GPIO pin range\n");
	1274	+ return ret;
	1275	+ }
	1276	+ }
	1277	+
	1278	+ return 0;
	1279	+}
	1280	+
	1281	+static unsigned int intel_gpio_ngpio(const struct intel_pinctrl *pctrl)
1163	1282	{
1164	1283	const struct intel_community *community;
1165		- unsigned ngpio = 0;
	1284	+ unsigned int ngpio = 0;
1166	1285	int i, j;
1167	1286
1168	1287	for (i = 0; i < pctrl->ncommunities; i++) {
..	..	@@ -1170,7 +1289,7 @@
1170	1289	for (j = 0; j < community->ngpps; j++) {
1171	1290	const struct intel_padgroup *gpp = &community->gpps[j];
1172	1291
1173		- if (gpp->gpio_base < 0)
	1292	+ if (gpp->gpio_base == INTEL_GPIO_BASE_NOMAP)
1174	1293	continue;
1175	1294
1176	1295	if (gpp->gpio_base + gpp->size > ngpio)
..	..	@@ -1183,36 +1302,31 @@
1183	1302
1184	1303	static int intel_gpio_probe(struct intel_pinctrl *pctrl, int irq)
1185	1304	{
1186		- int ret, i;
	1305	+ int ret;
	1306	+ struct gpio_irq_chip *girq;
1187	1307
1188	1308	pctrl->chip = intel_gpio_chip;
1189	1309
	1310	+ /* Setup GPIO chip */
1190	1311	pctrl->chip.ngpio = intel_gpio_ngpio(pctrl);
1191	1312	pctrl->chip.label = dev_name(pctrl->dev);
1192	1313	pctrl->chip.parent = pctrl->dev;
1193	1314	pctrl->chip.base = -1;
	1315	+ pctrl->chip.add_pin_ranges = intel_gpio_add_pin_ranges;
1194	1316	pctrl->irq = irq;
1195	1317
1196		- ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl);
1197		- if (ret) {
1198		- dev_err(pctrl->dev, "failed to register gpiochip\n");
1199		- return ret;
1200		- }
1201		-
1202		- for (i = 0; i < pctrl->ncommunities; i++) {
1203		- struct intel_community *community = &pctrl->communities[i];
1204		-
1205		- ret = intel_gpio_add_pin_ranges(pctrl, community);
1206		- if (ret) {
1207		- dev_err(pctrl->dev, "failed to add GPIO pin range\n");
1208		- return ret;
1209		- }
1210		- }
	1318	+ /* Setup IRQ chip */
	1319	+ pctrl->irqchip.name = dev_name(pctrl->dev);
	1320	+ pctrl->irqchip.irq_ack = intel_gpio_irq_ack;
	1321	+ pctrl->irqchip.irq_mask = intel_gpio_irq_mask;
	1322	+ pctrl->irqchip.irq_unmask = intel_gpio_irq_unmask;
	1323	+ pctrl->irqchip.irq_set_type = intel_gpio_irq_type;
	1324	+ pctrl->irqchip.irq_set_wake = intel_gpio_irq_wake;
	1325	+ pctrl->irqchip.flags = IRQCHIP_MASK_ON_SUSPEND;
1211	1326
1212	1327	/*
1213		- * We need to request the interrupt here (instead of providing chip
1214		- * to the irq directly) because on some platforms several GPIO
1215		- * controllers share the same interrupt line.
	1328	+ * On some platforms several GPIO controllers share the same interrupt
	1329	+ * line.
1216	1330	*/
1217	1331	ret = devm_request_irq(pctrl->dev, irq, intel_gpio_irq,
1218	1332	IRQF_SHARED \| IRQF_NO_THREAD,
..	..	@@ -1222,15 +1336,21 @@
1222	1336	return ret;
1223	1337	}
1224	1338
1225		- ret = gpiochip_irqchip_add(&pctrl->chip, &intel_gpio_irqchip, 0,
1226		- handle_bad_irq, IRQ_TYPE_NONE);
	1339	+ girq = &pctrl->chip.irq;
	1340	+ girq->chip = &pctrl->irqchip;
	1341	+ /* This will let us handle the IRQ in the driver */
	1342	+ girq->parent_handler = NULL;
	1343	+ girq->num_parents = 0;
	1344	+ girq->default_type = IRQ_TYPE_NONE;
	1345	+ girq->handler = handle_bad_irq;
	1346	+ girq->init_hw = intel_gpio_irq_init_hw;
	1347	+
	1348	+ ret = devm_gpiochip_add_data(pctrl->dev, &pctrl->chip, pctrl);
1227	1349	if (ret) {
1228		- dev_err(pctrl->dev, "failed to add irqchip\n");
	1350	+ dev_err(pctrl->dev, "failed to register gpiochip\n");
1229	1351	return ret;
1230	1352	}
1231	1353
1232		- gpiochip_set_chained_irqchip(&pctrl->chip, &intel_gpio_irqchip, irq,
1233		- NULL);
1234	1354	return 0;
1235	1355	}
1236	1356
..	..	@@ -1238,8 +1358,8 @@
1238	1358	struct intel_community *community)
1239	1359	{
1240	1360	struct intel_padgroup *gpps;
1241		- unsigned npins = community->npins;
1242		- unsigned padown_num = 0;
	1361	+ unsigned int npins = community->npins;
	1362	+ unsigned int padown_num = 0;
1243	1363	size_t ngpps, i;
1244	1364
1245	1365	if (community->gpps)
..	..	@@ -1255,7 +1375,7 @@
1255	1375	if (community->gpps) {
1256	1376	gpps[i] = community->gpps[i];
1257	1377	} else {
1258		- unsigned gpp_size = community->gpp_size;
	1378	+ unsigned int gpp_size = community->gpp_size;
1259	1379
1260	1380	gpps[i].reg_num = i;
1261	1381	gpps[i].base = community->pin_base + i * gpp_size;
..	..	@@ -1266,8 +1386,18 @@
1266	1386	if (gpps[i].size > 32)
1267	1387	return -EINVAL;
1268	1388
1269		- if (!gpps[i].gpio_base)
1270		- gpps[i].gpio_base = gpps[i].base;
	1389	+ /* Special treatment for GPIO base */
	1390	+ switch (gpps[i].gpio_base) {
	1391	+ case INTEL_GPIO_BASE_MATCH:
	1392	+ gpps[i].gpio_base = gpps[i].base;
	1393	+ break;
	1394	+ case INTEL_GPIO_BASE_ZERO:
	1395	+ gpps[i].gpio_base = 0;
	1396	+ break;
	1397	+ case INTEL_GPIO_BASE_NOMAP:
	1398	+ default:
	1399	+ break;
	1400	+ }
1271	1401
1272	1402	gpps[i].padown_num = padown_num;
1273	1403
..	..	@@ -1307,7 +1437,7 @@
1307	1437
1308	1438	for (i = 0; i < pctrl->ncommunities; i++) {
1309	1439	struct intel_community *community = &pctrl->communities[i];
1310		- u32 *intmask;
	1440	+ u32 intmask, hostown;
1311	1441
1312	1442	intmask = devm_kcalloc(pctrl->dev, community->ngpps,
1313	1443	sizeof(*intmask), GFP_KERNEL);
..	..	@@ -1315,6 +1445,13 @@
1315	1445	return -ENOMEM;
1316	1446
1317	1447	communities[i].intmask = intmask;
	1448	+
	1449	+ hostown = devm_kcalloc(pctrl->dev, community->ngpps,
	1450	+ sizeof(*hostown), GFP_KERNEL);
	1451	+ if (!hostown)
	1452	+ return -ENOMEM;
	1453	+
	1454	+ communities[i].hostown = hostown;
1318	1455	}
1319	1456
1320	1457	pctrl->context.pads = pads;
..	..	@@ -1324,14 +1461,11 @@
1324	1461	return 0;
1325	1462	}
1326	1463
1327		-int intel_pinctrl_probe(struct platform_device *pdev,
1328		- const struct intel_pinctrl_soc_data *soc_data)
	1464	+static int intel_pinctrl_probe(struct platform_device *pdev,
	1465	+ const struct intel_pinctrl_soc_data *soc_data)
1329	1466	{
1330	1467	struct intel_pinctrl *pctrl;
1331	1468	int i, ret, irq;
1332		-
1333		- if (!soc_data)
1334		- return -EINVAL;
1335	1469
1336	1470	pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1337	1471	if (!pctrl)
..	..	@@ -1353,15 +1487,12 @@
1353	1487
1354	1488	for (i = 0; i < pctrl->ncommunities; i++) {
1355	1489	struct intel_community *community = &pctrl->communities[i];
1356		- struct resource *res;
1357	1490	void __iomem *regs;
1358	1491	u32 padbar;
1359	1492
1360	1493	*community = pctrl->soc->communities[i];
1361	1494
1362		- res = platform_get_resource(pdev, IORESOURCE_MEM,
1363		- community->barno);
1364		- regs = devm_ioremap_resource(&pdev->dev, res);
	1495	+ regs = devm_platform_ioremap_resource(pdev, community->barno);
1365	1496	if (IS_ERR(regs))
1366	1497	return PTR_ERR(regs);
1367	1498
..	..	@@ -1385,19 +1516,14 @@
1385	1516	community->regs = regs;
1386	1517	community->pad_regs = regs + padbar;
1387	1518
1388		- if (!community->is_offset)
1389		- community->is_offset = GPI_IS;
1390		-
1391	1519	ret = intel_pinctrl_add_padgroups(pctrl, community);
1392	1520	if (ret)
1393	1521	return ret;
1394	1522	}
1395	1523
1396	1524	irq = platform_get_irq(pdev, 0);
1397		- if (irq < 0) {
1398		- dev_err(&pdev->dev, "failed to get interrupt number\n");
	1525	+ if (irq < 0)
1399	1526	return irq;
1400		- }
1401	1527
1402	1528	ret = intel_pinctrl_pm_init(pctrl);
1403	1529	if (ret)
..	..	@@ -1423,12 +1549,73 @@
1423	1549
1424	1550	return 0;
1425	1551	}
1426		-EXPORT_SYMBOL_GPL(intel_pinctrl_probe);
	1552	+
	1553	+int intel_pinctrl_probe_by_hid(struct platform_device *pdev)
	1554	+{
	1555	+ const struct intel_pinctrl_soc_data *data;
	1556	+
	1557	+ data = device_get_match_data(&pdev->dev);
	1558	+ if (!data)
	1559	+ return -ENODATA;
	1560	+
	1561	+ return intel_pinctrl_probe(pdev, data);
	1562	+}
	1563	+EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_hid);
	1564	+
	1565	+int intel_pinctrl_probe_by_uid(struct platform_device *pdev)
	1566	+{
	1567	+ const struct intel_pinctrl_soc_data *data;
	1568	+
	1569	+ data = intel_pinctrl_get_soc_data(pdev);
	1570	+ if (IS_ERR(data))
	1571	+ return PTR_ERR(data);
	1572	+
	1573	+ return intel_pinctrl_probe(pdev, data);
	1574	+}
	1575	+EXPORT_SYMBOL_GPL(intel_pinctrl_probe_by_uid);
	1576	+
	1577	+const struct intel_pinctrl_soc_data intel_pinctrl_get_soc_data(struct platform_device pdev)
	1578	+{
	1579	+ const struct intel_pinctrl_soc_data * const *table;
	1580	+ const struct intel_pinctrl_soc_data *data = NULL;
	1581	+
	1582	+ table = device_get_match_data(&pdev->dev);
	1583	+ if (table) {
	1584	+ struct acpi_device *adev = ACPI_COMPANION(&pdev->dev);
	1585	+ unsigned int i;
	1586	+
	1587	+ for (i = 0; table[i]; i++) {
	1588	+ if (!strcmp(adev->pnp.unique_id, table[i]->uid)) {
	1589	+ data = table[i];
	1590	+ break;
	1591	+ }
	1592	+ }
	1593	+ } else {
	1594	+ const struct platform_device_id *id;
	1595	+
	1596	+ id = platform_get_device_id(pdev);
	1597	+ if (!id)
	1598	+ return ERR_PTR(-ENODEV);
	1599	+
	1600	+ table = (const struct intel_pinctrl_soc_data * const *)id->driver_data;
	1601	+ data = table[pdev->id];
	1602	+ }
	1603	+
	1604	+ return data ?: ERR_PTR(-ENODATA);
	1605	+}
	1606	+EXPORT_SYMBOL_GPL(intel_pinctrl_get_soc_data);
1427	1607
1428	1608	#ifdef CONFIG_PM_SLEEP
1429		-static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned pin)
	1609	+static bool __intel_gpio_is_direct_irq(u32 value)
	1610	+{
	1611	+ return (value & PADCFG0_GPIROUTIOXAPIC) && (value & PADCFG0_GPIOTXDIS) &&
	1612	+ (__intel_gpio_get_gpio_mode(value) == PADCFG0_PMODE_GPIO);
	1613	+}
	1614	+
	1615	+static bool intel_pinctrl_should_save(struct intel_pinctrl *pctrl, unsigned int pin)
1430	1616	{
1431	1617	const struct pin_desc *pd = pin_desc_get(pctrl->pctldev, pin);
	1618	+ u32 value;
1432	1619
1433	1620	if (!pd \|\| !intel_pad_usable(pctrl, pin))
1434	1621	return false;
..	..	@@ -1440,16 +1627,33 @@
1440	1627	* them alone.
1441	1628	*/
1442	1629	if (pd->mux_owner \|\| pd->gpio_owner \|\|
1443		- gpiochip_line_is_irq(&pctrl->chip, pin))
	1630	+ gpiochip_line_is_irq(&pctrl->chip, intel_pin_to_gpio(pctrl, pin)))
	1631	+ return true;
	1632	+
	1633	+ /*
	1634	+ * The firmware on some systems may configure GPIO pins to be
	1635	+ * an interrupt source in so called "direct IRQ" mode. In such
	1636	+ * cases the GPIO controller driver has no idea if those pins
	1637	+ * are being used or not. At the same time, there is a known bug
	1638	+ * in the firmwares that don't restore the pin settings correctly
	1639	+ * after suspend, i.e. by an unknown reason the Rx value becomes
	1640	+ * inverted.
	1641	+ *
	1642	+ * Hence, let's save and restore the pins that are configured
	1643	+ * as GPIOs in the input mode with GPIROUTIOXAPIC bit set.
	1644	+ *
	1645	+ * See https://bugzilla.kernel.org/show_bug.cgi?id=214749.
	1646	+ */
	1647	+ value = readl(intel_get_padcfg(pctrl, pin, PADCFG0));
	1648	+ if (__intel_gpio_is_direct_irq(value))
1444	1649	return true;
1445	1650
1446	1651	return false;
1447	1652	}
1448	1653
1449		-int intel_pinctrl_suspend(struct device *dev)
	1654	+int intel_pinctrl_suspend_noirq(struct device *dev)
1450	1655	{
1451		- struct platform_device *pdev = to_platform_device(dev);
1452		- struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
	1656	+ struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
1453	1657	struct intel_community_context *communities;
1454	1658	struct intel_pad_context *pads;
1455	1659	int i;
..	..	@@ -1477,41 +1681,89 @@
1477	1681	for (i = 0; i < pctrl->ncommunities; i++) {
1478	1682	struct intel_community *community = &pctrl->communities[i];
1479	1683	void __iomem *base;
1480		- unsigned gpp;
	1684	+ unsigned int gpp;
1481	1685
1482	1686	base = community->regs + community->ie_offset;
1483	1687	for (gpp = 0; gpp < community->ngpps; gpp++)
1484	1688	communities[i].intmask[gpp] = readl(base + gpp * 4);
	1689	+
	1690	+ base = community->regs + community->hostown_offset;
	1691	+ for (gpp = 0; gpp < community->ngpps; gpp++)
	1692	+ communities[i].hostown[gpp] = readl(base + gpp * 4);
1485	1693	}
1486	1694
1487	1695	return 0;
1488	1696	}
1489		-EXPORT_SYMBOL_GPL(intel_pinctrl_suspend);
	1697	+EXPORT_SYMBOL_GPL(intel_pinctrl_suspend_noirq);
1490	1698
1491		-static void intel_gpio_irq_init(struct intel_pinctrl *pctrl)
	1699	+static bool intel_gpio_update_reg(void __iomem *reg, u32 mask, u32 value)
1492	1700	{
1493		- size_t i;
	1701	+ u32 curr, updated;
1494	1702
1495		- for (i = 0; i < pctrl->ncommunities; i++) {
1496		- const struct intel_community *community;
1497		- void __iomem *base;
1498		- unsigned gpp;
	1703	+ curr = readl(reg);
1499	1704
1500		- community = &pctrl->communities[i];
1501		- base = community->regs;
	1705	+ updated = (curr & ~mask) \| (value & mask);
	1706	+ if (curr == updated)
	1707	+ return false;
1502	1708
1503		- for (gpp = 0; gpp < community->ngpps; gpp++) {
1504		- /* Mask and clear all interrupts */
1505		- writel(0, base + community->ie_offset + gpp * 4);
1506		- writel(0xffff, base + community->is_offset + gpp * 4);
1507		- }
1508		- }
	1709	+ writel(updated, reg);
	1710	+ return true;
1509	1711	}
1510	1712
1511		-int intel_pinctrl_resume(struct device *dev)
	1713	+static void intel_restore_hostown(struct intel_pinctrl *pctrl, unsigned int c,
	1714	+ void __iomem *base, unsigned int gpp, u32 saved)
1512	1715	{
1513		- struct platform_device *pdev = to_platform_device(dev);
1514		- struct intel_pinctrl *pctrl = platform_get_drvdata(pdev);
	1716	+ const struct intel_community *community = &pctrl->communities[c];
	1717	+ const struct intel_padgroup *padgrp = &community->gpps[gpp];
	1718	+ struct device *dev = pctrl->dev;
	1719	+ const char *dummy;
	1720	+ u32 requested = 0;
	1721	+ unsigned int i;
	1722	+
	1723	+ if (padgrp->gpio_base == INTEL_GPIO_BASE_NOMAP)
	1724	+ return;
	1725	+
	1726	+ for_each_requested_gpio_in_range(&pctrl->chip, i, padgrp->gpio_base, padgrp->size, dummy)
	1727	+ requested \|= BIT(i);
	1728	+
	1729	+ if (!intel_gpio_update_reg(base + gpp * 4, requested, saved))
	1730	+ return;
	1731	+
	1732	+ dev_dbg(dev, "restored hostown %u/%u %#08x\n", c, gpp, readl(base + gpp * 4));
	1733	+}
	1734	+
	1735	+static void intel_restore_intmask(struct intel_pinctrl *pctrl, unsigned int c,
	1736	+ void __iomem *base, unsigned int gpp, u32 saved)
	1737	+{
	1738	+ struct device *dev = pctrl->dev;
	1739	+
	1740	+ if (!intel_gpio_update_reg(base + gpp * 4, ~0U, saved))
	1741	+ return;
	1742	+
	1743	+ dev_dbg(dev, "restored mask %u/%u %#08x\n", c, gpp, readl(base + gpp * 4));
	1744	+}
	1745	+
	1746	+static void intel_restore_padcfg(struct intel_pinctrl *pctrl, unsigned int pin,
	1747	+ unsigned int reg, u32 saved)
	1748	+{
	1749	+ u32 mask = (reg == PADCFG0) ? PADCFG0_GPIORXSTATE : 0;
	1750	+ unsigned int n = reg / sizeof(u32);
	1751	+ struct device *dev = pctrl->dev;
	1752	+ void __iomem *padcfg;
	1753	+
	1754	+ padcfg = intel_get_padcfg(pctrl, pin, reg);
	1755	+ if (!padcfg)
	1756	+ return;
	1757	+
	1758	+ if (!intel_gpio_update_reg(padcfg, ~mask, saved))
	1759	+ return;
	1760	+
	1761	+ dev_dbg(dev, "restored pin %u padcfg%u %#08x\n", pin, n, readl(padcfg));
	1762	+}
	1763	+
	1764	+int intel_pinctrl_resume_noirq(struct device *dev)
	1765	+{
	1766	+ struct intel_pinctrl *pctrl = dev_get_drvdata(dev);
1515	1767	const struct intel_community_context *communities;
1516	1768	const struct intel_pad_context *pads;
1517	1769	int i;
..	..	@@ -1522,56 +1774,38 @@
1522	1774	pads = pctrl->context.pads;
1523	1775	for (i = 0; i < pctrl->soc->npins; i++) {
1524	1776	const struct pinctrl_pin_desc *desc = &pctrl->soc->pins[i];
1525		- void __iomem *padcfg;
1526		- u32 val;
1527	1777
1528		- if (!intel_pinctrl_should_save(pctrl, desc->number))
	1778	+ if (!(intel_pinctrl_should_save(pctrl, desc->number) \|\|
	1779	+ /*
	1780	+ * If the firmware mangled the register contents too much,
	1781	+ * check the saved value for the Direct IRQ mode.
	1782	+ */
	1783	+ __intel_gpio_is_direct_irq(pads[i].padcfg0)))
1529	1784	continue;
1530	1785
1531		- padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG0);
1532		- val = readl(padcfg) & ~PADCFG0_GPIORXSTATE;
1533		- if (val != pads[i].padcfg0) {
1534		- writel(pads[i].padcfg0, padcfg);
1535		- dev_dbg(dev, "restored pin %u padcfg0 %#08x\n",
1536		- desc->number, readl(padcfg));
1537		- }
1538		-
1539		- padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG1);
1540		- val = readl(padcfg);
1541		- if (val != pads[i].padcfg1) {
1542		- writel(pads[i].padcfg1, padcfg);
1543		- dev_dbg(dev, "restored pin %u padcfg1 %#08x\n",
1544		- desc->number, readl(padcfg));
1545		- }
1546		-
1547		- padcfg = intel_get_padcfg(pctrl, desc->number, PADCFG2);
1548		- if (padcfg) {
1549		- val = readl(padcfg);
1550		- if (val != pads[i].padcfg2) {
1551		- writel(pads[i].padcfg2, padcfg);
1552		- dev_dbg(dev, "restored pin %u padcfg2 %#08x\n",
1553		- desc->number, readl(padcfg));
1554		- }
1555		- }
	1786	+ intel_restore_padcfg(pctrl, desc->number, PADCFG0, pads[i].padcfg0);
	1787	+ intel_restore_padcfg(pctrl, desc->number, PADCFG1, pads[i].padcfg1);
	1788	+ intel_restore_padcfg(pctrl, desc->number, PADCFG2, pads[i].padcfg2);
1556	1789	}
1557	1790
1558	1791	communities = pctrl->context.communities;
1559	1792	for (i = 0; i < pctrl->ncommunities; i++) {
1560	1793	struct intel_community *community = &pctrl->communities[i];
1561	1794	void __iomem *base;
1562		- unsigned gpp;
	1795	+ unsigned int gpp;
1563	1796
1564	1797	base = community->regs + community->ie_offset;
1565		- for (gpp = 0; gpp < community->ngpps; gpp++) {
1566		- writel(communities[i].intmask[gpp], base + gpp * 4);
1567		- dev_dbg(dev, "restored mask %d/%u %#08x\n", i, gpp,
1568		- readl(base + gpp * 4));
1569		- }
	1798	+ for (gpp = 0; gpp < community->ngpps; gpp++)
	1799	+ intel_restore_intmask(pctrl, i, base, gpp, communities[i].intmask[gpp]);
	1800	+
	1801	+ base = community->regs + community->hostown_offset;
	1802	+ for (gpp = 0; gpp < community->ngpps; gpp++)
	1803	+ intel_restore_hostown(pctrl, i, base, gpp, communities[i].hostown[gpp]);
1570	1804	}
1571	1805
1572	1806	return 0;
1573	1807	}
1574		-EXPORT_SYMBOL_GPL(intel_pinctrl_resume);
	1808	+EXPORT_SYMBOL_GPL(intel_pinctrl_resume_noirq);
1575	1809	#endif
1576	1810
1577	1811	MODULE_AUTHOR("Mathias Nyman <mathias.nyman@linux.intel.com>");