update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
..
..
@@ -59,10 +59,12 @@
59
59
 	struct combphy_reg con2_for_sata;
60
60
 	struct combphy_reg con3_for_sata;
61
61
 	struct combphy_reg pipe_con0_for_sata;
62
+	struct combphy_reg pipe_con1_for_sata;
62
63
 	struct combphy_reg pipe_sgmii_mac_sel;
63
64
 	struct combphy_reg pipe_xpcs_phy_ready;
64
65
 	struct combphy_reg u3otg0_port_en;
65
66
 	struct combphy_reg u3otg1_port_en;
67
+	struct combphy_reg pipe_phy_grf_reset;
66
68
 };
67
69
 
68
70
 struct rockchip_combphy_cfg {
..
..
@@ -251,6 +253,9 @@
251
253
 	if (ret)
252
254
 		goto err_clk;
253
255
 
256
+	if (cfg->pipe_phy_grf_reset.enable)
257
+		param_write(priv->phy_grf, &cfg->pipe_phy_grf_reset, false);
258
+
254
259
 	if (priv->mode == PHY_TYPE_USB3) {
255
260
 		ret = readx_poll_timeout_atomic(rockchip_combphy_is_ready,
256
261
 						priv, val,
..
..
@@ -271,6 +276,10 @@
271
276
 static int rockchip_combphy_exit(struct phy *phy)
272
277
 {
273
278
 	struct rockchip_combphy_priv *priv = phy_get_drvdata(phy);
279
+	const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
280
+
281
+	if (cfg->pipe_phy_grf_reset.enable)
282
+		param_write(priv->phy_grf, &cfg->pipe_phy_grf_reset, true);
274
283
 
275
284
 	clk_bulk_disable_unprepare(priv->num_clks, priv->clks);
276
285
 	reset_control_assert(priv->phy_rst);
..
..
@@ -278,9 +287,42 @@
278
287
 	return 0;
279
288
 }
280
289
 
290
+static const char *rockchip_combphy_mode2str(enum phy_mode mode)
291
+{
292
+	switch (mode) {
293
+	case PHY_TYPE_SATA:
294
+		return "SATA";
295
+	case PHY_TYPE_PCIE:
296
+		return "PCIe";
297
+	case PHY_TYPE_USB3:
298
+		return "USB3";
299
+	case PHY_TYPE_SGMII:
300
+	case PHY_TYPE_QSGMII:
301
+		return "GMII";
302
+	default:
303
+		return "Unknown";
304
+	}
305
+}
306
+
307
+static int rockchip_combphy_validate(struct phy *phy, enum phy_mode mode, int submode,
308
+			      union phy_configure_opts *opts)
309
+{
310
+	struct rockchip_combphy_priv *priv = phy_get_drvdata(phy);
311
+
312
+	if (mode != priv->mode) {
313
+		dev_err(priv->dev, "expected mode is %s, but current mode is %s\n",
314
+			rockchip_combphy_mode2str(mode),
315
+			rockchip_combphy_mode2str(priv->mode));
316
+		return -EINVAL;
317
+	}
318
+
319
+	return 0;
320
+}
321
+
281
322
 static const struct phy_ops rochchip_combphy_ops = {
282
323
 	.init = rockchip_combphy_init,
283
324
 	.exit = rockchip_combphy_exit,
325
+	.validate = rockchip_combphy_validate,
284
326
 	.owner = THIS_MODULE,
285
327
 };
286
328
 
..
..
@@ -308,6 +350,7 @@
308
350
 {
309
351
 	const struct rockchip_combphy_cfg *phy_cfg = priv->cfg;
310
352
 	int ret, mac_id;
353
+	u32 vals[4];
311
354
 
312
355
 	ret = devm_clk_bulk_get(dev, priv->num_clks, priv->clks);
313
356
 	if (ret == -EPROBE_DEFER)
..
..
@@ -340,6 +383,11 @@
340
383
 	    (mac_id > 0))
341
384
 		param_write(priv->pipe_grf, &phy_cfg->grfcfg->pipe_sgmii_mac_sel,
342
385
 			    true);
386
+
387
+	if (!device_property_read_u32_array(dev, "rockchip,pcie1ln-sel-bits",
388
+					    vals, ARRAY_SIZE(vals)))
389
+		regmap_write(priv->pipe_grf, vals[0],
390
+			     (GENMASK(vals[2], vals[1]) << 16) | (vals[3] << vals[1]));
343
391
 
344
392
 	priv->apb_rst = devm_reset_control_get_optional(dev, "combphy-apb");
345
393
 	if (IS_ERR(priv->apb_rst)) {
..
..
@@ -468,6 +516,18 @@
468
516
 		val |= 0x01 << 17;
469
517
 		writel(val, priv->mmio + 0x200);
470
518
 
519
+		/* Set slow slew rate control for PI */
520
+		val = readl(priv->mmio + 0x204);
521
+		val &= ~GENMASK(2, 0);
522
+		val |= 0x07;
523
+		writel(val, priv->mmio + 0x204);
524
+
525
+		/* Set CDR phase path with 2x gain */
526
+		val = readl(priv->mmio + 0x204);
527
+		val &= ~GENMASK(5, 5);
528
+		val |= 0x01 << 5;
529
+		writel(val, priv->mmio + 0x204);
530
+
471
531
 		/* Set Rx squelch input filler bandwidth */
472
532
 		val = readl(priv->mmio + 0x20c);
473
533
 		val &= ~GENMASK(2, 0);
..
..
@@ -495,39 +555,15 @@
495
555
 			val |= 0x17d;
496
556
 			writel(val, priv->mmio + 0x100);
497
557
 		} else if (priv->mode == PHY_TYPE_PCIE) {
498
-			/* Set ssc_cnt[10:0]=00101111101 & 31.5KHz */
499
-			val = readl(priv->mmio + 0x100);
500
-			val &= ~GENMASK(10, 0);
501
-			val |= 0x17d;
502
-			writel(val, priv->mmio + 0x100);
503
-
504
558
 			/* tx_trim[14]=1, Enable the counting clock of the rterm detect */
505
559
 			val = readl(priv->mmio + 0x218);
506
560
 			val |= (1 << 14);
507
561
 			writel(val, priv->mmio + 0x218);
508
-
509
-			/* PLL KVCO tuning fine */
510
-			val = readl(priv->mmio + 0x18);
511
-			val &= ~(0x7 << 10);
512
-			val |= 0x2 << 10;
513
-			writel(val, priv->mmio + 0x18);
514
-
515
-			/* su_trim[6:4]=111, [10:7]=1001, [2:0]=000 */
516
-			val = readl(priv->mmio + 0x108);
517
-			val &= ~(0x7f7);
518
-			val |= 0x4f0;
519
-			writel(val, priv->mmio + 0x108);
520
562
 		}
521
563
 		break;
522
564
 	case 100000000:
523
565
 		param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
524
566
 		if (priv->mode == PHY_TYPE_PCIE) {
525
-			/* Set ssc_cnt[10:0]=11000110011 & 31.5KHz */
526
-			val = readl(priv->mmio + 0x100);
527
-			val &= ~GENMASK(10, 0);
528
-			val |= 0x633;
529
-			writel(val, priv->mmio + 0x100);
530
-
531
567
 			/* PLL KVCO tuning fine */
532
568
 			val = readl(priv->mmio + 0x18);
533
569
 			val &= ~(0x7 << 10);
..
..
@@ -542,14 +578,6 @@
542
578
 	default:
543
579
 		dev_err(priv->dev, "Unsupported rate: %lu\n", rate);
544
580
 		return -EINVAL;
545
-	}
546
-
547
-	if (priv->mode == PHY_TYPE_PCIE) {
548
-		if (device_property_read_bool(priv->dev, "rockchip,enable-ssc")) {
549
-			val = readl(priv->mmio + 0x100);
550
-			val |= BIT(20);
551
-			writel(val, priv->mmio + 0x100);
552
-		}
553
581
 	}
554
582
 
555
583
 	return 0;
..
..
@@ -588,6 +616,201 @@
588
616
 	.clks		= rk3528_clks,
589
617
 	.grfcfg		= &rk3528_combphy_grfcfgs,
590
618
 	.combphy_cfg	= rk3528_combphy_cfg,
619
+};
620
+
621
+static int rk3562_combphy_cfg(struct rockchip_combphy_priv *priv)
622
+{
623
+	const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
624
+	struct clk *refclk = NULL;
625
+	unsigned long rate;
626
+	int i;
627
+	u32 val;
628
+
629
+	/* Configure PHY reference clock frequency */
630
+	for (i = 0; i < priv->num_clks; i++) {
631
+		if (!strncmp(priv->clks[i].id, "refclk", 6)) {
632
+			refclk = priv->clks[i].clk;
633
+			break;
634
+		}
635
+	}
636
+
637
+	if (!refclk) {
638
+		dev_err(priv->dev, "No refclk found\n");
639
+		return -EINVAL;
640
+	}
641
+
642
+	switch (priv->mode) {
643
+	case PHY_TYPE_PCIE:
644
+		/* Set SSC downward spread spectrum */
645
+		val = readl(priv->mmio + (0x1f << 2));
646
+		val &= ~GENMASK(5, 4);
647
+		val |= 0x01 << 4;
648
+		writel(val, priv->mmio + 0x7c);
649
+
650
+		param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
651
+		param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
652
+		param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
653
+		param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
654
+		break;
655
+	case PHY_TYPE_USB3:
656
+		/* Set SSC downward spread spectrum */
657
+		val = readl(priv->mmio + (0x1f << 2));
658
+		val &= ~GENMASK(5, 4);
659
+		val |= 0x01 << 4;
660
+		writel(val, priv->mmio + 0x7c);
661
+
662
+		/* Enable adaptive CTLE for USB3.0 Rx */
663
+		val = readl(priv->mmio + (0x0e << 2));
664
+		val &= ~GENMASK(0, 0);
665
+		val |= 0x01;
666
+		writel(val, priv->mmio + (0x0e << 2));
667
+
668
+		/* Set PLL KVCO fine tuning signals */
669
+		val = readl(priv->mmio + (0x20 << 2));
670
+		val &= ~(0x7 << 2);
671
+		val |= 0x2 << 2;
672
+		writel(val, priv->mmio + (0x20 << 2));
673
+
674
+		/* Set PLL LPF R1 to su_trim[10:7]=1001 */
675
+		writel(0x4, priv->mmio + (0xb << 2));
676
+
677
+		/* Set PLL input clock divider 1/2 */
678
+		val = readl(priv->mmio + (0x5 << 2));
679
+		val &= ~(0x3 << 6);
680
+		val |= 0x1 << 6;
681
+		writel(val, priv->mmio + (0x5 << 2));
682
+
683
+		/* Set PLL loop divider */
684
+		writel(0x32, priv->mmio + (0x11 << 2));
685
+
686
+		/* Set PLL KVCO to min and set PLL charge pump current to max */
687
+		writel(0xf0, priv->mmio + (0xa << 2));
688
+
689
+		/* Set Rx squelch input filler bandwidth */
690
+		writel(0x0e, priv->mmio + (0x14 << 2));
691
+
692
+		param_write(priv->phy_grf, &cfg->pipe_sel_usb, true);
693
+		param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
694
+		param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
695
+		param_write(priv->phy_grf, &cfg->usb_mode_set, true);
696
+		break;
697
+	default:
698
+		dev_err(priv->dev, "incompatible PHY type\n");
699
+		return -EINVAL;
700
+	}
701
+
702
+	rate = clk_get_rate(refclk);
703
+
704
+	switch (rate) {
705
+	case 24000000:
706
+		if (priv->mode == PHY_TYPE_USB3) {
707
+			/* Set ssc_cnt[9:0]=0101111101 & 31.5KHz */
708
+			val = readl(priv->mmio + (0x0e << 2));
709
+			val &= ~GENMASK(7, 6);
710
+			val |= 0x01 << 6;
711
+			writel(val, priv->mmio + (0x0e << 2));
712
+
713
+			val = readl(priv->mmio + (0x0f << 2));
714
+			val &= ~GENMASK(7, 0);
715
+			val |= 0x5f;
716
+			writel(val, priv->mmio + (0x0f << 2));
717
+		}
718
+		break;
719
+	case 25000000:
720
+		param_write(priv->phy_grf, &cfg->pipe_clk_25m, true);
721
+		break;
722
+	case 100000000:
723
+		param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
724
+		if (priv->mode == PHY_TYPE_PCIE) {
725
+			/* PLL KVCO tuning fine */
726
+			val = readl(priv->mmio + (0x20 << 2));
727
+			val &= ~(0x7 << 2);
728
+			val |= 0x2 << 2;
729
+			writel(val, priv->mmio + (0x20 << 2));
730
+
731
+			/* Enable controlling random jitter, aka RMJ */
732
+			writel(0x4, priv->mmio + (0xb << 2));
733
+
734
+			val = readl(priv->mmio + (0x5 << 2));
735
+			val &= ~(0x3 << 6);
736
+			val |= 0x1 << 6;
737
+			writel(val, priv->mmio + (0x5 << 2));
738
+
739
+			writel(0x32, priv->mmio + (0x11 << 2));
740
+			writel(0xf0, priv->mmio + (0xa << 2));
741
+
742
+			/* CKDRV output swing adjust to 650mv */
743
+			val = readl(priv->mmio + (0xd << 2));
744
+			val &= ~(0xf << 1);
745
+			val |= (0xb << 1);
746
+			writel(val, priv->mmio + (0xd << 2));
747
+		}
748
+		break;
749
+	default:
750
+		dev_err(priv->dev, "Unsupported rate: %lu\n", rate);
751
+		return -EINVAL;
752
+	}
753
+
754
+	if (device_property_read_bool(priv->dev, "rockchip,ext-refclk")) {
755
+		param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
756
+		if (priv->mode == PHY_TYPE_PCIE && rate == 100000000) {
757
+			val = readl(priv->mmio + (0xc << 2));
758
+			val |= 0x3 << 4 | 0x1 << 7;
759
+			writel(val, priv->mmio + (0xc << 2));
760
+
761
+			val = readl(priv->mmio + (0xd << 2));
762
+			val |= 0x1;
763
+			writel(val, priv->mmio + (0xd << 2));
764
+		}
765
+	}
766
+
767
+	if (device_property_read_bool(priv->dev, "rockchip,enable-ssc")) {
768
+		val = readl(priv->mmio + (0x7 << 2));
769
+		val |= BIT(4);
770
+		writel(val, priv->mmio + (0x7 << 2));
771
+	}
772
+
773
+	return 0;
774
+}
775
+
776
+static const struct rockchip_combphy_grfcfg rk3562_combphy_grfcfgs = {
777
+	/* pipe-phy-grf */
778
+	.pcie_mode_set		= { 0x0000, 5, 0, 0x00, 0x11 },
779
+	.usb_mode_set		= { 0x0000, 5, 0, 0x00, 0x04 },
780
+	.pipe_rxterm_set	= { 0x0000, 12, 12, 0x00, 0x01 },
781
+	.pipe_txelec_set	= { 0x0004, 1, 1, 0x00, 0x01 },
782
+	.pipe_txcomp_set	= { 0x0004, 4, 4, 0x00, 0x01 },
783
+	.pipe_clk_25m		= { 0x0004, 14, 13, 0x00, 0x01 },
784
+	.pipe_clk_100m		= { 0x0004, 14, 13, 0x00, 0x02 },
785
+	.pipe_phymode_sel	= { 0x0008, 1, 1, 0x00, 0x01 },
786
+	.pipe_rate_sel		= { 0x0008, 2, 2, 0x00, 0x01 },
787
+	.pipe_rxterm_sel	= { 0x0008, 8, 8, 0x00, 0x01 },
788
+	.pipe_txelec_sel	= { 0x0008, 12, 12, 0x00, 0x01 },
789
+	.pipe_txcomp_sel	= { 0x0008, 15, 15, 0x00, 0x01 },
790
+	.pipe_clk_ext		= { 0x000c, 9, 8, 0x02, 0x01 },
791
+	.pipe_sel_usb		= { 0x000c, 14, 13, 0x00, 0x01 },
792
+	.pipe_phy_status	= { 0x0034, 6, 6, 0x01, 0x00 },
793
+	.con0_for_pcie		= { 0x0000, 15, 0, 0x00, 0x1000 },
794
+	.con1_for_pcie		= { 0x0004, 15, 0, 0x00, 0x0000 },
795
+	.con2_for_pcie		= { 0x0008, 15, 0, 0x00, 0x0101 },
796
+	.con3_for_pcie		= { 0x000c, 15, 0, 0x00, 0x0200 },
797
+	.pipe_phy_grf_reset	= { 0x0014, 1, 0, 0x3, 0x1 },
798
+	/* peri-grf */
799
+	.u3otg0_port_en		= { 0x0094, 15, 0, 0x0181, 0x1100 },
800
+};
801
+
802
+static const struct clk_bulk_data rk3562_clks[] = {
803
+	{ .id = "refclk" },
804
+	{ .id = "apbclk" },
805
+	{ .id = "pipe_clk" },
806
+};
807
+
808
+static const struct rockchip_combphy_cfg rk3562_combphy_cfgs = {
809
+	.num_clks	= ARRAY_SIZE(rk3562_clks),
810
+	.clks		= rk3562_clks,
811
+	.grfcfg		= &rk3562_combphy_grfcfgs,
812
+	.combphy_cfg	= rk3562_combphy_cfg,
813
+	.force_det_out	= true,
591
814
 };
592
815
 
593
816
 static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv)
..
..
@@ -817,15 +1040,294 @@
817
1040
 	.force_det_out	= true,
818
1041
 };
819
1042
 
1043
+static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv)
1044
+{
1045
+	const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
1046
+	struct clk *refclk = NULL;
1047
+	unsigned long rate;
1048
+	int i;
1049
+	u32 val;
1050
+
1051
+	/* Configure PHY reference clock frequency */
1052
+	for (i = 0; i < priv->num_clks; i++) {
1053
+		if (!strncmp(priv->clks[i].id, "refclk", 6)) {
1054
+			refclk = priv->clks[i].clk;
1055
+			break;
1056
+		}
1057
+	}
1058
+
1059
+	if (!refclk) {
1060
+		dev_err(priv->dev, "No refclk found\n");
1061
+		return -EINVAL;
1062
+	}
1063
+
1064
+	switch (priv->mode) {
1065
+	case PHY_TYPE_PCIE:
1066
+		/* Set SSC downward spread spectrum */
1067
+		val = readl(priv->mmio + (0x1f << 2));
1068
+		val &= ~GENMASK(5, 4);
1069
+		val |= 0x01 << 4;
1070
+		writel(val, priv->mmio + 0x7c);
1071
+
1072
+		param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
1073
+		param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
1074
+		param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
1075
+		param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
1076
+		break;
1077
+	case PHY_TYPE_USB3:
1078
+		/* Set SSC downward spread spectrum */
1079
+		val = readl(priv->mmio + (0x1f << 2));
1080
+		val &= ~GENMASK(5, 4);
1081
+		val |= 0x01 << 4;
1082
+		writel(val, priv->mmio + 0x7c);
1083
+
1084
+		/* Enable adaptive CTLE for USB3.0 Rx */
1085
+		val = readl(priv->mmio + (0x0e << 2));
1086
+		val &= ~GENMASK(0, 0);
1087
+		val |= 0x01;
1088
+		writel(val, priv->mmio + (0x0e << 2));
1089
+
1090
+		/* Set PLL KVCO fine tuning signals */
1091
+		val = readl(priv->mmio + (0x20 << 2));
1092
+		val &= ~(0x7 << 2);
1093
+		val |= 0x2 << 2;
1094
+		writel(val, priv->mmio + (0x20 << 2));
1095
+
1096
+		/* Set PLL LPF R1 to su_trim[10:7]=1001 */
1097
+		writel(0x4, priv->mmio + (0xb << 2));
1098
+
1099
+		/* Set PLL input clock divider 1/2 */
1100
+		val = readl(priv->mmio + (0x5 << 2));
1101
+		val &= ~(0x3 << 6);
1102
+		val |= 0x1 << 6;
1103
+		writel(val, priv->mmio + (0x5 << 2));
1104
+
1105
+		/* Set PLL loop divider */
1106
+		writel(0x32, priv->mmio + (0x11 << 2));
1107
+
1108
+		/* Set PLL KVCO to min and set PLL charge pump current to max */
1109
+		writel(0xf0, priv->mmio + (0xa << 2));
1110
+
1111
+		/* Set Rx squelch input filler bandwidth */
1112
+		writel(0x0d, priv->mmio + (0x14 << 2));
1113
+
1114
+		param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
1115
+		param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
1116
+		param_write(priv->phy_grf, &cfg->usb_mode_set, true);
1117
+		break;
1118
+	case PHY_TYPE_SATA:
1119
+		/* Enable adaptive CTLE for SATA Rx */
1120
+		val = readl(priv->mmio + (0x0e << 2));
1121
+		val &= ~GENMASK(0, 0);
1122
+		val |= 0x01;
1123
+		writel(val, priv->mmio + (0x0e << 2));
1124
+		/* Set tx_rterm = 50 ohm and rx_rterm = 43.5 ohm */
1125
+		writel(0x8F, priv->mmio + (0x06 << 2));
1126
+
1127
+		param_write(priv->phy_grf, &cfg->con0_for_sata, true);
1128
+		param_write(priv->phy_grf, &cfg->con1_for_sata, true);
1129
+		param_write(priv->phy_grf, &cfg->con2_for_sata, true);
1130
+		param_write(priv->phy_grf, &cfg->con3_for_sata, true);
1131
+		param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true);
1132
+		param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true);
1133
+		break;
1134
+	case PHY_TYPE_SGMII:
1135
+	case PHY_TYPE_QSGMII:
1136
+	default:
1137
+		dev_err(priv->dev, "incompatible PHY type\n");
1138
+		return -EINVAL;
1139
+	}
1140
+
1141
+	rate = clk_get_rate(refclk);
1142
+
1143
+	switch (rate) {
1144
+	case 24000000:
1145
+		param_write(priv->phy_grf, &cfg->pipe_clk_24m, true);
1146
+		if (priv->mode == PHY_TYPE_USB3 || priv->mode == PHY_TYPE_SATA) {
1147
+			/* Set ssc_cnt[9:0]=0101111101 & 31.5KHz */
1148
+			val = readl(priv->mmio + (0x0e << 2));
1149
+			val &= ~GENMASK(7, 6);
1150
+			val |= 0x01 << 6;
1151
+			writel(val, priv->mmio + (0x0e << 2));
1152
+
1153
+			val = readl(priv->mmio + (0x0f << 2));
1154
+			val &= ~GENMASK(7, 0);
1155
+			val |= 0x5f;
1156
+			writel(val, priv->mmio + (0x0f << 2));
1157
+		} else if (priv->mode == PHY_TYPE_PCIE) {
1158
+			/* PLL KVCO tuning fine */
1159
+			val = readl(priv->mmio + (0x20 << 2));
1160
+			val &= ~GENMASK(4, 2);
1161
+			val |= 0x4 << 2;
1162
+			writel(val, priv->mmio + (0x20 << 2));
1163
+
1164
+			/* Set up rx_trim */
1165
+			val = 0x0;
1166
+			writel(val, priv->mmio + (0x1b << 2));
1167
+
1168
+			/* Set up su_trim: T0_1 */
1169
+			val = 0x90;
1170
+			writel(val, priv->mmio + (0xa << 2));
1171
+			val = 0x02;
1172
+			writel(val, priv->mmio + (0xb << 2));
1173
+			val = 0x57;
1174
+			writel(val, priv->mmio + (0xd << 2));
1175
+
1176
+			val = 0x5f;
1177
+			writel(val, priv->mmio + (0xf << 2));
1178
+		}
1179
+		break;
1180
+	case 25000000:
1181
+		param_write(priv->phy_grf, &cfg->pipe_clk_25m, true);
1182
+		break;
1183
+	case 100000000:
1184
+		param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
1185
+		if (priv->mode == PHY_TYPE_PCIE) {
1186
+			/* gate_tx_pck_sel length select work for L1SS */
1187
+			val = 0xc0;
1188
+			writel(val, priv->mmio + 0x74);
1189
+
1190
+			/* PLL KVCO tuning fine */
1191
+			val = readl(priv->mmio + (0x20 << 2));
1192
+			val &= ~GENMASK(4, 2);
1193
+			val |= 0x4 << 2;
1194
+			writel(val, priv->mmio + (0x20 << 2));
1195
+
1196
+			/* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */
1197
+			val = 0x4c;
1198
+			writel(val, priv->mmio + (0x1b << 2));
1199
+
1200
+			/* Set up su_trim: T3_P1 650mv */
1201
+			val = 0x90;
1202
+			writel(val, priv->mmio + (0xa << 2));
1203
+			val = 0x43;
1204
+			writel(val, priv->mmio + (0xb << 2));
1205
+			val = 0x88;
1206
+			writel(val, priv->mmio + (0xc << 2));
1207
+			val = 0x56;
1208
+			writel(val, priv->mmio + (0xd << 2));
1209
+		} else if (priv->mode == PHY_TYPE_SATA) {
1210
+			/* downward spread spectrum +500ppm */
1211
+			val = readl(priv->mmio + (0x1f << 2));
1212
+			val &= ~GENMASK(7, 4);
1213
+			val |= 0x50;
1214
+			writel(val, priv->mmio + (0x1f << 2));
1215
+
1216
+			/* ssc ppm adjust to 3500ppm */
1217
+			val = readl(priv->mmio + (0x9 << 2));
1218
+			val &= ~GENMASK(3, 0);
1219
+			val |= 0x7;
1220
+			writel(val, priv->mmio + (0x9 << 2));
1221
+		}
1222
+		break;
1223
+	default:
1224
+		dev_err(priv->dev, "Unsupported rate: %lu\n", rate);
1225
+		return -EINVAL;
1226
+	}
1227
+
1228
+	if (device_property_read_bool(priv->dev, "rockchip,ext-refclk")) {
1229
+		param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
1230
+		if (priv->mode == PHY_TYPE_PCIE && rate == 100000000) {
1231
+			val = 0x10;
1232
+			writel(val, priv->mmio + (0x20 << 2));
1233
+
1234
+			val = 0x0c;
1235
+			writel(val, priv->mmio + (0x1b << 2));
1236
+
1237
+			/* Set up su_trim: T3_P1 650mv */
1238
+			val = 0x90;
1239
+			writel(val, priv->mmio + (0xa << 2));
1240
+			val = 0x43;
1241
+			writel(val, priv->mmio + (0xb << 2));
1242
+			val = 0x88;
1243
+			writel(val, priv->mmio + (0xc << 2));
1244
+			val = 0x56;
1245
+			writel(val, priv->mmio + (0xd << 2));
1246
+		}
1247
+	}
1248
+
1249
+	if (device_property_read_bool(priv->dev, "rockchip,enable-ssc")) {
1250
+		val = readl(priv->mmio + (0x7 << 2));
1251
+		val |= BIT(4);
1252
+		writel(val, priv->mmio + (0x7 << 2));
1253
+
1254
+		if (priv->mode == PHY_TYPE_PCIE && rate == 24000000) {
1255
+			/* Xin24M T0_1 650mV */
1256
+			writel(0x00, priv->mmio + (0x10 << 2));
1257
+			writel(0x32, priv->mmio + (0x11 << 2));
1258
+			writel(0x00, priv->mmio + (0x1b << 2));
1259
+			writel(0x90, priv->mmio + (0x0a << 2));
1260
+			writel(0x02, priv->mmio + (0x0b << 2));
1261
+			writel(0x08, priv->mmio + (0x0c << 2));
1262
+			writel(0x57, priv->mmio + (0x0d << 2));
1263
+			writel(0x40, priv->mmio + (0x0e << 2));
1264
+			writel(0x5f, priv->mmio + (0x0f << 2));
1265
+			writel(0x10, priv->mmio + (0x20 << 2));
1266
+		}
1267
+	}
1268
+
1269
+	return 0;
1270
+}
1271
+
1272
+static const struct rockchip_combphy_grfcfg rk3588_combphy_grfcfgs = {
1273
+	/* pipe-phy-grf */
1274
+	.pcie_mode_set		= { 0x0000, 5, 0, 0x00, 0x11 },
1275
+	.usb_mode_set		= { 0x0000, 5, 0, 0x00, 0x04 },
1276
+	.pipe_rxterm_set	= { 0x0000, 12, 12, 0x00, 0x01 },
1277
+	.pipe_txelec_set	= { 0x0004, 1, 1, 0x00, 0x01 },
1278
+	.pipe_txcomp_set	= { 0x0004, 4, 4, 0x00, 0x01 },
1279
+	.pipe_clk_24m		= { 0x0004, 14, 13, 0x00, 0x00 },
1280
+	.pipe_clk_25m		= { 0x0004, 14, 13, 0x00, 0x01 },
1281
+	.pipe_clk_100m		= { 0x0004, 14, 13, 0x00, 0x02 },
1282
+	.pipe_rxterm_sel	= { 0x0008, 8, 8, 0x00, 0x01 },
1283
+	.pipe_txelec_sel	= { 0x0008, 12, 12, 0x00, 0x01 },
1284
+	.pipe_txcomp_sel	= { 0x0008, 15, 15, 0x00, 0x01 },
1285
+	.pipe_clk_ext		= { 0x000c, 9, 8, 0x02, 0x01 },
1286
+	.pipe_phy_status	= { 0x0034, 6, 6, 0x01, 0x00 },
1287
+	.con0_for_pcie		= { 0x0000, 15, 0, 0x00, 0x1000 },
1288
+	.con1_for_pcie		= { 0x0004, 15, 0, 0x00, 0x0000 },
1289
+	.con2_for_pcie		= { 0x0008, 15, 0, 0x00, 0x0101 },
1290
+	.con3_for_pcie		= { 0x000c, 15, 0, 0x00, 0x0200 },
1291
+	.con0_for_sata		= { 0x0000, 15, 0, 0x00, 0x0129 },
1292
+	.con1_for_sata		= { 0x0004, 15, 0, 0x00, 0x0000 },
1293
+	.con2_for_sata		= { 0x0008, 15, 0, 0x00, 0x80c1 },
1294
+	.con3_for_sata		= { 0x000c, 15, 0, 0x00, 0x0407 },
1295
+	/* pipe-grf */
1296
+	.pipe_con0_for_sata	= { 0x0000, 11, 5, 0x00, 0x22 },
1297
+	.pipe_con1_for_sata	= { 0x0004, 2, 0, 0x00, 0x2 },
1298
+};
1299
+
1300
+static const struct clk_bulk_data rk3588_clks[] = {
1301
+	{ .id = "refclk" },
1302
+	{ .id = "apbclk" },
1303
+	{ .id = "phpclk" },
1304
+};
1305
+
1306
+static const struct rockchip_combphy_cfg rk3588_combphy_cfgs = {
1307
+	.num_clks	= ARRAY_SIZE(rk3588_clks),
1308
+	.clks		= rk3588_clks,
1309
+	.grfcfg		= &rk3588_combphy_grfcfgs,
1310
+	.combphy_cfg	= rk3588_combphy_cfg,
1311
+	.force_det_out	= true,
1312
+};
1313
+
820
1314
 static const struct of_device_id rockchip_combphy_of_match[] = {
821
1315
 	{
822
1316
 		.compatible = "rockchip,rk3528-naneng-combphy",
823
1317
 		.data = &rk3528_combphy_cfgs,
824
1318
 	},
825
1319
 	{
1320
+		.compatible = "rockchip,rk3562-naneng-combphy",
1321
+		.data = &rk3562_combphy_cfgs,
1322
+	},
1323
+	{
826
1324
 		.compatible = "rockchip,rk3568-naneng-combphy",
827
1325
 		.data = &rk3568_combphy_cfgs,
828
1326
 	},
1327
+	{
1328
+		.compatible = "rockchip,rk3588-naneng-combphy",
1329
+		.data = &rk3588_combphy_cfgs,
1330
+	},
829
1331
 	{ },
830
1332
 };
831
1333
 MODULE_DEVICE_TABLE(of, rockchip_combphy_of_match);