| .. | .. |
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| 287 | 287 | return 0; |
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| 288 | 288 | } |
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| 289 | 289 | |
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| 290 | +static const char *rockchip_combphy_mode2str(enum phy_mode mode) |
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| 291 | +{ |
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| 292 | + switch (mode) { |
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| 293 | + case PHY_TYPE_SATA: |
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| 294 | + return "SATA"; |
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| 295 | + case PHY_TYPE_PCIE: |
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| 296 | + return "PCIe"; |
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| 297 | + case PHY_TYPE_USB3: |
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| 298 | + return "USB3"; |
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| 299 | + case PHY_TYPE_SGMII: |
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| 300 | + case PHY_TYPE_QSGMII: |
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| 301 | + return "GMII"; |
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| 302 | + default: |
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| 303 | + return "Unknown"; |
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| 304 | + } |
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| 305 | +} |
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| 306 | + |
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| 307 | +static int rockchip_combphy_validate(struct phy *phy, enum phy_mode mode, int submode, |
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| 308 | + union phy_configure_opts *opts) |
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| 309 | +{ |
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| 310 | + struct rockchip_combphy_priv *priv = phy_get_drvdata(phy); |
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| 311 | + |
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| 312 | + if (mode != priv->mode) { |
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| 313 | + dev_err(priv->dev, "expected mode is %s, but current mode is %s\n", |
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| 314 | + rockchip_combphy_mode2str(mode), |
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| 315 | + rockchip_combphy_mode2str(priv->mode)); |
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| 316 | + return -EINVAL; |
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| 317 | + } |
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| 318 | + |
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| 319 | + return 0; |
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| 320 | +} |
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| 321 | + |
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| 290 | 322 | static const struct phy_ops rochchip_combphy_ops = { |
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| 291 | 323 | .init = rockchip_combphy_init, |
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| 292 | 324 | .exit = rockchip_combphy_exit, |
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| 325 | + .validate = rockchip_combphy_validate, |
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| 293 | 326 | .owner = THIS_MODULE, |
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| 294 | 327 | }; |
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| 295 | 328 | |
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| .. | .. |
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| 482 | 515 | val &= ~GENMASK(17, 17); |
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| 483 | 516 | val |= 0x01 << 17; |
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| 484 | 517 | writel(val, priv->mmio + 0x200); |
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| 518 | + |
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| 519 | + /* Set slow slew rate control for PI */ |
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| 520 | + val = readl(priv->mmio + 0x204); |
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| 521 | + val &= ~GENMASK(2, 0); |
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| 522 | + val |= 0x07; |
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| 523 | + writel(val, priv->mmio + 0x204); |
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| 524 | + |
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| 525 | + /* Set CDR phase path with 2x gain */ |
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| 526 | + val = readl(priv->mmio + 0x204); |
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| 527 | + val &= ~GENMASK(5, 5); |
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| 528 | + val |= 0x01 << 5; |
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| 529 | + writel(val, priv->mmio + 0x204); |
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| 485 | 530 | |
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| 486 | 531 | /* Set Rx squelch input filler bandwidth */ |
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| 487 | 532 | val = readl(priv->mmio + 0x20c); |
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| .. | .. |
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| 697 | 742 | /* CKDRV output swing adjust to 650mv */ |
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| 698 | 743 | val = readl(priv->mmio + (0xd << 2)); |
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| 699 | 744 | val &= ~(0xf << 1); |
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| 700 | | - val |= 0xb; |
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| 745 | + val |= (0xb << 1); |
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| 701 | 746 | writel(val, priv->mmio + (0xd << 2)); |
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| 702 | 747 | } |
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| 703 | 748 | break; |
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