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2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf 
 kernel/drivers/net/ethernet/qlogic/qed/qed_reg_addr.h
....@@ -1,33 +1,7 @@
1
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
12 /* QLogic qed NIC Driver
23  * Copyright (c) 2015-2017  QLogic Corporation
3
- *
4
- * This software is available to you under a choice of one of two
5
- * licenses.  You may choose to be licensed under the terms of the GNU
6
- * General Public License (GPL) Version 2, available from the file
7
- * COPYING in the main directory of this source tree, or the
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- * OpenIB.org BSD license below:
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- *
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- *     Redistribution and use in source and binary forms, with or
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- *     without modification, are permitted provided that the following
12
- *     conditions are met:
13
- *
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- *      - Redistributions of source code must retain the above
15
- *        copyright notice, this list of conditions and the following
16
- *        disclaimer.
17
- *
18
- *      - Redistributions in binary form must reproduce the above
19
- *        copyright notice, this list of conditions and the following
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- *        disclaimer in the documentation and /or other materials
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- *        provided with the distribution.
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- *
23
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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- * SOFTWARE.
4
+ * Copyright (c) 2019-2020 Marvell International Ltd.
315  */
326 
337 #ifndef REG_ADDR_H
....@@ -178,6 +152,8 @@
178152 	0x008c80UL
179153 #define  MCP_REG_SCRATCH	\
180154 	0xe20000UL
155
+#define MCP_REG_SCRATCH_SIZE \
156
+	57344
181157 #define  CNIG_REG_NW_PORT_MODE_BB \
182158 	0x218200UL
183159 #define  MISCS_REG_CHIP_NUM \
....@@ -212,6 +188,8 @@
212188 	0x580900UL
213189 #define  DBG_REG_CLIENT_ENABLE \
214190 	0x010004UL
191
+#define DBG_REG_TIMESTAMP_VALID_EN \
192
+	0x010b58UL
215193 #define  DMAE_REG_INIT \
216194 	0x00c000UL
217195 #define  DORQ_REG_IFEN \
....@@ -254,6 +232,10 @@
254232 	0x500840UL
255233 #define NIG_REG_LLH_TAGMAC_DEF_PF_VECTOR \
256234 	0x50196cUL
235
+#define NIG_REG_LLH_PPFID2PFID_TBL_0 \
236
+	0x501970UL
237
+#define NIG_REG_LLH_ENG_CLS_ROCE_QP_SEL	\
238
+	0x50
257239 #define NIG_REG_LLH_CLS_TYPE_DUALMODE \
258240 	0x501964UL
259241 #define NIG_REG_LLH_FUNC_TAG_EN 0x5019b0UL
....@@ -346,6 +328,10 @@
346328 	0x24000cUL
347329 #define PSWRQ2_REG_ILT_MEMORY \
348330 	0x260000UL
331
+#define PSWRQ2_REG_ILT_MEMORY_SIZE_BB \
332
+	15200
333
+#define PSWRQ2_REG_ILT_MEMORY_SIZE_K2 \
334
+	22000
349335 #define  PSWHST_REG_DISCARD_INTERNAL_WRITES \
350336 	0x2a0040UL
351337 #define  PSWHST2_REG_DBGSYN_ALMOST_FULL_THR \
....@@ -518,6 +504,8 @@
518504 	0x180824UL
519505 #define  MISC_REG_AEU_GENERAL_ATTN_0 \
520506 	0x008400UL
507
+#define MISC_REG_AEU_GENERAL_ATTN_35 \
508
+	0x00848cUL
521509 #define  CAU_REG_SB_ADDR_MEMORY \
522510 	0x1c8000UL
523511 #define  CAU_REG_SB_VAR_MEMORY \
....@@ -1243,6 +1231,56 @@
12431231 	0x1701534UL
12441232 #define TSEM_REG_DBG_FORCE_FRAME \
12451233 	0x1701538UL
1234
+#define DORQ_REG_PF_USAGE_CNT \
1235
+	0x1009c0UL
1236
+#define DORQ_REG_PF_OVFL_STICKY	\
1237
+	0x1009d0UL
1238
+#define DORQ_REG_DPM_FORCE_ABORT \
1239
+	0x1009d8UL
1240
+#define DORQ_REG_INT_STS \
1241
+	0x100180UL
1242
+#define DORQ_REG_INT_STS_ADDRESS_ERROR \
1243
+	(0x1UL << 0)
1244
+#define DORQ_REG_INT_STS_WR \
1245
+	0x100188UL
1246
+#define DORQ_REG_DB_DROP_DETAILS_REL \
1247
+	0x100a28UL
1248
+#define DORQ_REG_INT_STS_ADDRESS_ERROR_SHIFT \
1249
+	0
1250
+#define DORQ_REG_INT_STS_DB_DROP \
1251
+		(0x1UL << 1)
1252
+#define DORQ_REG_INT_STS_DB_DROP_SHIFT \
1253
+	1
1254
+#define DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR \
1255
+		(0x1UL << 2)
1256
+#define DORQ_REG_INT_STS_DORQ_FIFO_OVFL_ERR_SHIFT \
1257
+	2
1258
+#define DORQ_REG_INT_STS_DORQ_FIFO_AFULL\
1259
+		(0x1UL << 3)
1260
+#define DORQ_REG_INT_STS_DORQ_FIFO_AFULL_SHIFT \
1261
+	3
1262
+#define DORQ_REG_INT_STS_CFC_BYP_VALIDATION_ERR \
1263
+		(0x1UL << 4)
1264
+#define DORQ_REG_INT_STS_CFC_BYP_VALIDATION_ERR_SHIFT \
1265
+	4
1266
+#define DORQ_REG_INT_STS_CFC_LD_RESP_ERR \
1267
+		(0x1UL << 5)
1268
+#define DORQ_REG_INT_STS_CFC_LD_RESP_ERR_SHIFT \
1269
+	5
1270
+#define DORQ_REG_INT_STS_XCM_DONE_CNT_ERR \
1271
+		(0x1UL << 6)
1272
+#define DORQ_REG_INT_STS_XCM_DONE_CNT_ERR_SHIFT	\
1273
+	6
1274
+#define DORQ_REG_INT_STS_CFC_LD_REQ_FIFO_OVFL_ERR \
1275
+		(0x1UL << 7)
1276
+#define DORQ_REG_INT_STS_CFC_LD_REQ_FIFO_OVFL_ERR_SHIFT	\
1277
+	7
1278
+#define DORQ_REG_INT_STS_CFC_LD_REQ_FIFO_UNDER_ERR \
1279
+		(0x1UL << 8)
1280
+#define DORQ_REG_INT_STS_CFC_LD_REQ_FIFO_UNDER_ERR_SHIFT \
1281
+	8
1282
+#define DORQ_REG_DB_DROP_DETAILS_REASON	\
1283
+	0x100a20UL
12461284 #define MSEM_REG_DBG_SELECT \
12471285 	0x1801528UL
12481286 #define MSEM_REG_DBG_DWORD_ENABLE \
....@@ -1397,6 +1435,8 @@
13971435 	0x1401404UL
13981436 #define XSEM_REG_DBG_FRAME_MODE_BB_K2	\
13991437 	0x1401408UL
1438
+#define XSEM_REG_DBG_GPRE_VECT \
1439
+	0x1401410UL
14001440 #define XSEM_REG_DBG_MODE1_CFG_BB_K2 \
14011441 	0x1401420UL
14021442 #define XSEM_REG_FAST_MEMORY \
....@@ -1409,6 +1449,8 @@
14091449 	0x1501404UL
14101450 #define YSEM_REG_DBG_FRAME_MODE_BB_K2	\
14111451 	0x1501408UL
1452
+#define YSEM_REG_DBG_GPRE_VECT \
1453
+	0x1501410UL
14121454 #define YSEM_REG_DBG_MODE1_CFG_BB_K2 \
14131455 	0x1501420UL
14141456 #define YSEM_REG_FAST_MEMORY \
....@@ -1423,6 +1465,8 @@
14231465 	0x1601404UL
14241466 #define PSEM_REG_DBG_FRAME_MODE_BB_K2	\
14251467 	0x1601408UL
1468
+#define PSEM_REG_DBG_GPRE_VECT \
1469
+	0x1601410UL
14261470 #define PSEM_REG_DBG_MODE1_CFG_BB_K2 \
14271471 	0x1601420UL
14281472 #define PSEM_REG_FAST_MEMORY \
....@@ -1437,6 +1481,8 @@
14371481 	0x1701404UL
14381482 #define TSEM_REG_DBG_FRAME_MODE_BB_K2	\
14391483 	0x1701408UL
1484
+#define TSEM_REG_DBG_GPRE_VECT \
1485
+	0x1701410UL
14401486 #define TSEM_REG_DBG_MODE1_CFG_BB_K2 \
14411487 	0x1701420UL
14421488 #define TSEM_REG_FAST_MEMORY \
....@@ -1451,12 +1497,16 @@
14511497 	0x1801404UL
14521498 #define MSEM_REG_DBG_FRAME_MODE_BB_K2	\
14531499 	0x1801408UL
1500
+#define MSEM_REG_DBG_GPRE_VECT \
1501
+	0x1801410UL
14541502 #define MSEM_REG_DBG_MODE1_CFG_BB_K2 \
14551503 	0x1801420UL
14561504 #define MSEM_REG_FAST_MEMORY \
14571505 	0x1840000UL
14581506 #define USEM_REG_SLOW_DBG_EMPTY_BB_K2	\
14591507 	0x1901140UL
1508
+#define SEM_FAST_REG_INT_RAM_SIZE \
1509
+	20480
14601510 #define USEM_REG_SYNC_DBG_EMPTY	\
14611511 	0x1901160UL
14621512 #define USEM_REG_SLOW_DBG_ACTIVE_BB_K2 \
....@@ -1465,14 +1515,26 @@
14651515 	0x1901404UL
14661516 #define USEM_REG_DBG_FRAME_MODE_BB_K2	\
14671517 	0x1901408UL
1518
+#define USEM_REG_DBG_GPRE_VECT \
1519
+	0x1901410UL
14681520 #define USEM_REG_DBG_MODE1_CFG_BB_K2 \
14691521 	0x1901420UL
14701522 #define USEM_REG_FAST_MEMORY \
14711523 	0x1940000UL
1524
+#define SEM_FAST_REG_DBG_MODE23_SRC_DISABLE \
1525
+	0x000748UL
1526
+#define SEM_FAST_REG_DBG_MODE4_SRC_DISABLE \
1527
+	0x00074cUL
1528
+#define SEM_FAST_REG_DBG_MODE6_SRC_DISABLE \
1529
+	0x000750UL
1530
+#define SEM_FAST_REG_DEBUG_ACTIVE \
1531
+	0x000740UL
14721532 #define SEM_FAST_REG_INT_RAM \
14731533 	0x020000UL
14741534 #define SEM_FAST_REG_INT_RAM_SIZE_BB_K2 \
14751535 	20480
1536
+#define SEM_FAST_REG_RECORD_FILTER_ENABLE \
1537
+	0x000768UL
14761538 #define GRC_REG_TRACE_FIFO_VALID_DATA \
14771539 	0x050064UL
14781540 #define GRC_REG_NUMBER_VALID_OVERRIDE_WINDOW \
....@@ -1527,14 +1589,20 @@
15271589 	0x181530UL
15281590 #define DBG_REG_DBG_BLOCK_ON \
15291591 	0x010454UL
1592
+#define DBG_REG_FILTER_ENABLE \
1593
+	0x0109d0UL
15301594 #define DBG_REG_FRAMING_MODE \
15311595 	0x010058UL
1596
+#define DBG_REG_TRIGGER_ENABLE \
1597
+	0x01054cUL
15321598 #define SEM_FAST_REG_VFC_DATA_WR \
15331599 	0x000b40UL
15341600 #define SEM_FAST_REG_VFC_ADDR \
15351601 	0x000b44UL
15361602 #define SEM_FAST_REG_VFC_DATA_RD \
15371603 	0x000b48UL
1604
+#define SEM_FAST_REG_VFC_STATUS	\
1605
+	0x000b4cUL
15381606 #define RSS_REG_RSS_RAM_DATA \
15391607 	0x238c20UL
15401608 #define RSS_REG_RSS_RAM_DATA_SIZE \
....@@ -1574,6 +1642,8 @@
15741642 #define PHY_PCIE_REG_PHY1_K2_E5 \
15751643 	0x624000UL
15761644 #define NIG_REG_ROCE_DUPLICATE_TO_HOST 0x5088f0UL
1645
+#define NIG_REG_PPF_TO_ENGINE_SEL 0x508900UL
1646
+#define NIG_REG_PPF_TO_ENGINE_SEL_SIZE 8
15771647 #define PRS_REG_LIGHT_L2_ETHERTYPE_EN 0x1f0968UL
15781648 #define NIG_REG_LLH_ENG_CLS_ENG_ID_TBL 0x501b90UL
15791649 #define DORQ_REG_PF_DPM_ENABLE 0x100510UL