update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/drivers/mtd/nand/spi/xtx.c
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@@ -203,6 +203,28 @@
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 		return -EBADMSG;
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 }
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+static int xt26g11c_ecc_get_status(struct spinand_device *spinand,
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+				   u8 status)
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+{
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+	struct nand_device *nand = spinand_to_nand(spinand);
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+
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+	switch (status & STATUS_ECC_MASK) {
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+	case STATUS_ECC_NO_BITFLIPS:
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+		return 0;
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+
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+	case STATUS_ECC_UNCOR_ERROR:
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+		return -EBADMSG;
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+
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+	case STATUS_ECC_HAS_BITFLIPS:
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+		return 1;
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+
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+	default:
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+		return nanddev_get_ecc_requirements(nand)->strength;
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+	}
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+
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+	return -EINVAL;
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+}
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+
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 static const struct spinand_info xtx_spinand_table[] = {
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 	SPINAND_INFO("XT26G01A",
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 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_ADDR, 0xE1),
..
..
@@ -293,7 +315,61 @@
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 					      &update_cache_variants),
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 		     SPINAND_HAS_QE_BIT,
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 		     SPINAND_ECCINFO(&xt26g01c_ooblayout,
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-				     xt26g01c_ecc_get_status)),
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+				     xt26g11c_ecc_get_status)),
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+	SPINAND_INFO("XT26Q02DWSIGA",
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+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x52),
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+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
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+		     NAND_ECCREQ(8, 512),
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+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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+					      &write_cache_variants,
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+					      &update_cache_variants),
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+		     SPINAND_HAS_QE_BIT,
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+		     SPINAND_ECCINFO(&xt26g01c_ooblayout, xt26g11c_ecc_get_status)),
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+	SPINAND_INFO("XT26Q01DWSIGA",
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+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x51),
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+		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
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+		     NAND_ECCREQ(8, 512),
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+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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+					      &write_cache_variants,
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+					      &update_cache_variants),
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+		     SPINAND_HAS_QE_BIT,
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+		     SPINAND_ECCINFO(&xt26g01c_ooblayout, xt26g11c_ecc_get_status)),
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+	SPINAND_INFO("XT26Q04DWSIGA",
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+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x53),
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+		     NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
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+		     NAND_ECCREQ(8, 512),
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+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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+					      &write_cache_variants,
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+					      &update_cache_variants),
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+		     SPINAND_HAS_QE_BIT,
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+		     SPINAND_ECCINFO(&xt26g01c_ooblayout, xt26g11c_ecc_get_status)),
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+	SPINAND_INFO("XT26G01DWSIGA",
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+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x31),
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+		     NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
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+		     NAND_ECCREQ(8, 512),
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+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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+					      &write_cache_variants,
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+					      &update_cache_variants),
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+		     SPINAND_HAS_QE_BIT,
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+		     SPINAND_ECCINFO(&xt26g01b_ooblayout, xt26g11c_ecc_get_status)),
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+	SPINAND_INFO("XT26G02DWSIGA",
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+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x32),
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+		     NAND_MEMORG(1, 2048, 64, 64, 2048, 40, 1, 1, 1),
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+		     NAND_ECCREQ(8, 512),
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+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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+					      &write_cache_variants,
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+					      &update_cache_variants),
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+		     SPINAND_HAS_QE_BIT,
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+		     SPINAND_ECCINFO(&xt26g01b_ooblayout, xt26g11c_ecc_get_status)),
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+	SPINAND_INFO("XT26G04DWSIGA",
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+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x33),
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+		     NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
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+		     NAND_ECCREQ(8, 512),
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+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
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+					      &write_cache_variants,
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+					      &update_cache_variants),
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+		     SPINAND_HAS_QE_BIT,
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+		     SPINAND_ECCINFO(&xt26g01c_ooblayout, xt26g11c_ecc_get_status)),
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 };
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 static const struct spinand_manufacturer_ops xtx_spinand_manuf_ops = {