update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/drivers/media/platform/rockchip/isp/csi.c
..
..
@@ -12,9 +12,10 @@
12
12
 #include <media/v4l2-subdev.h>
13
13
 #include <media/videobuf2-dma-contig.h>
14
14
 #include "dev.h"
15
+#include "isp_external.h"
15
16
 #include "regs.h"
16
17
 
17
-static void get_remote_mipi_sensor(struct rkisp_device *dev,
18
+void rkisp_get_remote_mipi_sensor(struct rkisp_device *dev,
18
19
 				  struct v4l2_subdev **sensor_sd, u32 function)
19
20
 {
20
21
 	struct media_graph graph;
..
..
@@ -81,6 +82,8 @@
81
82
 		id = local->index - 1;
82
83
 		if (id && id < RKISP_STREAM_DMATX3)
83
84
 			stream = &csi->ispdev->cap_dev.stream[id + 1];
85
+		if (id >= ARRAY_SIZE(csi->sink))
86
+			return -EINVAL;
84
87
 		if (flags & MEDIA_LNK_FL_ENABLED) {
85
88
 			if (csi->sink[id].linked) {
86
89
 				ret = -EBUSY;
..
..
@@ -103,14 +106,15 @@
103
106
 }
104
107
 
105
108
 static int rkisp_csi_g_mbus_config(struct v4l2_subdev *sd,
106
-				  struct v4l2_mbus_config *config)
109
+				   unsigned int pad_id,
110
+				   struct v4l2_mbus_config *config)
107
111
 {
108
112
 	struct v4l2_subdev *remote_sd;
109
113
 
110
114
 	if (!sd)
111
115
 		return -ENODEV;
112
116
 	remote_sd = get_remote_subdev(sd);
113
-	return v4l2_subdev_call(remote_sd, video, g_mbus_config, config);
117
+	return v4l2_subdev_call(remote_sd, pad, get_mbus_config, pad_id, config);
114
118
 }
115
119
 
116
120
 static int rkisp_csi_get_set_fmt(struct v4l2_subdev *sd,
..
..
@@ -159,10 +163,10 @@
159
163
 static const struct v4l2_subdev_pad_ops rkisp_csi_pad_ops = {
160
164
 	.set_fmt = rkisp_csi_get_set_fmt,
161
165
 	.get_fmt = rkisp_csi_get_set_fmt,
166
+	.get_mbus_config = rkisp_csi_g_mbus_config,
162
167
 };
163
168
 
164
169
 static const struct v4l2_subdev_video_ops rkisp_csi_video_ops = {
165
-	.g_mbus_config = rkisp_csi_g_mbus_config,
166
170
 	.s_stream = rkisp_csi_s_stream,
167
171
 };
168
172
 
..
..
@@ -208,7 +212,7 @@
208
212
 	emd_vc = 0xFF;
209
213
 	emd_dt = 0;
210
214
 	dev->hdr.sensor = NULL;
211
-	get_remote_mipi_sensor(dev, &mipi_sensor, MEDIA_ENT_F_CAM_SENSOR);
215
+	rkisp_get_remote_mipi_sensor(dev, &mipi_sensor, MEDIA_ENT_F_CAM_SENSOR);
212
216
 	if (mipi_sensor) {
213
217
 		ctrl = v4l2_ctrl_find(mipi_sensor->ctrl_handler,
214
218
 				      CIFISP_CID_EMB_VC);
..
..
@@ -279,15 +283,10 @@
279
283
 
280
284
 		dev->hdr.op_mode = HDR_NORMAL;
281
285
 		dev->hdr.esp_mode = HDR_NORMAL_VC;
282
-		if (mipi_sensor) {
283
-			ret = v4l2_subdev_call(mipi_sensor,
284
-					       core, ioctl,
285
-					       RKMODULE_GET_HDR_CFG,
286
-					       &hdr_cfg);
287
-			if (!ret) {
288
-				dev->hdr.op_mode = hdr_cfg.hdr_mode;
289
-				dev->hdr.esp_mode = hdr_cfg.esp.mode;
290
-			}
286
+		memset(&hdr_cfg, 0, sizeof(hdr_cfg));
287
+		if (rkisp_csi_get_hdr_cfg(dev, &hdr_cfg) == 0) {
288
+			dev->hdr.op_mode = hdr_cfg.hdr_mode;
289
+			dev->hdr.esp_mode = hdr_cfg.esp.mode;
291
290
 		}
292
291
 
293
292
 		/* normal read back mode */
..
..
@@ -316,9 +315,13 @@
316
315
 			rkisp_write(dev, CSI2RX_DATA_IDS_1, val, true);
317
316
 		} else {
318
317
 			rkisp_set_bits(dev, CSI2RX_DATA_IDS_1, mask, val, true);
319
-			for (i = 0; i < dev->hw_dev->dev_num; i++)
318
+			for (i = 0; i < dev->hw_dev->dev_num; i++) {
319
+				if (dev->hw_dev->isp[i] &&
320
+				    !dev->hw_dev->isp[i]->is_hw_link)
321
+					continue;
320
322
 				rkisp_set_bits(dev->hw_dev->isp[i],
321
323
 					CSI2RX_DATA_IDS_1, mask, val, false);
324
+			}
322
325
 		}
323
326
 		val = SW_CSI_ID4(csi->mipi_di[4]);
324
327
 		rkisp_write(dev, CSI2RX_DATA_IDS_2, val, true);
..
..
@@ -338,9 +341,13 @@
338
341
 			Y_STAT_AFIFOX3_OVERFLOW;
339
342
 		rkisp_write(dev, CSI2RX_MASK_OVERFLOW, val, true);
340
343
 		val = RAW0_WR_FRAME | RAW1_WR_FRAME | RAW2_WR_FRAME |
341
-			MIPI_DROP_FRM | RAW_WR_SIZE_ERR | MIPI_LINECNT |
344
+			RAW_WR_SIZE_ERR | MIPI_LINECNT |
342
345
 			RAW_RD_SIZE_ERR | RAW0_Y_STATE |
343
346
 			RAW1_Y_STATE | RAW2_Y_STATE;
347
+		if (dev->isp_ver == ISP_V20)
348
+			val |= MIPI_DROP_FRM;
349
+		else
350
+			val |= ISP21_MIPI_DROP_FRM;
344
351
 		rkisp_write(dev, CSI2RX_MASK_STAT, val, true);
345
352
 
346
353
 		/* hdr merge */
..
..
@@ -423,6 +430,133 @@
423
430
 	return 0;
424
431
 }
425
432
 
433
+int rkisp_expander_config(struct rkisp_device *dev,
434
+			  struct rkmodule_hdr_cfg *cfg, bool on)
435
+{
436
+	struct rkmodule_hdr_cfg hdr_cfg;
437
+	u32 i, val, num, d0, d1, drop_bit = 0;
438
+
439
+	if (dev->isp_ver != ISP_V32)
440
+		return 0;
441
+
442
+	if (!on) {
443
+		rkisp_write(dev, ISP32_EXPD_CTRL, 0, false);
444
+		return 0;
445
+	}
446
+
447
+	if (!cfg) {
448
+		if (rkisp_csi_get_hdr_cfg(dev, &hdr_cfg) != 0)
449
+			goto err;
450
+		cfg = &hdr_cfg;
451
+	}
452
+
453
+	if (cfg->hdr_mode != HDR_COMPR)
454
+		return 0;
455
+
456
+	/* compressed data max 12bit and src data max 20bit */
457
+	if (cfg->compr.bit > 20)
458
+		drop_bit = cfg->compr.bit - 20;
459
+	dev->hdr.compr_bit = cfg->compr.bit - drop_bit;
460
+
461
+	num = cfg->compr.segment;
462
+	for (i = 0; i < num; i++) {
463
+		val = cfg->compr.slope_k[i];
464
+		rkisp_write(dev, ISP32_EXPD_K0 + i * 4, val, false);
465
+	}
466
+
467
+	d0 = 0;
468
+	d1 = cfg->compr.data_compr[0];
469
+	val = ISP32_EXPD_DATA(d0, d1 > 0xfff ? 0xfff : d1);
470
+	rkisp_write(dev, ISP32_EXPD_X00_01, val, false);
471
+
472
+	d1 = cfg->compr.data_src_shitf[0];
473
+	val = ISP32_EXPD_DATA(d0, drop_bit ? d1 >> drop_bit : d1);
474
+	rkisp_write(dev, ISP32_EXPD_Y00_01, val, false);
475
+
476
+	for (i = 1; i < num - 1; i += 2) {
477
+		d0 = cfg->compr.data_compr[i];
478
+		d1 = cfg->compr.data_compr[i + 1];
479
+		val = ISP32_EXPD_DATA(d0 > 0xfff ? 0xfff : d0,
480
+				      d1 > 0xfff ? 0xfff : d1);
481
+		rkisp_write(dev, ISP32_EXPD_X00_01 + (i + 1) * 2, val, false);
482
+
483
+		d0 = cfg->compr.data_src_shitf[i];
484
+		d1 = cfg->compr.data_src_shitf[i + 1];
485
+		if (drop_bit) {
486
+			d0 = d0 >> drop_bit;
487
+			d1 = d1 >> drop_bit;
488
+		}
489
+		val = ISP32_EXPD_DATA(d0, d1);
490
+		rkisp_write(dev, ISP32_EXPD_Y00_01 + (i + 1) * 2, val, false);
491
+	}
492
+
493
+	/* the last valid point */
494
+	val = cfg->compr.data_compr[i];
495
+	val = val > 0xfff ? 0xfff : val;
496
+	d0 = ISP32_EXPD_DATA(val, val);
497
+
498
+	val = cfg->compr.data_src_shitf[i];
499
+	val = drop_bit ? val >> drop_bit : val;
500
+	d1 = ISP32_EXPD_DATA(val, val);
501
+
502
+	num = HDR_COMPR_SEGMENT_16;
503
+	for (; i < num - 1; i += 2) {
504
+		rkisp_write(dev, ISP32_EXPD_X00_01 + (i + 1) * 2, d0, false);
505
+		rkisp_write(dev, ISP32_EXPD_Y00_01 + (i + 1) * 2, d1, false);
506
+	}
507
+	rkisp_write(dev, ISP32_EXPD_Y16, val, false);
508
+
509
+	switch (cfg->compr.segment) {
510
+	case HDR_COMPR_SEGMENT_12:
511
+		num = 1;
512
+		break;
513
+	case HDR_COMPR_SEGMENT_16:
514
+		num = 2;
515
+		break;
516
+	default:
517
+		num = 0;
518
+	}
519
+	val = ISP32_EXPD_EN |
520
+	      ISP32_EXPD_MODE(num) |
521
+	      ISP32_EXPD_K_SHIFT(cfg->compr.k_shift);
522
+	rkisp_write(dev, ISP32_EXPD_CTRL, val, false);
523
+	return 0;
524
+err:
525
+	return -EINVAL;
526
+}
527
+
528
+int rkisp_csi_get_hdr_cfg(struct rkisp_device *dev, void *arg)
529
+{
530
+	struct rkmodule_hdr_cfg *cfg = arg;
531
+	struct v4l2_subdev *sd = NULL;
532
+	u32 type;
533
+
534
+	if (dev->isp_inp & INP_CSI) {
535
+		type = MEDIA_ENT_F_CAM_SENSOR;
536
+	} else if (dev->isp_inp & INP_CIF) {
537
+		type = MEDIA_ENT_F_PROC_VIDEO_COMPOSER;
538
+	} else {
539
+		switch (dev->isp_inp & 0x7) {
540
+		case INP_RAWRD2 | INP_RAWRD0:
541
+			cfg->hdr_mode = HDR_RDBK_FRAME2;
542
+			break;
543
+		case INP_RAWRD2 | INP_RAWRD1 | INP_RAWRD0:
544
+			cfg->hdr_mode = HDR_RDBK_FRAME3;
545
+			break;
546
+		default: //INP_RAWRD2
547
+			cfg->hdr_mode = HDR_RDBK_FRAME1;
548
+		}
549
+		return 0;
550
+	}
551
+	rkisp_get_remote_mipi_sensor(dev, &sd, type);
552
+	if (!sd) {
553
+		v4l2_err(&dev->v4l2_dev, "%s don't find subdev\n", __func__);
554
+		return -EINVAL;
555
+	}
556
+
557
+	return v4l2_subdev_call(sd, core, ioctl, RKMODULE_GET_HDR_CFG, cfg);
558
+}
559
+
426
560
 int rkisp_csi_config_patch(struct rkisp_device *dev)
427
561
 {
428
562
 	int val = 0, ret = 0;
..
..
@@ -434,63 +568,106 @@
434
568
 		dev->hw_dev->mipi_dev_id = dev->dev_id;
435
569
 		ret = csi_config(&dev->csi_dev);
436
570
 	} else {
437
-		if (dev->isp_inp & INP_CIF) {
438
-			struct rkmodule_hdr_cfg hdr_cfg;
571
+		struct rkmodule_hdr_cfg hdr_cfg;
439
572
 
440
-			get_remote_mipi_sensor(dev, &mipi_sensor, MEDIA_ENT_F_PROC_VIDEO_COMPOSER);
573
+		memset(&hdr_cfg, 0, sizeof(hdr_cfg));
574
+		ret = rkisp_csi_get_hdr_cfg(dev, &hdr_cfg);
575
+		if (dev->isp_inp & INP_CIF) {
576
+			struct rkisp_vicap_mode mode;
577
+			int buf_cnt;
578
+
579
+			memset(&mode, 0, sizeof(mode));
580
+			mode.name = dev->name;
581
+
582
+			rkisp_get_remote_mipi_sensor(dev, &mipi_sensor, MEDIA_ENT_F_PROC_VIDEO_COMPOSER);
583
+			if (!mipi_sensor)
584
+				return -EINVAL;
441
585
 			dev->hdr.op_mode = HDR_NORMAL;
442
586
 			dev->hdr.esp_mode = HDR_NORMAL_VC;
443
-			if (mipi_sensor) {
444
-				ret = v4l2_subdev_call(mipi_sensor,
445
-						       core, ioctl,
446
-						       RKMODULE_GET_HDR_CFG,
447
-						       &hdr_cfg);
448
-				if (!ret) {
449
-					dev->hdr.op_mode = hdr_cfg.hdr_mode;
450
-					dev->hdr.esp_mode = hdr_cfg.esp.mode;
451
-				}
587
+			if (!ret) {
588
+				dev->hdr.op_mode = hdr_cfg.hdr_mode;
589
+				dev->hdr.esp_mode = hdr_cfg.esp.mode;
590
+				rkisp_expander_config(dev, &hdr_cfg, true);
452
591
 			}
453
592
 
454
-			/* normal read back mode */
455
-			if (dev->hdr.op_mode == HDR_NORMAL)
593
+			/* normal read back mode default */
594
+			if (dev->hdr.op_mode == HDR_NORMAL || dev->hdr.op_mode == HDR_COMPR)
456
595
 				dev->hdr.op_mode = HDR_RDBK_FRAME1;
457
-		} else {
458
-			switch (dev->isp_inp & 0x7) {
459
-			case INP_RAWRD2 | INP_RAWRD0:
460
-				dev->hdr.op_mode = HDR_RDBK_FRAME2;
461
-				break;
462
-			case INP_RAWRD2 | INP_RAWRD1 | INP_RAWRD0:
463
-				dev->hdr.op_mode = HDR_RDBK_FRAME3;
464
-				break;
465
-			default: //INP_RAWRD2
466
-				dev->hdr.op_mode = HDR_RDBK_FRAME1;
596
+
597
+			if (dev->isp_inp == INP_CIF && dev->isp_ver > ISP_V21)
598
+				mode.rdbk_mode = dev->is_rdbk_auto ? RKISP_VICAP_RDBK_AUTO : RKISP_VICAP_ONLINE;
599
+			else
600
+				mode.rdbk_mode = RKISP_VICAP_RDBK_AIQ;
601
+			v4l2_subdev_call(mipi_sensor, core, ioctl, RKISP_VICAP_CMD_MODE, &mode);
602
+			dev->vicap_in = mode.input;
603
+			/* vicap direct to isp */
604
+			if (dev->isp_ver >= ISP_V30 && !mode.rdbk_mode) {
605
+				switch (dev->hdr.op_mode) {
606
+				case HDR_RDBK_FRAME3:
607
+					dev->hdr.op_mode = HDR_LINEX3_DDR;
608
+					break;
609
+				case HDR_RDBK_FRAME2:
610
+					dev->hdr.op_mode = HDR_LINEX2_DDR;
611
+					break;
612
+				default:
613
+					dev->hdr.op_mode = HDR_NORMAL;
614
+				}
615
+				if (dev->hdr.op_mode != HDR_NORMAL) {
616
+					buf_cnt = 1;
617
+					v4l2_subdev_call(mipi_sensor, core, ioctl,
618
+							 RKISP_VICAP_CMD_INIT_BUF, &buf_cnt);
619
+				}
620
+			} else if (mode.rdbk_mode == RKISP_VICAP_RDBK_AUTO) {
621
+				buf_cnt = RKISP_VICAP_BUF_CNT;
622
+				v4l2_subdev_call(mipi_sensor, core, ioctl,
623
+						 RKISP_VICAP_CMD_INIT_BUF, &buf_cnt);
467
624
 			}
625
+		} else {
626
+			dev->hdr.op_mode = hdr_cfg.hdr_mode;
468
627
 		}
469
628
 
470
-		if (dev->hdr.op_mode == HDR_RDBK_FRAME2)
471
-			val = SW_HDRMGE_EN | SW_HDRMGE_MODE_FRAMEX2;
472
-		else if (dev->hdr.op_mode == HDR_RDBK_FRAME3)
473
-			val = SW_HDRMGE_EN | SW_HDRMGE_MODE_FRAMEX3;
474
-
475
629
 		if (!dev->hw_dev->is_mi_update)
476
-			rkisp_write(dev, CSI2RX_CTRL0,
477
-				    SW_IBUF_OP_MODE(dev->hdr.op_mode), true);
630
+			rkisp_unite_write(dev, CSI2RX_CTRL0,
631
+					  SW_IBUF_OP_MODE(dev->hdr.op_mode), true);
478
632
 
633
+		/* hdr merge */
634
+		switch (dev->hdr.op_mode) {
635
+		case HDR_RDBK_FRAME2:
636
+		case HDR_FRAMEX2_DDR:
637
+		case HDR_LINEX2_DDR:
638
+		case HDR_LINEX2_NO_DDR:
639
+			val = SW_HDRMGE_EN | SW_HDRMGE_MODE_FRAMEX2;
640
+			break;
641
+		case HDR_RDBK_FRAME3:
642
+		case HDR_FRAMEX3_DDR:
643
+		case HDR_LINEX3_DDR:
644
+			val = SW_HDRMGE_EN | SW_HDRMGE_MODE_FRAMEX3;
645
+			break;
646
+		default:
647
+			val = 0;
648
+		}
479
649
 		if (is_feature_on) {
480
650
 			if ((ISP2X_MODULE_HDRMGE & ~iq_feature) && (val & SW_HDRMGE_EN)) {
481
651
 				v4l2_err(&dev->v4l2_dev, "hdrmge is not supported\n");
482
652
 				return -EINVAL;
483
653
 			}
484
654
 		}
485
-		rkisp_write(dev, ISP_HDRMGE_BASE, val, false);
655
+		rkisp_unite_write(dev, ISP_HDRMGE_BASE, val, false);
486
656
 
487
-		rkisp_set_bits(dev, CSI2RX_MASK_STAT, 0, RAW_RD_SIZE_ERR, true);
657
+		val = RAW_RD_SIZE_ERR;
658
+		if (!IS_HDR_RDBK(dev->hdr.op_mode))
659
+			val |= ISP21_MIPI_DROP_FRM;
660
+		rkisp_unite_set_bits(dev, CSI2RX_MASK_STAT, 0, val, true);
488
661
 	}
489
662
 
490
663
 	if (IS_HDR_RDBK(dev->hdr.op_mode))
491
-		rkisp_set_bits(dev, CTRL_SWS_CFG, 0, SW_MPIP_DROP_FRM_DIS, true);
664
+		rkisp_unite_set_bits(dev, CTRL_SWS_CFG, 0, SW_MPIP_DROP_FRM_DIS, true);
492
665
 
493
-	memset(dev->filt_state, 0, sizeof(dev->filt_state));
666
+	if (dev->isp_ver >= ISP_V30)
667
+		rkisp_unite_set_bits(dev, CTRL_SWS_CFG, 0, ISP3X_SW_ACK_FRM_PRO_DIS, true);
668
+	/* line counter from isp out, default from mp out */
669
+	if (dev->isp_ver == ISP_V32_L)
670
+		rkisp_unite_set_bits(dev, CTRL_SWS_CFG, 0, ISP32L_ISP2ENC_CNT_MUX, true);
494
671
 	dev->rdbk_cnt = -1;
495
672
 	dev->rdbk_cnt_x1 = -1;
496
673
 	dev->rdbk_cnt_x2 = -1;
..
..
@@ -556,6 +733,8 @@
556
733
 		csi_dev->pads[CSI_SRC_CH2].flags = MEDIA_PAD_FL_SOURCE;
557
734
 		csi_dev->pads[CSI_SRC_CH3].flags = MEDIA_PAD_FL_SOURCE;
558
735
 		csi_dev->pads[CSI_SRC_CH4].flags = MEDIA_PAD_FL_SOURCE;
736
+	} else if (dev->isp_ver >= ISP_V30) {
737
+		return 0;
559
738
 	}
560
739
 
561
740
 	ret = media_entity_pads_init(&sd->entity, csi_dev->max_pad,