~ljy/RK356X_SDK_RELEASE.git

..	..	@@ -70,8 +70,7 @@
70	70
71	71	/*
72	72	* Legal values for the SVGA_REG_CURSOR_ON register in old-fashioned
73		- * cursor bypass mode. This is still supported, but no new guest
74		- * drivers should use it.
	73	+ * cursor bypass mode.
75	74	*/
76	75	#define SVGA_CURSOR_ON_HIDE 0x0
77	76	#define SVGA_CURSOR_ON_SHOW 0x1
..	..	@@ -137,6 +136,17 @@
137	136	#define SVGA_IRQFLAG_ERROR 0x10 /* Error while processing commands */
138	137
139	138	/*
	139	+ * The byte-size is the size of the actual cursor data,
	140	+ * possibly after expanding it to the current bit depth.
	141	+ *
	142	+ * 40K is sufficient memory for two 32-bit planes for a 64 x 64 cursor.
	143	+ *
	144	+ * The dimension limit is a bound on the maximum width or height.
	145	+ */
	146	+#define SVGA_MAX_CURSOR_CMD_BYTES (40 * 1024)
	147	+#define SVGA_MAX_CURSOR_CMD_DIMENSION 1024
	148	+
	149	+/*
140	150	* Registers
141	151	*/
142	152
..	..	@@ -169,7 +179,7 @@
169	179	SVGA_REG_SYNC = 21, /* See "FIFO Synchronization Registers" */
170	180	SVGA_REG_BUSY = 22, /* See "FIFO Synchronization Registers" */
171	181	SVGA_REG_GUEST_ID = 23, /* (Deprecated) */
172		- SVGA_REG_CURSOR_ID = 24, /* (Deprecated) */
	182	+ SVGA_REG_DEAD = 24, /* Drivers should never write this. */
173	183	SVGA_REG_CURSOR_X = 25, /* (Deprecated) */
174	184	SVGA_REG_CURSOR_Y = 26, /* (Deprecated) */
175	185	SVGA_REG_CURSOR_ON = 27, /* (Deprecated) */
..	..	@@ -208,7 +218,13 @@
208	218	SVGA_REG_MAX_PRIMARY_MEM = 50,
209	219	SVGA_REG_MAX_PRIMARY_BOUNDING_BOX_MEM = 50,
210	220
211		- SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB = 51, /* Sugested limit on mob mem */
	221	+ /*
	222	+ * Legacy version of SVGA_REG_GBOBJECT_MEM_SIZE_KB for drivers that
	223	+ * don't know how to convert to a 64-bit byte value without overflowing.
	224	+ * (See SVGA_REG_GBOBJECT_MEM_SIZE_KB).
	225	+ */
	226	+ SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB = 51,
	227	+
212	228	SVGA_REG_DEV_CAP = 52, /* Write dev cap index, read value */
213	229	SVGA_REG_CMD_PREPEND_LOW = 53,
214	230	SVGA_REG_CMD_PREPEND_HIGH = 54,
..	..	@@ -218,7 +234,59 @@
218	234	SVGA_REG_BLANK_SCREEN_TARGETS = 58,
219	235	SVGA_REG_CAP2 = 59,
220	236	SVGA_REG_DEVEL_CAP = 60,
221		- SVGA_REG_TOP = 61, /* Must be 1 more than the last register */
	237	+
	238	+ /*
	239	+ * Allow the guest to hint to the device which driver is running.
	240	+ *
	241	+ * This should not generally change device behavior, but might be
	242	+ * convenient to work-around specific bugs in guest drivers.
	243	+ *
	244	+ * Drivers should first write their id value into SVGA_REG_GUEST_DRIVER_ID,
	245	+ * and then fill out all of the version registers that they have defined.
	246	+ *
	247	+ * After the driver has written all of the registers, they should
	248	+ * then write the value SVGA_REG_GUEST_DRIVER_ID_SUBMIT to the
	249	+ * SVGA_REG_GUEST_DRIVER_ID register, to signal that they have finished.
	250	+ *
	251	+ * The SVGA_REG_GUEST_DRIVER_ID values are defined below by the
	252	+ * SVGARegGuestDriverId enum.
	253	+ *
	254	+ * The SVGA_REG_GUEST_DRIVER_VERSION fields are driver-specific,
	255	+ * but ideally should encode a monotonically increasing number that allows
	256	+ * the device to perform inequality checks against ranges of driver versions.
	257	+ */
	258	+ SVGA_REG_GUEST_DRIVER_ID = 61,
	259	+ SVGA_REG_GUEST_DRIVER_VERSION1 = 62,
	260	+ SVGA_REG_GUEST_DRIVER_VERSION2 = 63,
	261	+ SVGA_REG_GUEST_DRIVER_VERSION3 = 64,
	262	+ SVGA_REG_CURSOR_MOBID = 65,
	263	+ SVGA_REG_CURSOR_MAX_BYTE_SIZE = 66,
	264	+ SVGA_REG_CURSOR_MAX_DIMENSION = 67,
	265	+
	266	+ SVGA_REG_FIFO_CAPS = 68,
	267	+ SVGA_REG_FENCE = 69,
	268	+
	269	+ SVGA_REG_RESERVED1 = 70,
	270	+ SVGA_REG_RESERVED2 = 71,
	271	+ SVGA_REG_RESERVED3 = 72,
	272	+ SVGA_REG_RESERVED4 = 73,
	273	+ SVGA_REG_RESERVED5 = 74,
	274	+ SVGA_REG_SCREENDMA = 75,
	275	+
	276	+ /*
	277	+ * The maximum amount of guest-backed objects that the device can have
	278	+ * resident at a time. Guest-drivers should keep their working set size
	279	+ * below this limit for best performance.
	280	+ *
	281	+ * Note that this value is in kilobytes, and not bytes, because the actual
	282	+ * number of bytes might be larger than can fit in a 32-bit register.
	283	+ *
	284	+ * PLEASE USE A 64-BIT VALUE WHEN CONVERTING THIS INTO BYTES.
	285	+ * (See SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB).
	286	+ */
	287	+ SVGA_REG_GBOBJECT_MEM_SIZE_KB = 76,
	288	+
	289	+ SVGA_REG_TOP = 77, /* Must be 1 more than the last register */
222	290
223	291	SVGA_PALETTE_BASE = 1024, /* Base of SVGA color map */
224	292	/* Next 768 (== 2563) registers exist for colormap /
..	..	@@ -228,6 +296,20 @@
228	296	First 4 are reserved for VESA BIOS Extension; any remaining are for
229	297	the use of the current SVGA driver. */
230	298	};
	299	+
	300	+
	301	+/*
	302	+ * Values for SVGA_REG_GUEST_DRIVER_ID.
	303	+ */
	304	+typedef enum SVGARegGuestDriverId {
	305	+ SVGA_REG_GUEST_DRIVER_ID_UNKNOWN = 0,
	306	+ SVGA_REG_GUEST_DRIVER_ID_WDDM = 1,
	307	+ SVGA_REG_GUEST_DRIVER_ID_LINUX = 2,
	308	+ SVGA_REG_GUEST_DRIVER_ID_MAX,
	309	+
	310	+ SVGA_REG_GUEST_DRIVER_ID_SUBMIT = MAX_UINT32,
	311	+} SVGARegGuestDriverId;
	312	+
231	313
232	314	/*
233	315	* Guest memory regions (GMRs):
..	..	@@ -416,7 +498,6 @@
416	498	SVGA_CB_CONTEXT_0 = 0x0,
417	499	SVGA_CB_CONTEXT_1 = 0x1, /* Supported with SVGA_CAP_HP_CMD_QUEUE */
418	500	SVGA_CB_CONTEXT_MAX = 0x2,
419		- SVGA_CB_CONTEXT_HP_MAX = 0x2,
420	501	} SVGACBContext;
421	502
422	503
..	..	@@ -733,9 +814,6 @@
733	814	* and must not be reused. Those capabilities will never be reported
734	815	* by new versions of the SVGA device.
735	816	*
736		- * XXX: Add longer descriptions for each capability, including a list
737		- * of the new features that each capability provides.
738		- *
739	817	* SVGA_CAP_IRQMASK --
740	818	* Provides device interrupts. Adds device register SVGA_REG_IRQMASK
741	819	* to set interrupt mask and direct I/O port SVGA_IRQSTATUS_PORT to
..	..	@@ -842,17 +920,51 @@
842	920	* Allow the IntraSurfaceCopy command.
843	921	*
844	922	* SVGA_CAP2_DX2 --
845		- * Allow the DefineGBSurface_v3, WholeSurfaceCopy.
	923	+ * Allow the DefineGBSurface_v3, WholeSurfaceCopy, WriteZeroSurface, and
	924	+ * HintZeroSurface commands, and the SVGA_REG_GUEST_DRIVER_ID register.
	925	+ *
	926	+ * SVGA_CAP2_GB_MEMSIZE_2 --
	927	+ * Allow the SVGA_REG_GBOBJECT_MEM_SIZE_KB register.
	928	+ *
	929	+ * SVGA_CAP2_SCREENDMA_REG --
	930	+ * Allow the SVGA_REG_SCREENDMA register.
	931	+ *
	932	+ * SVGA_CAP2_OTABLE_PTDEPTH_2 --
	933	+ * Allow 2 level page tables for OTable commands.
	934	+ *
	935	+ * SVGA_CAP2_NON_MS_TO_MS_STRETCHBLT --
	936	+ * Allow a stretch blt from a non-multisampled surface to a multisampled
	937	+ * surface.
	938	+ *
	939	+ * SVGA_CAP2_CURSOR_MOB --
	940	+ * Allow the SVGA_REG_CURSOR_MOBID register.
	941	+ *
	942	+ * SVGA_CAP2_MSHINT --
	943	+ * Allow the SVGA_REG_MSHINT register.
	944	+ *
	945	+ * SVGA_CAP2_DX3 --
	946	+ * Allows the DefineGBSurface_v4 command.
	947	+ * Allows the DXDefineDepthStencilView_v2, DXDefineStreamOutputWithMob,
	948	+ * and DXBindStreamOutput commands if 3D is also available.
	949	+ * Allows the DXPredStagingCopy and DXStagingCopy commands if SM41
	950	+ * is also available.
846	951	*
847	952	* SVGA_CAP2_RESERVED --
848	953	* Reserve the last bit for extending the SVGA capabilities to some
849	954	* future mechanisms.
850	955	*/
851		-#define SVGA_CAP2_NONE 0x00000000
852		-#define SVGA_CAP2_GROW_OTABLE 0x00000001
853		-#define SVGA_CAP2_INTRA_SURFACE_COPY 0x00000002
854		-#define SVGA_CAP2_DX2 0x00000004
855		-#define SVGA_CAP2_RESERVED 0x80000000
	956	+#define SVGA_CAP2_NONE 0x00000000
	957	+#define SVGA_CAP2_GROW_OTABLE 0x00000001
	958	+#define SVGA_CAP2_INTRA_SURFACE_COPY 0x00000002
	959	+#define SVGA_CAP2_DX2 0x00000004
	960	+#define SVGA_CAP2_GB_MEMSIZE_2 0x00000008
	961	+#define SVGA_CAP2_SCREENDMA_REG 0x00000010
	962	+#define SVGA_CAP2_OTABLE_PTDEPTH_2 0x00000020
	963	+#define SVGA_CAP2_NON_MS_TO_MS_STRETCHBLT 0x00000040
	964	+#define SVGA_CAP2_CURSOR_MOB 0x00000080
	965	+#define SVGA_CAP2_MSHINT 0x00000100
	966	+#define SVGA_CAP2_DX3 0x00000400
	967	+#define SVGA_CAP2_RESERVED 0x80000000
856	968
857	969
858	970	/*
..	..	@@ -875,7 +987,9 @@
875	987	SVGABackdoorCapFifoCaps = 1,
876	988	SVGABackdoorCap3dHWVersion = 2,
877	989	SVGABackdoorCapDeviceCaps2 = 3,
878		- SVGABackdoorCapMax = 4,
	990	+ SVGABackdoorCapDevelCaps = 4,
	991	+ SVGABackdoorDevelRenderer = 5,
	992	+ SVGABackdoorCapMax = 6,
879	993	} SVGABackdoorCapType;
880	994
881	995
..	..	@@ -1055,103 +1169,80 @@
1055	1169	/*
1056	1170	* FIFO Synchronization Registers
1057	1171	*
1058		- * This explains the relationship between the various FIFO
1059		- * sync-related registers in IOSpace and in FIFO space.
1060		- *
1061	1172	* SVGA_REG_SYNC --
1062	1173	*
1063		- * The SYNC register can be used in two different ways by the guest:
	1174	+ * The SYNC register can be used by the guest driver to signal to the
	1175	+ * device that the guest driver is waiting for previously submitted
	1176	+ * commands to complete.
1064	1177	*
1065		- * 1. If the guest wishes to fully sync (drain) the FIFO,
1066		- * it will write once to SYNC then poll on the BUSY
1067		- * register. The FIFO is sync'ed once BUSY is zero.
	1178	+ * When the guest driver writes to the SYNC register, the device sets
	1179	+ * the BUSY register to TRUE, and starts processing the submitted commands
	1180	+ * (if it was not already doing so). When all previously submitted
	1181	+ * commands are finished and the device is idle again, it sets the BUSY
	1182	+ * register back to FALSE. (If the guest driver submits new commands
	1183	+ * after writing the SYNC register, the new commands are not guaranteed
	1184	+ * to have been procesesd.)
1068	1185	*
1069		- * 2. If the guest wants to asynchronously wake up the host,
1070		- * it will write once to SYNC without polling on BUSY.
1071		- * Ideally it will do this after some new commands have
1072		- * been placed in the FIFO, and after reading a zero
1073		- * from SVGA_FIFO_BUSY.
	1186	+ * When guest drivers are submitting commands using the FIFO, the device
	1187	+ * periodically polls to check for new FIFO commands when idle, which may
	1188	+ * introduce a delay in command processing. If the guest-driver wants
	1189	+ * the commands to be processed quickly (which it typically does), it
	1190	+ * should write SYNC after each batch of commands is committed to the
	1191	+ * FIFO to immediately wake up the device. For even better performance,
	1192	+ * the guest can use the SVGA_FIFO_BUSY register to avoid these extra
	1193	+ * SYNC writes if the device is already active, using the technique known
	1194	+ * as "Ringing the Doorbell" (described below). (Note that command
	1195	+ * buffer submission implicitly wakes up the device, and so doesn't
	1196	+ * suffer from this problem.)
1074	1197	*
1075		- * (1) is the original behaviour that SYNC was designed to
1076		- * support. Originally, a write to SYNC would implicitly
1077		- * trigger a read from BUSY. This causes us to synchronously
1078		- * process the FIFO.
1079		- *
1080		- * This behaviour has since been changed so that writing SYNC
1081		- * will not implicitly cause a read from BUSY. Instead, it
1082		- * makes a channel call which asynchronously wakes up the MKS
1083		- * thread.
1084		- *
1085		- * New guests can use this new behaviour to implement (2)
1086		- * efficiently. This lets guests get the host's attention
1087		- * without waiting for the MKS to poll, which gives us much
1088		- * better CPU utilization on SMP hosts and on UP hosts while
1089		- * we're blocked on the host GPU.
1090		- *
1091		- * Old guests shouldn't notice the behaviour change. SYNC was
1092		- * never guaranteed to process the entire FIFO, since it was
1093		- * bounded to a particular number of CPU cycles. Old guests will
1094		- * still loop on the BUSY register until the FIFO is empty.
1095		- *
1096		- * Writing to SYNC currently has the following side-effects:
1097		- *
1098		- * - Sets SVGA_REG_BUSY to TRUE (in the monitor)
1099		- * - Asynchronously wakes up the MKS thread for FIFO processing
1100		- * - The value written to SYNC is recorded as a "reason", for
1101		- * stats purposes.
1102		- *
1103		- * If SVGA_FIFO_BUSY is available, drivers are advised to only
1104		- * write to SYNC if SVGA_FIFO_BUSY is FALSE. Drivers should set
1105		- * SVGA_FIFO_BUSY to TRUE after writing to SYNC. The MKS will
1106		- * eventually set SVGA_FIFO_BUSY on its own, but this approach
1107		- * lets the driver avoid sending multiple asynchronous wakeup
1108		- * messages to the MKS thread.
	1198	+ * The SYNC register can also be used in combination with BUSY to
	1199	+ * synchronously ensure that all SVGA commands are processed (with both
	1200	+ * the FIFO and command-buffers). To do this, the guest driver should
	1201	+ * write to SYNC, and then loop reading BUSY until BUSY returns FALSE.
	1202	+ * This technique is known as a "Legacy Sync".
1109	1203	*
1110	1204	* SVGA_REG_BUSY --
1111	1205	*
1112	1206	* This register is set to TRUE when SVGA_REG_SYNC is written,
1113		- * and it reads as FALSE when the FIFO has been completely
1114		- * drained.
	1207	+ * and is set back to FALSE when the device has finished processing
	1208	+ * all commands and is idle again.
1115	1209	*
1116		- * Every read from this register causes us to synchronously
1117		- * process FIFO commands. There is no guarantee as to how many
1118		- * commands each read will process.
	1210	+ * Every read from the BUSY reigster will block for an undefined
	1211	+ * amount of time (normally until the device finishes some interesting
	1212	+ * work unit), or the device is idle.
1119	1213	*
1120		- * CPU time spent processing FIFO commands will be billed to
1121		- * the guest.
1122		- *
1123		- * New drivers should avoid using this register unless they
1124		- * need to guarantee that the FIFO is completely drained. It
1125		- * is overkill for performing a sync-to-fence. Older drivers
1126		- * will use this register for any type of synchronization.
	1214	+ * Guest drivers can also do a partial Legacy Sync to check for some
	1215	+ * particular condition, for instance by stopping early when a fence
	1216	+ * passes before BUSY has been set back to FALSE. This is particularly
	1217	+ * useful if the guest-driver knows that it is blocked waiting on the
	1218	+ * device, because it will yield CPU time back to the host.
1127	1219	*
1128	1220	* SVGA_FIFO_BUSY --
1129	1221	*
1130		- * This register is a fast way for the guest driver to check
1131		- * whether the FIFO is already being processed. It reads and
1132		- * writes at normal RAM speeds, with no monitor intervention.
	1222	+ * The SVGA_FIFO_BUSY register is a fast way for the guest driver to check
	1223	+ * whether the device is actively processing FIFO commands before writing
	1224	+ * the more expensive SYNC register.
1133	1225	*
1134		- * If this register reads as TRUE, the host is guaranteeing that
1135		- * any new commands written into the FIFO will be noticed before
1136		- * the MKS goes back to sleep.
	1226	+ * If this register reads as TRUE, the device is actively processing
	1227	+ * FIFO commands.
1137	1228	*
1138		- * If this register reads as FALSE, no such guarantee can be
1139		- * made.
	1229	+ * If this register reads as FALSE, the device may not be actively
	1230	+ * processing commands, and the guest driver should try
	1231	+ * "Ringing the Doorbell".
1140	1232	*
1141		- * The guest should use this register to quickly determine
1142		- * whether or not it needs to wake up the host. If the guest
1143		- * just wrote a command or group of commands that it would like
1144		- * the host to begin processing, it should:
	1233	+ * To Ring the Doorbell, the guest should:
1145	1234	*
1146		- * 1. Read SVGA_FIFO_BUSY. If it reads as TRUE, no further
1147		- * action is necessary.
	1235	+ * 1. Have already written their batch of commands into the FIFO.
	1236	+ * 2. Check if the SVGA_FIFO_BUSY register is available by reading
	1237	+ * SVGA_FIFO_MIN.
	1238	+ * 3. Read SVGA_FIFO_BUSY. If it reads as TRUE, the device is actively
	1239	+ * processing FIFO commands, and no further action is necessary.
	1240	+ * 4. If SVGA_FIFO_BUSY was FALSE, write TRUE to SVGA_REG_SYNC.
1148	1241	*
1149		- * 2. Write TRUE to SVGA_FIFO_BUSY. This informs future guest
1150		- * code that we've already sent a SYNC to the host and we
1151		- * don't need to send a duplicate.
1152		- *
1153		- * 3. Write a reason to SVGA_REG_SYNC. This will send an
1154		- * asynchronous wakeup to the MKS thread.
	1242	+ * For maximum performance, this procedure should be followed after
	1243	+ * every meaningful batch of commands has been written into the FIFO.
	1244	+ * (Normally when the underlying application signals it's finished a
	1245	+ * meaningful work unit by calling Flush.)
1155	1246	*/
1156	1247
1157	1248
..	..	@@ -1163,9 +1254,6 @@
1163	1254	* Pitch Lock -- Pitch lock register is supported
1164	1255	* Video -- SVGA Video overlay units are supported
1165	1256	* Escape -- Escape command is supported
1166		- *
1167		- * XXX: Add longer descriptions for each capability, including a list
1168		- * of the new features that each capability provides.
1169	1257	*
1170	1258	* SVGA_FIFO_CAP_SCREEN_OBJECT --
1171	1259	*
..	..	@@ -1277,6 +1365,15 @@
1277	1365
1278	1366	#define SVGA_FIFO_RESERVED_UNKNOWN 0xffffffff
1279	1367
	1368	+
	1369	+/*
	1370	+ * ScreenDMA Register Values
	1371	+ */
	1372	+
	1373	+#define SVGA_SCREENDMA_REG_UNDEFINED 0
	1374	+#define SVGA_SCREENDMA_REG_NOT_PRESENT 1
	1375	+#define SVGA_SCREENDMA_REG_PRESENT 2
	1376	+#define SVGA_SCREENDMA_REG_MAX 3
1280	1377
1281	1378	/*
1282	1379	* Video overlay support
..	..	@@ -1662,6 +1759,80 @@
1662	1759	}
1663	1760	#include "vmware_pack_end.h"
1664	1761	SVGAFifoCmdDefineAlphaCursor;
	1762	+
	1763	+
	1764	+/*
	1765	+ * Provide a new large cursor image, as an AND/XOR mask.
	1766	+ *
	1767	+ * Should only be used for CursorMob functionality
	1768	+ */
	1769	+
	1770	+typedef
	1771	+#include "vmware_pack_begin.h"
	1772	+struct {
	1773	+ uint32 hotspotX;
	1774	+ uint32 hotspotY;
	1775	+ uint32 width;
	1776	+ uint32 height;
	1777	+ uint32 andMaskDepth;
	1778	+ uint32 xorMaskDepth;
	1779	+ /*
	1780	+ * Followed by scanline data for AND mask, then XOR mask.
	1781	+ * Each scanline is padded to a 32-bit boundary.
	1782	+ */
	1783	+}
	1784	+#include "vmware_pack_end.h"
	1785	+SVGAGBColorCursorHeader;
	1786	+
	1787	+
	1788	+/*
	1789	+ * Provide a new large cursor image, in 32-bit BGRA format.
	1790	+ *
	1791	+ * Should only be used for CursorMob functionality
	1792	+ */
	1793	+
	1794	+typedef
	1795	+#include "vmware_pack_begin.h"
	1796	+struct {
	1797	+ uint32 hotspotX;
	1798	+ uint32 hotspotY;
	1799	+ uint32 width;
	1800	+ uint32 height;
	1801	+ /* Followed by scanline data */
	1802	+}
	1803	+#include "vmware_pack_end.h"
	1804	+SVGAGBAlphaCursorHeader;
	1805	+
	1806	+ /*
	1807	+ * Define the SVGA guest backed cursor types
	1808	+ */
	1809	+
	1810	+typedef enum {
	1811	+ SVGA_COLOR_CURSOR = 0,
	1812	+ SVGA_ALPHA_CURSOR = 1,
	1813	+} SVGAGBCursorType;
	1814	+
	1815	+/*
	1816	+ * Provide a new large cursor image.
	1817	+ *
	1818	+ * Should only be used for CursorMob functionality
	1819	+ */
	1820	+
	1821	+typedef
	1822	+#include "vmware_pack_begin.h"
	1823	+struct {
	1824	+ SVGAGBCursorType type;
	1825	+ union {
	1826	+ SVGAGBColorCursorHeader colorHeader;
	1827	+ SVGAGBAlphaCursorHeader alphaHeader;
	1828	+ } header;
	1829	+ uint32 sizeInBytes;
	1830	+ /*
	1831	+ * Followed by the cursor data
	1832	+ */
	1833	+}
	1834	+#include "vmware_pack_end.h"
	1835	+SVGAGBCursorHeader;
1665	1836
1666	1837
1667	1838	/*
..	..	@@ -2061,9 +2232,12 @@
2061	2232	#define SVGA_VRAM_MAX_SIZE (128 * 1024 * 1024)
2062	2233	#define SVGA_MEMORY_SIZE_MAX (1024 * 1024 * 1024)
2063	2234	#define SVGA_FIFO_SIZE_MAX (2 * 1024 * 1024)
2064		-#define SVGA_GRAPHICS_MEMORY_KB_MIN (32 * 1024)
2065		-#define SVGA_GRAPHICS_MEMORY_KB_MAX (2 * 1024 * 1024)
2066		-#define SVGA_GRAPHICS_MEMORY_KB_DEFAULT (256 * 1024)
	2235	+#define SVGA_GRAPHICS_MEMORY_KB_MIN (32 * 1024)
	2236	+#define SVGA_GRAPHICS_MEMORY_KB_MAX_2GB (2 * 1024 * 1024)
	2237	+#define SVGA_GRAPHICS_MEMORY_KB_MAX_3GB (3 * 1024 * 1024)
	2238	+#define SVGA_GRAPHICS_MEMORY_KB_MAX_4GB (4 * 1024 * 1024)
	2239	+#define SVGA_GRAPHICS_MEMORY_KB_MAX_8GB (8 * 1024 * 1024)
	2240	+#define SVGA_GRAPHICS_MEMORY_KB_DEFAULT (256 * 1024)
2067	2241
2068	2242	#define SVGA_VRAM_SIZE_W2K (64 * 1024 * 1024) /* 64 MB */
2069	2243
..	..	@@ -2086,4 +2260,6 @@
2086	2260	#define SVGA_FIFO_SIZE_GBOBJECTS (256 * 1024)
2087	2261	#define SVGA_VRAM_SIZE_GBOBJECTS (4 * 1024 * 1024)
2088	2262
	2263	+#define SVGA_PCI_REGS_PAGES (1)
	2264	+
2089	2265	#endif