~ljy/RK356X_SDK_RELEASE.git

..	..	@@ -1,3 +1,4 @@
	1	+// SPDX-License-Identifier: GPL-2.0-or-later
1	2	/*
2	3	* Rockchip SoC DP (Display Port) interface driver.
3	4	*
..	..	@@ -5,11 +6,6 @@
5	6	* Author: Andy Yan <andy.yan@rock-chips.com>
6	7	* Yakir Yang <ykk@rock-chips.com>
7	8	* Jeff Chen <jeff.chen@rock-chips.com>
8		- *
9		- * This program is free software; you can redistribute it and/or modify it
10		- * under the terms of the GNU General Public License as published by the
11		- * Free Software Foundation; either version 2 of the License, or (at your
12		- * option) any later version.
13	9	*/
14	10
15	11	#include <linux/component.h>
..	..	@@ -17,86 +13,118 @@
17	13	#include <linux/of_device.h>
18	14	#include <linux/of_graph.h>
19	15	#include <linux/regmap.h>
20		-#include <linux/regulator/consumer.h>
21	16	#include <linux/reset.h>
22	17	#include <linux/clk.h>
23		-
24		-#include <drm/drmP.h>
25		-#include <drm/drm_crtc_helper.h>
26		-#include <drm/drm_dp_helper.h>
27		-#include <drm/drm_of.h>
28		-#include <drm/drm_panel.h>
29	18
30	19	#include <uapi/linux/videodev2.h>
31	20	#include <video/of_videomode.h>
32	21	#include <video/videomode.h>
33	22
	23	+#include <drm/drm_atomic.h>
	24	+#include <drm/drm_atomic_helper.h>
34	25	#include <drm/bridge/analogix_dp.h>
35		-
36		-#include "../bridge/analogix/analogix_dp_core.h"
	26	+#include <drm/drm_dp_helper.h>
	27	+#include <drm/drm_of.h>
	28	+#include <drm/drm_panel.h>
	29	+#include <drm/drm_probe_helper.h>
	30	+#include <drm/drm_simple_kms_helper.h>
37	31
38	32	#include "rockchip_drm_drv.h"
39		-#include "rockchip_drm_psr.h"
40	33	#include "rockchip_drm_vop.h"
41		-
42		-#define RK3288_GRF_SOC_CON6 0x25c
43		-#define RK3288_EDP_LCDC_SEL BIT(5)
44		-#define RK3399_GRF_SOC_CON20 0x6250
45		-#define RK3399_EDP_LCDC_SEL BIT(5)
46		-
47		-#define HIWORD_UPDATE(val, mask) (val \| (mask) << 16)
48	34
49	35	#define PSR_WAIT_LINE_FLAG_TIMEOUT_MS 100
50	36
51	37	#define to_dp(nm) container_of(nm, struct rockchip_dp_device, nm)
52	38
	39	+#define GRF_REG_FIELD(_reg, _lsb, _msb) { \
	40	+ .reg = _reg, \
	41	+ .lsb = _lsb, \
	42	+ .msb = _msb, \
	43	+ .valid = true, \
	44	+ }
	45	+
	46	+struct rockchip_grf_reg_field {
	47	+ unsigned int reg;
	48	+ unsigned int lsb;
	49	+ unsigned int msb;
	50	+ bool valid;
	51	+};
	52	+
53	53	/**
54	54	* struct rockchip_dp_chip_data - splite the grf setting of kind of chips
55		- * @lcdsel_grf_reg: grf register offset of lcdc select
56		- * @lcdsel_big: reg value of selecting vop big for eDP
57		- * @lcdsel_lit: reg value of selecting vop little for eDP
	55	+ * @lcdc_sel: grf register field of lcdc_sel
	56	+ * @spdif_sel: grf register field of spdif_sel
	57	+ * @i2s_sel: grf register field of i2s_sel
	58	+ * @edp_mode: grf register field of edp_mode
58	59	* @chip_type: specific chip type
59	60	* @ssc: check if SSC is supported by source
60	61	* @audio: check if audio is supported by source
	62	+ * @split_mode: check if split mode is supported
61	63	*/
62	64	struct rockchip_dp_chip_data {
63		- u32 lcdsel_grf_reg;
64		- u32 lcdsel_big;
65		- u32 lcdsel_lit;
	65	+ const struct rockchip_grf_reg_field lcdc_sel;
	66	+ const struct rockchip_grf_reg_field spdif_sel;
	67	+ const struct rockchip_grf_reg_field i2s_sel;
	68	+ const struct rockchip_grf_reg_field edp_mode;
66	69	u32 chip_type;
67	70	bool ssc;
68	71	bool audio;
	72	+ bool split_mode;
69	73	};
70	74
71	75	struct rockchip_dp_device {
72	76	struct drm_device *drm_dev;
73	77	struct device *dev;
74	78	struct drm_encoder encoder;
75		- struct drm_bridge *bridge;
76	79	struct drm_display_mode mode;
77	80
78		- int num_clks;
79		- u8 id;
80		- struct clk_bulk_data *clks;
81	81	struct regmap *grf;
82	82	struct reset_control *rst;
83	83	struct reset_control *apb_reset;
84		- struct regulator *vcc_supply;
85		- struct regulator *vccio_supply;
86	84
87	85	struct platform_device *audio_pdev;
88	86	const struct rockchip_dp_chip_data *data;
	87	+ int id;
89	88
90	89	struct analogix_dp_device *adp;
91	90	struct analogix_dp_plat_data plat_data;
92	91	struct rockchip_drm_sub_dev sub_dev;
	92	+
	93	+ unsigned int min_refresh_rate;
	94	+ unsigned int max_refresh_rate;
93	95	};
	96	+
	97	+static int rockchip_grf_write(struct regmap *grf, unsigned int reg,
	98	+ unsigned int mask, unsigned int val)
	99	+{
	100	+ return regmap_write(grf, reg, (mask << 16) \| (val & mask));
	101	+}
	102	+
	103	+static int rockchip_grf_field_write(struct regmap *grf,
	104	+ const struct rockchip_grf_reg_field *field,
	105	+ unsigned int val)
	106	+{
	107	+ unsigned int mask;
	108	+
	109	+ if (!field->valid)
	110	+ return 0;
	111	+
	112	+ mask = GENMASK(field->msb, field->lsb);
	113	+ val <<= field->lsb;
	114	+
	115	+ return rockchip_grf_write(grf, field->reg, mask, val);
	116	+}
94	117
95	118	static int rockchip_dp_audio_hw_params(struct device dev, void data,
96	119	struct hdmi_codec_daifmt *daifmt,
97	120	struct hdmi_codec_params *params)
98	121	{
99	122	struct rockchip_dp_device *dp = dev_get_drvdata(dev);
	123	+
	124	+ rockchip_grf_field_write(dp->grf, &dp->data->spdif_sel,
	125	+ daifmt->fmt == HDMI_SPDIF);
	126	+ rockchip_grf_field_write(dp->grf, &dp->data->i2s_sel,
	127	+ daifmt->fmt == HDMI_I2S);
100	128
101	129	return analogix_dp_audio_hw_params(dp->adp, daifmt, params);
102	130	}
..	..	@@ -106,6 +134,9 @@
106	134	struct rockchip_dp_device *dp = dev_get_drvdata(dev);
107	135
108	136	analogix_dp_audio_shutdown(dp->adp);
	137	+
	138	+ rockchip_grf_field_write(dp->grf, &dp->data->spdif_sel, 0);
	139	+ rockchip_grf_field_write(dp->grf, &dp->data->i2s_sel, 0);
109	140	}
110	141
111	142	static int rockchip_dp_audio_startup(struct device dev, void data)
..	..	@@ -130,27 +161,24 @@
130	161	.get_eld = rockchip_dp_audio_get_eld,
131	162	};
132	163
133		-static int analogix_dp_psr_set(struct drm_encoder *encoder, bool enabled)
	164	+static int rockchip_dp_match_by_id(struct device dev, const void data)
134	165	{
135		- struct rockchip_dp_device *dp = to_dp(encoder);
136		- int ret;
	166	+ struct rockchip_dp_device *dp = dev_get_drvdata(dev);
	167	+ const unsigned int *id = data;
137	168
138		- if (!analogix_dp_psr_enabled(dp->adp))
139		- return 0;
	169	+ return dp->id == *id;
	170	+}
140	171
141		- DRM_DEV_DEBUG(dp->dev, "%s PSR...\n", enabled ? "Entry" : "Exit");
	172	+static struct rockchip_dp_device *
	173	+rockchip_dp_find_by_id(struct device_driver *drv, unsigned int id)
	174	+{
	175	+ struct device *dev;
142	176
143		- ret = rockchip_drm_wait_vact_end(dp->encoder.crtc,
144		- PSR_WAIT_LINE_FLAG_TIMEOUT_MS);
145		- if (ret) {
146		- DRM_DEV_ERROR(dp->dev, "line flag interrupt did not arrive\n");
147		- return -ETIMEDOUT;
148		- }
	177	+ dev = driver_find_device(drv, NULL, &id, rockchip_dp_match_by_id);
	178	+ if (!dev)
	179	+ return NULL;
149	180
150		- if (enabled)
151		- return analogix_dp_enable_psr(dp->adp);
152		- else
153		- return analogix_dp_disable_psr(dp->adp);
	181	+ return dev_get_drvdata(dev);
154	182	}
155	183
156	184	static int rockchip_dp_pre_init(struct rockchip_dp_device *dp)
..	..	@@ -171,50 +199,20 @@
171	199	struct rockchip_dp_device *dp = to_dp(plat_data);
172	200	int ret;
173	201
174		- if (dp->vcc_supply) {
175		- ret = regulator_enable(dp->vcc_supply);
176		- if (ret)
177		- dev_warn(dp->dev, "failed to enable vcc: %d\n", ret);
178		- }
179		-
180		- if (dp->vccio_supply) {
181		- ret = regulator_enable(dp->vccio_supply);
182		- if (ret)
183		- dev_warn(dp->dev, "failed to enable vccio: %d\n", ret);
184		- }
185		-
186	202	ret = rockchip_dp_pre_init(dp);
187	203	if (ret < 0) {
188	204	DRM_DEV_ERROR(dp->dev, "failed to dp pre init %d\n", ret);
189	205	return ret;
190	206	}
191	207
192		- return ret;
193		-}
194		-
195		-static int rockchip_dp_poweron_end(struct analogix_dp_plat_data *plat_data)
196		-{
197		- struct rockchip_dp_device *dp = to_dp(plat_data);
198		-
199		- return rockchip_drm_psr_inhibit_put(&dp->encoder);
	208	+ return rockchip_grf_field_write(dp->grf, &dp->data->edp_mode, 1);
200	209	}
201	210
202	211	static int rockchip_dp_powerdown(struct analogix_dp_plat_data *plat_data)
203	212	{
204	213	struct rockchip_dp_device *dp = to_dp(plat_data);
205		- int ret;
206	214
207		- ret = rockchip_drm_psr_inhibit_get(&dp->encoder);
208		- if (ret != 0)
209		- return ret;
210		-
211		- if (dp->vccio_supply)
212		- regulator_disable(dp->vccio_supply);
213		-
214		- if (dp->vcc_supply)
215		- regulator_disable(dp->vcc_supply);
216		-
217		- return 0;
	215	+ return rockchip_grf_field_write(dp->grf, &dp->data->edp_mode, 0);
218	216	}
219	217
220	218	static int rockchip_dp_get_modes(struct analogix_dp_plat_data *plat_data,
..	..	@@ -223,7 +221,6 @@
223	221	struct drm_display_info *di = &connector->display_info;
224	222	/* VOP couldn't output YUV video format for eDP rightly */
225	223	u32 mask = DRM_COLOR_FORMAT_YCRCB444 \| DRM_COLOR_FORMAT_YCRCB422;
226		- int ret = 0;
227	224
228	225	if ((di->color_formats & mask)) {
229	226	DRM_DEBUG_KMS("Swapping display color format from YUV to RGB\n");
..	..	@@ -232,12 +229,52 @@
232	229	di->bpc = 8;
233	230	}
234	231
235		- if (list_empty(&connector->probed_modes) && !plat_data->panel) {
236		- ret = rockchip_drm_add_modes_noedid(connector);
237		- DRM_ERROR("analogix dp get edid mode failed, use default mode\n");
	232	+ return 0;
	233	+}
	234	+
	235	+static int rockchip_dp_loader_protect(struct drm_encoder *encoder, bool on)
	236	+{
	237	+ struct rockchip_dp_device *dp = to_dp(encoder);
	238	+ struct analogix_dp_plat_data *plat_data = &dp->plat_data;
	239	+ struct rockchip_dp_device *secondary = NULL;
	240	+ int ret;
	241	+
	242	+ if (plat_data->right) {
	243	+ secondary = rockchip_dp_find_by_id(dp->dev->driver, !dp->id);
	244	+
	245	+ ret = rockchip_dp_loader_protect(&secondary->encoder, on);
	246	+ if (ret)
	247	+ return ret;
238	248	}
239	249
240		- return ret;
	250	+ if (!on)
	251	+ return 0;
	252	+
	253	+ if (plat_data->panel)
	254	+ panel_simple_loader_protect(plat_data->panel);
	255	+
	256	+ ret = analogix_dp_loader_protect(dp->adp);
	257	+ if (ret) {
	258	+ if (secondary)
	259	+ analogix_dp_disable(secondary->adp);
	260	+ return ret;
	261	+ }
	262	+
	263	+ return 0;
	264	+}
	265	+
	266	+static bool rockchip_dp_skip_connector(struct drm_bridge *bridge)
	267	+{
	268	+ if (!bridge)
	269	+ return false;
	270	+
	271	+ if (of_device_is_compatible(bridge->of_node, "dp-connector"))
	272	+ return false;
	273	+
	274	+ if (bridge->ops & DRM_BRIDGE_OP_MODES)
	275	+ return false;
	276	+
	277	+ return true;
241	278	}
242	279
243	280	static int rockchip_dp_bridge_attach(struct analogix_dp_plat_data *plat_data,
..	..	@@ -245,17 +282,53 @@
245	282	struct drm_connector *connector)
246	283	{
247	284	struct rockchip_dp_device *dp = to_dp(plat_data);
248		- int ret;
	285	+ struct rockchip_drm_sub_dev *sdev = &dp->sub_dev;
249	286
250		- if (dp->bridge) {
251		- ret = drm_bridge_attach(&dp->encoder, dp->bridge, bridge);
252		- if (ret) {
253		- DRM_ERROR("Failed to attach bridge to drm: %d\n", ret);
254		- return ret;
255		- }
	287	+ if (!connector) {
	288	+ struct list_head *connector_list =
	289	+ &bridge->dev->mode_config.connector_list;
	290	+
	291	+ list_for_each_entry(connector, connector_list, head)
	292	+ if (drm_connector_has_possible_encoder(connector,
	293	+ bridge->encoder))
	294	+ break;
	295	+ }
	296	+
	297	+ if (connector) {
	298	+ sdev->connector = connector;
	299	+ sdev->of_node = dp->dev->of_node;
	300	+ sdev->loader_protect = rockchip_dp_loader_protect;
	301	+ rockchip_drm_register_sub_dev(sdev);
256	302	}
257	303
258	304	return 0;
	305	+}
	306	+
	307	+static void rockchip_dp_bridge_detach(struct analogix_dp_plat_data *plat_data,
	308	+ struct drm_bridge *bridge)
	309	+{
	310	+ struct rockchip_dp_device *dp = to_dp(plat_data);
	311	+ struct rockchip_drm_sub_dev *sdev = &dp->sub_dev;
	312	+
	313	+ if (sdev->connector)
	314	+ rockchip_drm_unregister_sub_dev(sdev);
	315	+}
	316	+
	317	+static enum drm_mode_status
	318	+rockchip_dp_drm_encoder_mode_valid(struct drm_encoder *encoder,
	319	+ const struct drm_display_mode *mode)
	320	+{
	321	+ struct rockchip_dp_device *dp = to_dp(encoder);
	322	+ struct videomode vm;
	323	+
	324	+ drm_display_mode_to_videomode(mode, &vm);
	325	+
	326	+ if (!vm.hfront_porch \|\| !vm.hback_porch \|\| !vm.vfront_porch \|\| !vm.vback_porch) {
	327	+ DRM_DEV_ERROR(dp->dev, "front porch or back porch can not be 0\n");
	328	+ return MODE_BAD;
	329	+ }
	330	+
	331	+ return MODE_OK;
259	332	}
260	333
261	334	static bool
..	..	@@ -274,37 +347,79 @@
274	347	/* do nothing */
275	348	}
276	349
277		-static void rockchip_dp_drm_encoder_enable(struct drm_encoder *encoder)
	350	+static
	351	+struct drm_crtc rockchip_dp_drm_get_new_crtc(struct drm_encoder encoder,
	352	+ struct drm_atomic_state *state)
	353	+{
	354	+ struct drm_connector *connector;
	355	+ struct drm_connector_state *conn_state;
	356	+
	357	+ connector = drm_atomic_get_new_connector_for_encoder(state, encoder);
	358	+ if (!connector)
	359	+ return NULL;
	360	+
	361	+ conn_state = drm_atomic_get_new_connector_state(state, connector);
	362	+ if (!conn_state)
	363	+ return NULL;
	364	+
	365	+ return conn_state->crtc;
	366	+}
	367	+
	368	+static void rockchip_dp_drm_encoder_enable(struct drm_encoder *encoder,
	369	+ struct drm_atomic_state *state)
278	370	{
279	371	struct rockchip_dp_device *dp = to_dp(encoder);
	372	+ struct drm_crtc *crtc;
	373	+ struct drm_crtc_state *old_crtc_state;
280	374	int ret;
281		- u32 val;
282	375
283		- if (!dp->data->lcdsel_grf_reg)
	376	+ crtc = rockchip_dp_drm_get_new_crtc(encoder, state);
	377	+ if (!crtc)
	378	+ return;
	379	+
	380	+ old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc);
	381	+ /* Coming back from self refresh, nothing to do */
	382	+ if (old_crtc_state && old_crtc_state->self_refresh_active)
284	383	return;
285	384
286	385	ret = drm_of_encoder_active_endpoint_id(dp->dev->of_node, encoder);
287	386	if (ret < 0)
288	387	return;
289	388
290		- if (ret)
291		- val = dp->data->lcdsel_lit;
292		- else
293		- val = dp->data->lcdsel_big;
294		-
295	389	DRM_DEV_DEBUG(dp->dev, "vop %s output to dp\n", (ret) ? "LIT" : "BIG");
296	390
297		- ret = regmap_write(dp->grf, dp->data->lcdsel_grf_reg, val);
	391	+ ret = rockchip_grf_field_write(dp->grf, &dp->data->lcdc_sel, ret);
298	392	if (ret != 0)
299	393	DRM_DEV_ERROR(dp->dev, "Could not write to GRF: %d\n", ret);
300	394	}
301	395
302		-static void rockchip_dp_drm_encoder_disable(struct drm_encoder *encoder)
	396	+static void rockchip_dp_drm_encoder_disable(struct drm_encoder *encoder,
	397	+ struct drm_atomic_state *state)
303	398	{
304		- struct drm_crtc *crtc = encoder->crtc;
305		- struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc->state);
	399	+ struct rockchip_dp_device *dp = to_dp(encoder);
	400	+ struct drm_crtc *crtc;
	401	+ struct drm_crtc *old_crtc = encoder->crtc;
	402	+ struct drm_crtc_state *new_crtc_state = NULL;
	403	+ struct rockchip_crtc_state *s = to_rockchip_crtc_state(old_crtc->state);
	404	+ int ret;
306	405
307		- s->output_if &= ~VOP_OUTPUT_IF_eDP0;
	406	+ if (dp->plat_data.split_mode)
	407	+ s->output_if &= ~(VOP_OUTPUT_IF_eDP1 \| VOP_OUTPUT_IF_eDP0);
	408	+ else
	409	+ s->output_if &= ~(dp->id ? VOP_OUTPUT_IF_eDP1 : VOP_OUTPUT_IF_eDP0);
	410	+ crtc = rockchip_dp_drm_get_new_crtc(encoder, state);
	411	+ /* No crtc means we're doing a full shutdown */
	412	+ if (!crtc)
	413	+ return;
	414	+
	415	+ new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
	416	+ /* If we're not entering self-refresh, no need to wait for vact */
	417	+ if (!new_crtc_state \|\| !new_crtc_state->self_refresh_active)
	418	+ return;
	419	+
	420	+ ret = rockchip_drm_wait_vact_end(crtc, PSR_WAIT_LINE_FLAG_TIMEOUT_MS);
	421	+ if (ret)
	422	+ DRM_DEV_ERROR(dp->dev, "line flag irq timed out\n");
308	423	}
309	424
310	425	static int
..	..	@@ -312,8 +427,15 @@
312	427	struct drm_crtc_state *crtc_state,
313	428	struct drm_connector_state *conn_state)
314	429	{
	430	+ struct rockchip_dp_device *dp = to_dp(encoder);
315	431	struct rockchip_crtc_state *s = to_rockchip_crtc_state(crtc_state);
316	432	struct drm_display_info *di = &conn_state->connector->display_info;
	433	+ int refresh_rate;
	434	+
	435	+ if (di->num_bus_formats)
	436	+ s->bus_format = di->bus_formats[0];
	437	+ else
	438	+ s->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
317	439
318	440	/*
319	441	* The hardware IC designed that VOP must output the RGB10 video
..	..	@@ -325,98 +447,72 @@
325	447
326	448	s->output_mode = ROCKCHIP_OUT_MODE_AAAA;
327	449	s->output_type = DRM_MODE_CONNECTOR_eDP;
328		- s->output_if \|= VOP_OUTPUT_IF_eDP0;
	450	+ if (dp->plat_data.split_mode) {
	451	+ s->output_flags \|= ROCKCHIP_OUTPUT_DUAL_CHANNEL_LEFT_RIGHT_MODE;
	452	+ s->output_flags \|= dp->id ? ROCKCHIP_OUTPUT_DATA_SWAP : 0;
	453	+ s->output_if \|= VOP_OUTPUT_IF_eDP0 \| VOP_OUTPUT_IF_eDP1;
	454	+ } else {
	455	+ s->output_if \|= dp->id ? VOP_OUTPUT_IF_eDP1 : VOP_OUTPUT_IF_eDP0;
	456	+ }
	457	+
	458	+ if (dp->plat_data.dual_connector_split) {
	459	+ s->output_flags \|= ROCKCHIP_OUTPUT_DUAL_CONNECTOR_SPLIT_MODE;
	460	+
	461	+ if (dp->plat_data.left_display)
	462	+ s->output_if_left_panel \|= dp->id ?
	463	+ VOP_OUTPUT_IF_eDP1 :
	464	+ VOP_OUTPUT_IF_eDP0;
	465	+ }
	466	+
329	467	s->output_bpc = di->bpc;
330		- if (di->num_bus_formats)
331		- s->bus_format = di->bus_formats[0];
332		- else
333		- s->bus_format = MEDIA_BUS_FMT_RGB888_1X24;
334	468	s->bus_flags = di->bus_flags;
335	469	s->tv_state = &conn_state->tv;
336		- s->eotf = TRADITIONAL_GAMMA_SDR;
	470	+ s->eotf = HDMI_EOTF_TRADITIONAL_GAMMA_SDR;
337	471	s->color_space = V4L2_COLORSPACE_DEFAULT;
	472	+ /**
	473	+ * It's priority to user rate range define in dtsi.
	474	+ */
	475	+ if (dp->max_refresh_rate && dp->min_refresh_rate) {
	476	+ s->max_refresh_rate = dp->max_refresh_rate;
	477	+ s->min_refresh_rate = dp->min_refresh_rate;
	478	+ } else {
	479	+ s->max_refresh_rate = di->monitor_range.max_vfreq;
	480	+ s->min_refresh_rate = di->monitor_range.min_vfreq;
	481	+ }
338	482
339		- return 0;
340		-}
341		-
342		-static int rockchip_dp_drm_encoder_loader_protect(struct drm_encoder *encoder,
343		- bool on)
344		-{
345		- struct rockchip_dp_device *dp = to_dp(encoder);
346		- int ret;
347		-
348		- if (on) {
349		- if (dp->vcc_supply) {
350		- ret = regulator_enable(dp->vcc_supply);
351		- if (ret)
352		- dev_warn(dp->dev,
353		- "failed to enable vcc: %d\n", ret);
354		- }
355		-
356		- if (dp->vccio_supply) {
357		- ret = regulator_enable(dp->vccio_supply);
358		- if (ret)
359		- dev_warn(dp->dev,
360		- "failed to enable vccio: %d\n", ret);
361		- }
362		-
363		- rockchip_drm_psr_inhibit_put(&dp->encoder);
	483	+ /**
	484	+ * Timing exposed in DisplayID or legacy EDID is usually optimized
	485	+ * for bandwidth by using minimum horizontal and vertical blank. If
	486	+ * timing beyond the Adaptive-Sync range, it should not enable the
	487	+ * Ignore MSA option in this timing. If the refresh rate of the
	488	+ * timing is with the Adaptive-Sync range, this timing should support
	489	+ * the Adaptive-Sync from the timing's refresh rate to minimum
	490	+ * support range.
	491	+ */
	492	+ refresh_rate = drm_mode_vrefresh(&crtc_state->adjusted_mode);
	493	+ if (refresh_rate > s->max_refresh_rate \|\| refresh_rate < s->min_refresh_rate) {
	494	+ s->max_refresh_rate = 0;
	495	+ s->min_refresh_rate = 0;
	496	+ } else if (refresh_rate < s->max_refresh_rate) {
	497	+ s->max_refresh_rate = refresh_rate;
364	498	}
365	499
366	500	return 0;
367	501	}
368		-
369		-static int rockchip_dp_get_property(struct drm_connector *connector,
370		- const struct drm_connector_state *state,
371		- struct drm_property *property,
372		- u64 *val,
373		- struct analogix_dp_plat_data *data)
374		-{
375		- struct drm_encoder *encoder = data->encoder;
376		- struct rockchip_dp_device *dp = to_dp(encoder);
377		- struct rockchip_drm_private *private = connector->dev->dev_private;
378		-
379		- if (property == private->connector_id_prop) {
380		- *val = dp->id;
381		- return 0;
382		- }
383		-
384		- DRM_ERROR("failed to get rockchip analogic dp property\n");
385		- return -EINVAL;
386		-}
387		-
388		-static int rockchip_dp_attach_properties(struct drm_connector *connector)
389		-{
390		- struct rockchip_drm_private *private = connector->dev->dev_private;
391		-
392		- drm_object_attach_property(&connector->base, private->connector_id_prop, 0);
393		-
394		- return 0;
395		-}
396		-
397		-static const struct analogix_dp_property_ops rockchip_dp_encoder_property_ops = {
398		- .get_property = rockchip_dp_get_property,
399		- .attach_properties = rockchip_dp_attach_properties,
400		-};
401	502
402	503	static struct drm_encoder_helper_funcs rockchip_dp_encoder_helper_funcs = {
	504	+ .mode_valid = rockchip_dp_drm_encoder_mode_valid,
403	505	.mode_fixup = rockchip_dp_drm_encoder_mode_fixup,
404	506	.mode_set = rockchip_dp_drm_encoder_mode_set,
405		- .enable = rockchip_dp_drm_encoder_enable,
406		- .disable = rockchip_dp_drm_encoder_disable,
	507	+ .atomic_enable = rockchip_dp_drm_encoder_enable,
	508	+ .atomic_disable = rockchip_dp_drm_encoder_disable,
407	509	.atomic_check = rockchip_dp_drm_encoder_atomic_check,
408		- .loader_protect = rockchip_dp_drm_encoder_loader_protect,
409		-};
410		-
411		-static struct drm_encoder_funcs rockchip_dp_encoder_funcs = {
412		- .destroy = drm_encoder_cleanup,
413	510	};
414	511
415	512	static int rockchip_dp_of_probe(struct rockchip_dp_device *dp)
416	513	{
417	514	struct device *dev = dp->dev;
418	515	struct device_node *np = dev->of_node;
419		- int ret = 0;
420	516
421	517	if (of_property_read_bool(np, "rockchip,grf")) {
422	518	dp->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
..	..	@@ -425,14 +521,6 @@
425	521	return PTR_ERR(dp->grf);
426	522	}
427	523	}
428		-
429		- ret = devm_clk_bulk_get_all(dev, &dp->clks);
430		- if (ret < 0) {
431		- DRM_DEV_ERROR(dev, "failed to get clocks %d\n", ret);
432		- return ret;
433		- }
434		-
435		- dp->num_clks = ret;
436	524
437	525	dp->rst = devm_reset_control_get(dev, "dp");
438	526	if (IS_ERR(dp->rst)) {
..	..	@@ -446,29 +534,6 @@
446	534	return PTR_ERR(dp->apb_reset);
447	535	}
448	536
449		- dp->vcc_supply = devm_regulator_get_optional(dev, "vcc");
450		- if (IS_ERR(dp->vcc_supply)) {
451		- if (PTR_ERR(dp->vcc_supply) != -ENODEV) {
452		- ret = PTR_ERR(dp->vcc_supply);
453		- dev_err(dev, "failed to get vcc regulator: %d\n", ret);
454		- return ret;
455		- }
456		-
457		- dp->vcc_supply = NULL;
458		- }
459		-
460		- dp->vccio_supply = devm_regulator_get_optional(dev, "vccio");
461		- if (IS_ERR(dp->vccio_supply)) {
462		- if (PTR_ERR(dp->vccio_supply) != -ENODEV) {
463		- ret = PTR_ERR(dp->vccio_supply);
464		- dev_err(dev, "failed to get vccio regulator: %d\n",
465		- ret);
466		- return ret;
467		- }
468		-
469		- dp->vccio_supply = NULL;
470		- }
471		-
472	537	return 0;
473	538	}
474	539
..	..	@@ -479,12 +544,12 @@
479	544	struct device *dev = dp->dev;
480	545	int ret;
481	546
482		- encoder->possible_crtcs = drm_of_find_possible_crtcs(drm_dev,
483		- dev->of_node);
	547	+ encoder->possible_crtcs = rockchip_drm_of_find_possible_crtcs(drm_dev,
	548	+ dev->of_node);
484	549	DRM_DEBUG_KMS("possible_crtcs = 0x%x\n", encoder->possible_crtcs);
485	550
486		- ret = drm_encoder_init(drm_dev, encoder, &rockchip_dp_encoder_funcs,
487		- DRM_MODE_ENCODER_TMDS, NULL);
	551	+ ret = drm_simple_encoder_init(drm_dev, encoder,
	552	+ DRM_MODE_ENCODER_TMDS);
488	553	if (ret) {
489	554	DRM_ERROR("failed to initialize encoder with drm\n");
490	555	return ret;
..	..	@@ -499,36 +564,20 @@
499	564	void *data)
500	565	{
501	566	struct rockchip_dp_device *dp = dev_get_drvdata(dev);
502		- const struct rockchip_dp_chip_data *dp_data;
503	567	struct drm_device *drm_dev = data;
504	568	int ret;
505	569
506		- dp_data = of_device_get_match_data(dev);
507		- if (!dp_data)
508		- return -ENODEV;
509		-
510		- dp->data = dp_data;
511	570	dp->drm_dev = drm_dev;
512	571
513		- ret = rockchip_dp_drm_create_encoder(dp);
514		- if (ret) {
515		- DRM_ERROR("failed to create drm encoder\n");
516		- return ret;
	572	+ if (!dp->plat_data.left) {
	573	+ ret = rockchip_dp_drm_create_encoder(dp);
	574	+ if (ret) {
	575	+ DRM_ERROR("failed to create drm encoder\n");
	576	+ return ret;
	577	+ }
	578	+
	579	+ dp->plat_data.encoder = &dp->encoder;
517	580	}
518		-
519		- dp->plat_data.encoder = &dp->encoder;
520		- dp->plat_data.ssc = dp->data->ssc;
521		- dp->plat_data.dev_type = dp->data->chip_type;
522		- dp->plat_data.power_on_start = rockchip_dp_poweron_start;
523		- dp->plat_data.power_on_end = rockchip_dp_poweron_end;
524		- dp->plat_data.power_off = rockchip_dp_powerdown;
525		- dp->plat_data.get_modes = rockchip_dp_get_modes;
526		- dp->plat_data.attach = rockchip_dp_bridge_attach;
527		- dp->plat_data.property_ops = &rockchip_dp_encoder_property_ops;
528		-
529		- ret = rockchip_drm_psr_register(&dp->encoder, analogix_dp_psr_set);
530		- if (ret < 0)
531		- goto err_cleanup_encoder;
532	581
533	582	if (dp->data->audio) {
534	583	struct hdmi_codec_pdata codec_data = {
..	..	@@ -545,26 +594,19 @@
545	594	sizeof(codec_data));
546	595	if (IS_ERR(dp->audio_pdev)) {
547	596	ret = PTR_ERR(dp->audio_pdev);
548		- goto err_unreg_psr;
	597	+ goto err_cleanup_encoder;
549	598	}
550	599	}
551	600
552		- dp->adp = analogix_dp_bind(dev, dp->drm_dev, &dp->plat_data);
553		- if (IS_ERR(dp->adp)) {
554		- ret = PTR_ERR(dp->adp);
555		- goto err_unreg_audio;
556		- }
557		-
558		- dp->sub_dev.connector = &dp->adp->connector;
559		- dp->sub_dev.of_node = dev->of_node;
560		- rockchip_drm_register_sub_dev(&dp->sub_dev);
	601	+ ret = analogix_dp_bind(dp->adp, drm_dev);
	602	+ if (ret)
	603	+ goto err_unregister_audio_pdev;
561	604
562	605	return 0;
563		-err_unreg_audio:
	606	+
	607	+err_unregister_audio_pdev:
564	608	if (dp->audio_pdev)
565	609	platform_device_unregister(dp->audio_pdev);
566		-err_unreg_psr:
567		- rockchip_drm_psr_unregister(&dp->encoder);
568	610	err_cleanup_encoder:
569	611	dp->encoder.funcs->destroy(&dp->encoder);
570	612	return ret;
..	..	@@ -575,14 +617,10 @@
575	617	{
576	618	struct rockchip_dp_device *dp = dev_get_drvdata(dev);
577	619
578		- rockchip_drm_unregister_sub_dev(&dp->sub_dev);
579	620	if (dp->audio_pdev)
580	621	platform_device_unregister(dp->audio_pdev);
581	622	analogix_dp_unbind(dp->adp);
582		- rockchip_drm_psr_unregister(&dp->encoder);
583	623	dp->encoder.funcs->destroy(&dp->encoder);
584		-
585		- dp->adp = ERR_PTR(-ENODEV);
586	624	}
587	625
588	626	static const struct component_ops rockchip_dp_component_ops = {
..	..	@@ -593,10 +631,15 @@
593	631	static int rockchip_dp_probe(struct platform_device *pdev)
594	632	{
595	633	struct device *dev = &pdev->dev;
	634	+ const struct rockchip_dp_chip_data *dp_data;
596	635	struct drm_panel *panel = NULL;
597	636	struct drm_bridge *bridge = NULL;
598	637	struct rockchip_dp_device *dp;
599		- int ret, id;
	638	+ int id, i, ret;
	639	+
	640	+ dp_data = of_device_get_match_data(dev);
	641	+ if (!dp_data)
	642	+ return -ENODEV;
600	643
601	644	ret = drm_of_find_panel_or_bridge(dev->of_node, 1, 0, &panel, &bridge);
602	645	if (ret < 0 && ret != -ENODEV)
..	..	@@ -609,12 +652,32 @@
609	652	id = of_alias_get_id(dev->of_node, "edp");
610	653	if (id < 0)
611	654	id = 0;
612		- dp->id = id;
	655	+
	656	+ i = 0;
	657	+ while (is_rockchip(dp_data[i].chip_type))
	658	+ i++;
	659	+
	660	+ if (id >= i) {
	661	+ dev_err(dev, "invalid id: %d\n", id);
	662	+ return -ENODEV;
	663	+ }
	664	+
613	665	dp->dev = dev;
	666	+ dp->id = id;
614	667	dp->adp = ERR_PTR(-ENODEV);
	668	+ dp->data = &dp_data[id];
	669	+ dp->plat_data.ssc = dp->data->ssc;
615	670	dp->plat_data.panel = panel;
616		- dp->plat_data.skip_connector = !!bridge;
617		- dp->bridge = bridge;
	671	+ dp->plat_data.dev_type = dp->data->chip_type;
	672	+ dp->plat_data.power_on_start = rockchip_dp_poweron_start;
	673	+ dp->plat_data.power_off = rockchip_dp_powerdown;
	674	+ dp->plat_data.get_modes = rockchip_dp_get_modes;
	675	+ dp->plat_data.attach = rockchip_dp_bridge_attach;
	676	+ dp->plat_data.detach = rockchip_dp_bridge_detach;
	677	+ dp->plat_data.convert_to_split_mode = drm_mode_convert_to_split_mode;
	678	+ dp->plat_data.convert_to_origin_mode = drm_mode_convert_to_origin_mode;
	679	+ dp->plat_data.skip_connector = rockchip_dp_skip_connector(bridge);
	680	+ dp->plat_data.bridge = bridge;
618	681
619	682	ret = rockchip_dp_of_probe(dp);
620	683	if (ret < 0)
..	..	@@ -622,18 +685,56 @@
622	685
623	686	platform_set_drvdata(pdev, dp);
624	687
625		- return component_add(dev, &rockchip_dp_component_ops);
	688	+ dp->adp = analogix_dp_probe(dev, &dp->plat_data);
	689	+ if (IS_ERR(dp->adp))
	690	+ return PTR_ERR(dp->adp);
	691	+
	692	+ if (dp->data->split_mode && device_property_read_bool(dev, "split-mode")) {
	693	+ struct rockchip_dp_device *secondary =
	694	+ rockchip_dp_find_by_id(dev->driver, !dp->id);
	695	+ if (!secondary) {
	696	+ ret = -EPROBE_DEFER;
	697	+ goto err_dp_remove;
	698	+ }
	699	+
	700	+ dp->plat_data.right = secondary->adp;
	701	+ dp->plat_data.split_mode = true;
	702	+ secondary->plat_data.panel = dp->plat_data.panel;
	703	+ secondary->plat_data.left = dp->adp;
	704	+ secondary->plat_data.split_mode = true;
	705	+ }
	706	+
	707	+ device_property_read_u32(dev, "min-refresh-rate", &dp->min_refresh_rate);
	708	+ device_property_read_u32(dev, "max-refresh-rate", &dp->max_refresh_rate);
	709	+
	710	+ if (dp->data->split_mode && device_property_read_bool(dev, "dual-connector-split")) {
	711	+ dp->plat_data.dual_connector_split = true;
	712	+ if (device_property_read_bool(dev, "left-display"))
	713	+ dp->plat_data.left_display = true;
	714	+ }
	715	+
	716	+ ret = component_add(dev, &rockchip_dp_component_ops);
	717	+ if (ret)
	718	+ goto err_dp_remove;
	719	+
	720	+ return 0;
	721	+
	722	+err_dp_remove:
	723	+ analogix_dp_remove(dp->adp);
	724	+ return ret;
626	725	}
627	726
628	727	static int rockchip_dp_remove(struct platform_device *pdev)
629	728	{
	729	+ struct rockchip_dp_device *dp = platform_get_drvdata(pdev);
	730	+
630	731	component_del(&pdev->dev, &rockchip_dp_component_ops);
	732	+ analogix_dp_remove(dp->adp);
631	733
632	734	return 0;
633	735	}
634	736
635		-#ifdef CONFIG_PM_SLEEP
636		-static int rockchip_dp_suspend(struct device *dev)
	737	+static __maybe_unused int rockchip_dp_suspend(struct device *dev)
637	738	{
638	739	struct rockchip_dp_device *dp = dev_get_drvdata(dev);
639	740
..	..	@@ -643,7 +744,7 @@
643	744	return analogix_dp_suspend(dp->adp);
644	745	}
645	746
646		-static int rockchip_dp_resume(struct device *dev)
	747	+static __maybe_unused int rockchip_dp_resume(struct device *dev)
647	748	{
648	749	struct rockchip_dp_device *dp = dev_get_drvdata(dev);
649	750
..	..	@@ -653,64 +754,86 @@
653	754	return analogix_dp_resume(dp->adp);
654	755	}
655	756
656		-static int rockchip_dp_runtime_suspend(struct device *dev)
	757	+static __maybe_unused int rockchip_dp_runtime_suspend(struct device *dev)
657	758	{
658	759	struct rockchip_dp_device *dp = dev_get_drvdata(dev);
659	760
660		- clk_bulk_disable_unprepare(dp->num_clks, dp->clks);
	761	+ if (IS_ERR(dp->adp))
	762	+ return 0;
661	763
662		- return 0;
	764	+ return analogix_dp_runtime_suspend(dp->adp);
663	765	}
664	766
665		-static int rockchip_dp_runtime_resume(struct device *dev)
	767	+static __maybe_unused int rockchip_dp_runtime_resume(struct device *dev)
666	768	{
667	769	struct rockchip_dp_device *dp = dev_get_drvdata(dev);
668	770
669		- return clk_bulk_prepare_enable(dp->num_clks, dp->clks);
	771	+ if (IS_ERR(dp->adp))
	772	+ return 0;
	773	+
	774	+ return analogix_dp_runtime_resume(dp->adp);
670	775	}
671		-#endif
672	776
673	777	static const struct dev_pm_ops rockchip_dp_pm_ops = {
674		-#ifdef CONFIG_PM_SLEEP
675		- .suspend_late = rockchip_dp_suspend,
676		- .resume_early = rockchip_dp_resume,
677		- .runtime_suspend = rockchip_dp_runtime_suspend,
678		- .runtime_resume = rockchip_dp_runtime_resume,
679		-#endif
	778	+ SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(rockchip_dp_suspend, rockchip_dp_resume)
	779	+ SET_RUNTIME_PM_OPS(rockchip_dp_runtime_suspend,
	780	+ rockchip_dp_runtime_resume, NULL)
680	781	};
681	782
682		-static const struct rockchip_dp_chip_data rk3399_edp = {
683		- .lcdsel_grf_reg = RK3399_GRF_SOC_CON20,
684		- .lcdsel_big = HIWORD_UPDATE(0, RK3399_EDP_LCDC_SEL),
685		- .lcdsel_lit = HIWORD_UPDATE(RK3399_EDP_LCDC_SEL, RK3399_EDP_LCDC_SEL),
686		- .chip_type = RK3399_EDP,
687		- .ssc = true,
	783	+static const struct rockchip_dp_chip_data rk3399_edp[] = {
	784	+ {
	785	+ .chip_type = RK3399_EDP,
	786	+ .lcdc_sel = GRF_REG_FIELD(0x6250, 5, 5),
	787	+ .ssc = true,
	788	+ },
	789	+ { /* sentinel */ }
688	790	};
689	791
690		-static const struct rockchip_dp_chip_data rk3368_edp = {
691		- .chip_type = RK3368_EDP,
692		- .ssc = true,
	792	+static const struct rockchip_dp_chip_data rk3288_dp[] = {
	793	+ {
	794	+ .chip_type = RK3288_DP,
	795	+ .lcdc_sel = GRF_REG_FIELD(0x025c, 5, 5),
	796	+ .ssc = true,
	797	+ },
	798	+ { /* sentinel */ }
693	799	};
694	800
695		-static const struct rockchip_dp_chip_data rk3288_dp = {
696		- .lcdsel_grf_reg = RK3288_GRF_SOC_CON6,
697		- .lcdsel_big = HIWORD_UPDATE(0, RK3288_EDP_LCDC_SEL),
698		- .lcdsel_lit = HIWORD_UPDATE(RK3288_EDP_LCDC_SEL, RK3288_EDP_LCDC_SEL),
699		- .chip_type = RK3288_DP,
700		- .ssc = true,
	801	+static const struct rockchip_dp_chip_data rk3568_edp[] = {
	802	+ {
	803	+ .chip_type = RK3568_EDP,
	804	+ .ssc = true,
	805	+ .audio = true,
	806	+ },
	807	+ { /* sentinel */ }
701	808	};
702	809
703		-static const struct rockchip_dp_chip_data rk3568_edp = {
704		- .chip_type = RK3568_EDP,
705		- .ssc = true,
706		- .audio = true,
	810	+static const struct rockchip_dp_chip_data rk3588_edp[] = {
	811	+ {
	812	+ .chip_type = RK3588_EDP,
	813	+ .spdif_sel = GRF_REG_FIELD(0x0000, 4, 4),
	814	+ .i2s_sel = GRF_REG_FIELD(0x0000, 3, 3),
	815	+ .edp_mode = GRF_REG_FIELD(0x0000, 0, 0),
	816	+ .ssc = true,
	817	+ .audio = true,
	818	+ .split_mode = true,
	819	+ },
	820	+ {
	821	+ .chip_type = RK3588_EDP,
	822	+ .spdif_sel = GRF_REG_FIELD(0x0004, 4, 4),
	823	+ .i2s_sel = GRF_REG_FIELD(0x0004, 3, 3),
	824	+ .edp_mode = GRF_REG_FIELD(0x0004, 0, 0),
	825	+ .ssc = true,
	826	+ .audio = true,
	827	+ .split_mode = true,
	828	+ },
	829	+ { /* sentinel */ }
707	830	};
708	831
709	832	static const struct of_device_id rockchip_dp_dt_ids[] = {
710	833	{.compatible = "rockchip,rk3288-dp", .data = &rk3288_dp },
711		- {.compatible = "rockchip,rk3368-edp", .data = &rk3368_edp },
712	834	{.compatible = "rockchip,rk3399-edp", .data = &rk3399_edp },
713	835	{.compatible = "rockchip,rk3568-edp", .data = &rk3568_edp },
	836	+ {.compatible = "rockchip,rk3588-edp", .data = &rk3588_edp },
714	837	{}
715	838	};
716	839	MODULE_DEVICE_TABLE(of, rockchip_dp_dt_ids);