update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/drivers/gpu/drm/radeon/ni_dpm.c
..
..
@@ -21,15 +21,16 @@
21
21
  *
22
22
  */
23
23
 
24
-#include <drm/drmP.h>
25
-#include "radeon.h"
26
-#include "radeon_asic.h"
24
+#include <linux/math64.h>
25
+#include <linux/pci.h>
26
+#include <linux/seq_file.h>
27
+
28
+#include "atom.h"
29
+#include "ni_dpm.h"
27
30
 #include "nid.h"
28
31
 #include "r600_dpm.h"
29
-#include "ni_dpm.h"
30
-#include "atom.h"
31
-#include <linux/math64.h>
32
-#include <linux/seq_file.h>
32
+#include "radeon.h"
33
+#include "radeon_asic.h"
33
34
 
34
35
 #define MC_CG_ARB_FREQ_F0           0x0a
35
36
 #define MC_CG_ARB_FREQ_F1           0x0b
..
..
@@ -2239,8 +2240,12 @@
2239
2240
 						     ASIC_INTERNAL_MEMORY_SS, vco_freq)) {
2240
2241
 			u32 reference_clock = rdev->clock.mpll.reference_freq;
2241
2242
 			u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div);
2242
-			u32 clk_s = reference_clock * 5 / (decoded_ref * ss.rate);
2243
-			u32 clk_v = ss.percentage *
2243
+			u32 clk_s, clk_v;
2244
+
2245
+			if (!decoded_ref)
2246
+				return -EINVAL;
2247
+			clk_s = reference_clock * 5 / (decoded_ref * ss.rate);
2248
+			clk_v = ss.percentage *
2244
2249
 				(0x4000 * dividers.whole_fb_div + 0x800 * dividers.frac_fb_div) / (clk_s * 625);
2245
2250
 
2246
2251
 			mpll_ss1 &= ~CLKV_MASK;
..
..
@@ -2684,11 +2689,12 @@
2684
2689
 	struct rv7xx_power_info *pi = rv770_get_pi(rdev);
2685
2690
 	u16 address = pi->state_table_start +
2686
2691
 		offsetof(NISLANDS_SMC_STATETABLE, driverState);
2687
-	u16 state_size = sizeof(NISLANDS_SMC_SWSTATE) +
2688
-		((NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE - 1) * sizeof(NISLANDS_SMC_HW_PERFORMANCE_LEVEL));
2692
+	NISLANDS_SMC_SWSTATE *smc_state;
2693
+	size_t state_size = struct_size(smc_state, levels,
2694
+			NISLANDS_MAX_SMC_PERFORMANCE_LEVELS_PER_SWSTATE);
2689
2695
 	int ret;
2690
-	NISLANDS_SMC_SWSTATE *smc_state = kzalloc(state_size, GFP_KERNEL);
2691
2696
 
2697
+	smc_state = kzalloc(state_size, GFP_KERNEL);
2692
2698
 	if (smc_state == NULL)
2693
2699
 		return -ENOMEM;
2694
2700
 
..
..
@@ -2738,10 +2744,10 @@
2738
2744
 					table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
2739
2745
 			}
2740
2746
 			j++;
2741
-			if (j > SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE)
2742
-				return -EINVAL;
2743
2747
 			break;
2744
2748
 		case MC_SEQ_RESERVE_M >> 2:
2749
+			if (j >= SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE)
2750
+				return -EINVAL;
2745
2751
 			temp_reg = RREG32(MC_PMG_CMD_MRS1);
2746
2752
 			table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
2747
2753
 			table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
..
..
@@ -2750,8 +2756,6 @@
2750
2756
 					(temp_reg & 0xffff0000) |
2751
2757
 					(table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
2752
2758
 			j++;
2753
-			if (j > SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE)
2754
-				return -EINVAL;
2755
2759
 			break;
2756
2760
 		default:
2757
2761
 			break;