update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/drivers/gpu/drm/i915/gvt/edid.c
..
..
@@ -77,16 +77,32 @@
77
77
 	return chr;
78
78
 }
79
79
 
80
+static inline int cnp_get_port_from_gmbus0(u32 gmbus0)
81
+{
82
+	int port_select = gmbus0 & _GMBUS_PIN_SEL_MASK;
83
+	int port = -EINVAL;
84
+
85
+	if (port_select == GMBUS_PIN_1_BXT)
86
+		port = PORT_B;
87
+	else if (port_select == GMBUS_PIN_2_BXT)
88
+		port = PORT_C;
89
+	else if (port_select == GMBUS_PIN_3_BXT)
90
+		port = PORT_D;
91
+	else if (port_select == GMBUS_PIN_4_CNP)
92
+		port = PORT_E;
93
+	return port;
94
+}
95
+
80
96
 static inline int bxt_get_port_from_gmbus0(u32 gmbus0)
81
97
 {
82
98
 	int port_select = gmbus0 & _GMBUS_PIN_SEL_MASK;
83
99
 	int port = -EINVAL;
84
100
 
85
-	if (port_select == 1)
101
+	if (port_select == GMBUS_PIN_1_BXT)
86
102
 		port = PORT_B;
87
-	else if (port_select == 2)
103
+	else if (port_select == GMBUS_PIN_2_BXT)
88
104
 		port = PORT_C;
89
-	else if (port_select == 3)
105
+	else if (port_select == GMBUS_PIN_3_BXT)
90
106
 		port = PORT_D;
91
107
 	return port;
92
108
 }
..
..
@@ -96,13 +112,13 @@
96
112
 	int port_select = gmbus0 & _GMBUS_PIN_SEL_MASK;
97
113
 	int port = -EINVAL;
98
114
 
99
-	if (port_select == 2)
115
+	if (port_select == GMBUS_PIN_VGADDC)
100
116
 		port = PORT_E;
101
-	else if (port_select == 4)
117
+	else if (port_select == GMBUS_PIN_DPC)
102
118
 		port = PORT_C;
103
-	else if (port_select == 5)
119
+	else if (port_select == GMBUS_PIN_DPB)
104
120
 		port = PORT_B;
105
-	else if (port_select == 6)
121
+	else if (port_select == GMBUS_PIN_DPD)
106
122
 		port = PORT_D;
107
123
 	return port;
108
124
 }
..
..
@@ -119,7 +135,7 @@
119
135
 static int gmbus0_mmio_write(struct intel_vgpu *vgpu,
120
136
 			unsigned int offset, void *p_data, unsigned int bytes)
121
137
 {
122
-	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
138
+	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
123
139
 	int port, pin_select;
124
140
 
125
141
 	memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);
..
..
@@ -131,11 +147,13 @@
131
147
 	if (pin_select == 0)
132
148
 		return 0;
133
149
 
134
-	if (IS_BROXTON(dev_priv))
150
+	if (IS_BROXTON(i915))
135
151
 		port = bxt_get_port_from_gmbus0(pin_select);
152
+	else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915))
153
+		port = cnp_get_port_from_gmbus0(pin_select);
136
154
 	else
137
155
 		port = get_port_from_gmbus0(pin_select);
138
-	if (WARN_ON(port < 0))
156
+	if (drm_WARN_ON(&i915->drm, port < 0))
139
157
 		return 0;
140
158
 
141
159
 	vgpu->display.i2c_edid.state = I2C_GMBUS;
..
..
@@ -258,7 +276,9 @@
258
276
 static int gmbus3_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
259
277
 	void *p_data, unsigned int bytes)
260
278
 {
261
-	WARN_ON(1);
279
+	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
280
+
281
+	drm_WARN_ON(&i915->drm, 1);
262
282
 	return 0;
263
283
 }
264
284
 
..
..
@@ -340,6 +360,9 @@
340
360
 /**
341
361
  * intel_gvt_i2c_handle_gmbus_read - emulate gmbus register mmio read
342
362
  * @vgpu: a vGPU
363
+ * @offset: reg offset
364
+ * @p_data: data return buffer
365
+ * @bytes: access data length
343
366
  *
344
367
  * This function is used to emulate gmbus register mmio read
345
368
  *
..
..
@@ -350,7 +373,9 @@
350
373
 int intel_gvt_i2c_handle_gmbus_read(struct intel_vgpu *vgpu,
351
374
 	unsigned int offset, void *p_data, unsigned int bytes)
352
375
 {
353
-	if (WARN_ON(bytes > 8 && (offset & (bytes - 1))))
376
+	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
377
+
378
+	if (drm_WARN_ON(&i915->drm, bytes > 8 && (offset & (bytes - 1))))
354
379
 		return -EINVAL;
355
380
 
356
381
 	if (offset == i915_mmio_reg_offset(PCH_GMBUS2))
..
..
@@ -365,6 +390,9 @@
365
390
 /**
366
391
  * intel_gvt_i2c_handle_gmbus_write - emulate gmbus register mmio write
367
392
  * @vgpu: a vGPU
393
+ * @offset: reg offset
394
+ * @p_data: data return buffer
395
+ * @bytes: access data length
368
396
  *
369
397
  * This function is used to emulate gmbus register mmio write
370
398
  *
..
..
@@ -375,7 +403,9 @@
375
403
 int intel_gvt_i2c_handle_gmbus_write(struct intel_vgpu *vgpu,
376
404
 		unsigned int offset, void *p_data, unsigned int bytes)
377
405
 {
378
-	if (WARN_ON(bytes > 8 && (offset & (bytes - 1))))
406
+	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
407
+
408
+	if (drm_WARN_ON(&i915->drm, bytes > 8 && (offset & (bytes - 1))))
379
409
 		return -EINVAL;
380
410
 
381
411
 	if (offset == i915_mmio_reg_offset(PCH_GMBUS0))
..
..
@@ -437,6 +467,9 @@
437
467
 /**
438
468
  * intel_gvt_i2c_handle_aux_ch_write - emulate AUX channel register write
439
469
  * @vgpu: a vGPU
470
+ * @port_idx: port index
471
+ * @offset: reg offset
472
+ * @p_data: write ptr
440
473
  *
441
474
  * This function is used to emulate AUX channel register write
442
475
  *
..
..
@@ -446,6 +479,7 @@
446
479
 				unsigned int offset,
447
480
 				void *p_data)
448
481
 {
482
+	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
449
483
 	struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;
450
484
 	int msg_length, ret_msg_size;
451
485
 	int msg, addr, ctrl, op;
..
..
@@ -505,9 +539,9 @@
505
539
 		 * support the gfx driver to do EDID access.
506
540
 		 */
507
541
 	} else {
508
-		if (WARN_ON((op & 0x1) != GVT_AUX_I2C_READ))
542
+		if (drm_WARN_ON(&i915->drm, (op & 0x1) != GVT_AUX_I2C_READ))
509
543
 			return;
510
-		if (WARN_ON(msg_length != 4))
544
+		if (drm_WARN_ON(&i915->drm, msg_length != 4))
511
545
 			return;
512
546
 		if (i2c_edid->edid_available && i2c_edid->slave_selected) {
513
547
 			unsigned char val = edid_get_byte(vgpu);