update kernel to 5.10.198

hc

2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf

 kernel/drivers/gpu/drm/i915/gvt/display.c
..
..
@@ -57,7 +57,7 @@
57
57
 
58
58
 static int edp_pipe_is_enabled(struct intel_vgpu *vgpu)
59
59
 {
60
-	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
60
+	struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
61
61
 
62
62
 	if (!(vgpu_vreg_t(vgpu, PIPECONF(_PIPE_EDP)) & PIPECONF_ENABLE))
63
63
 		return 0;
..
..
@@ -69,9 +69,10 @@
69
69
 
70
70
 int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe)
71
71
 {
72
-	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
72
+	struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
73
73
 
74
-	if (WARN_ON(pipe < PIPE_A || pipe >= I915_MAX_PIPES))
74
+	if (drm_WARN_ON(&dev_priv->drm,
75
+			pipe < PIPE_A || pipe >= I915_MAX_PIPES))
75
76
 		return -EINVAL;
76
77
 
77
78
 	if (vgpu_vreg_t(vgpu, PIPECONF(pipe)) & PIPECONF_ENABLE)
..
..
@@ -163,30 +164,185 @@
163
164
 
164
165
 /* let the virtual display supports DP1.2 */
165
166
 static u8 dpcd_fix_data[DPCD_HEADER_SIZE] = {
166
-	0x12, 0x014, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
167
+	0x12, 0x014, 0x84, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
167
168
 };
168
169
 
169
170
 static void emulate_monitor_status_change(struct intel_vgpu *vgpu)
170
171
 {
171
-	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
172
+	struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
172
173
 	int pipe;
173
174
 
174
175
 	if (IS_BROXTON(dev_priv)) {
176
+		enum transcoder trans;
177
+		enum port port;
178
+
179
+		/* Clear PIPE, DDI, PHY, HPD before setting new */
175
180
 		vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= ~(BXT_DE_PORT_HP_DDIA |
176
181
 			BXT_DE_PORT_HP_DDIB |
177
182
 			BXT_DE_PORT_HP_DDIC);
178
183
 
184
+		for_each_pipe(dev_priv, pipe) {
185
+			vgpu_vreg_t(vgpu, PIPECONF(pipe)) &=
186
+				~(PIPECONF_ENABLE | I965_PIPECONF_ACTIVE);
187
+			vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE;
188
+			vgpu_vreg_t(vgpu, SPRCTL(pipe)) &= ~SPRITE_ENABLE;
189
+			vgpu_vreg_t(vgpu, CURCNTR(pipe)) &= ~MCURSOR_MODE;
190
+			vgpu_vreg_t(vgpu, CURCNTR(pipe)) |= MCURSOR_MODE_DISABLE;
191
+		}
192
+
193
+		for (trans = TRANSCODER_A; trans <= TRANSCODER_EDP; trans++) {
194
+			vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(trans)) &=
195
+				~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
196
+				  TRANS_DDI_PORT_MASK | TRANS_DDI_FUNC_ENABLE);
197
+		}
198
+		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) &=
199
+			~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
200
+			  TRANS_DDI_PORT_MASK);
201
+
202
+		for (port = PORT_A; port <= PORT_C; port++) {
203
+			vgpu_vreg_t(vgpu, BXT_PHY_CTL(port)) &=
204
+				~BXT_PHY_LANE_ENABLED;
205
+			vgpu_vreg_t(vgpu, BXT_PHY_CTL(port)) |=
206
+				(BXT_PHY_CMNLANE_POWERDOWN_ACK |
207
+				 BXT_PHY_LANE_POWERDOWN_ACK);
208
+
209
+			vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(port)) &=
210
+				~(PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE |
211
+				  PORT_PLL_REF_SEL | PORT_PLL_LOCK |
212
+				  PORT_PLL_ENABLE);
213
+
214
+			vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) &=
215
+				~(DDI_INIT_DISPLAY_DETECTED |
216
+				  DDI_BUF_CTL_ENABLE);
217
+			vgpu_vreg_t(vgpu, DDI_BUF_CTL(port)) |= DDI_BUF_IS_IDLE;
218
+		}
219
+		vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
220
+			~(PORTA_HOTPLUG_ENABLE | PORTA_HOTPLUG_STATUS_MASK);
221
+		vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
222
+			~(PORTB_HOTPLUG_ENABLE | PORTB_HOTPLUG_STATUS_MASK);
223
+		vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
224
+			~(PORTC_HOTPLUG_ENABLE | PORTC_HOTPLUG_STATUS_MASK);
225
+		/* No hpd_invert set in vgpu vbt, need to clear invert mask */
226
+		vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &= ~BXT_DDI_HPD_INVERT_MASK;
227
+		vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &= ~BXT_DE_PORT_HOTPLUG_MASK;
228
+
229
+		vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) &= ~(BIT(0) | BIT(1));
230
+		vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) &=
231
+			~PHY_POWER_GOOD;
232
+		vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) &=
233
+			~PHY_POWER_GOOD;
234
+		vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) &= ~BIT(30);
235
+		vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) &= ~BIT(30);
236
+
237
+		vgpu_vreg_t(vgpu, SFUSE_STRAP) &= ~SFUSE_STRAP_DDIB_DETECTED;
238
+		vgpu_vreg_t(vgpu, SFUSE_STRAP) &= ~SFUSE_STRAP_DDIC_DETECTED;
239
+
240
+		/*
241
+		 * Only 1 PIPE enabled in current vGPU display and PIPE_A is
242
+		 *  tied to TRANSCODER_A in HW, so it's safe to assume PIPE_A,
243
+		 *   TRANSCODER_A can be enabled. PORT_x depends on the input of
244
+		 *   setup_virtual_dp_monitor.
245
+		 */
246
+		vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= PIPECONF_ENABLE;
247
+		vgpu_vreg_t(vgpu, PIPECONF(PIPE_A)) |= I965_PIPECONF_ACTIVE;
248
+
249
+		/*
250
+		 * Golden M/N are calculated based on:
251
+		 *   24 bpp, 4 lanes, 154000 pixel clk (from virtual EDID),
252
+		 *   DP link clk 1620 MHz and non-constant_n.
253
+		 * TODO: calculate DP link symbol clk and stream clk m/n.
254
+		 */
255
+		vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) = 63 << TU_SIZE_SHIFT;
256
+		vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e;
257
+		vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000;
258
+		vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e;
259
+		vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000;
260
+
261
+		/* Enable per-DDI/PORT vreg */
179
262
 		if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
263
+			vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(1);
264
+			vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY1)) |=
265
+				PHY_POWER_GOOD;
266
+			vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY1)) |=
267
+				BIT(30);
268
+			vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) |=
269
+				BXT_PHY_LANE_ENABLED;
270
+			vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_A)) &=
271
+				~(BXT_PHY_CMNLANE_POWERDOWN_ACK |
272
+				  BXT_PHY_LANE_POWERDOWN_ACK);
273
+			vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_A)) |=
274
+				(PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE |
275
+				 PORT_PLL_REF_SEL | PORT_PLL_LOCK |
276
+				 PORT_PLL_ENABLE);
277
+			vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) |=
278
+				(DDI_BUF_CTL_ENABLE | DDI_INIT_DISPLAY_DETECTED);
279
+			vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_A)) &=
280
+				~DDI_BUF_IS_IDLE;
281
+			vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)) |=
282
+				(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
283
+				 TRANS_DDI_FUNC_ENABLE);
284
+			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
285
+				PORTA_HOTPLUG_ENABLE;
180
286
 			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
181
287
 				BXT_DE_PORT_HP_DDIA;
182
288
 		}
183
289
 
184
290
 		if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
291
+			vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIB_DETECTED;
292
+			vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0);
293
+			vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |=
294
+				PHY_POWER_GOOD;
295
+			vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |=
296
+				BIT(30);
297
+			vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) |=
298
+				BXT_PHY_LANE_ENABLED;
299
+			vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_B)) &=
300
+				~(BXT_PHY_CMNLANE_POWERDOWN_ACK |
301
+				  BXT_PHY_LANE_POWERDOWN_ACK);
302
+			vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_B)) |=
303
+				(PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE |
304
+				 PORT_PLL_REF_SEL | PORT_PLL_LOCK |
305
+				 PORT_PLL_ENABLE);
306
+			vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) |=
307
+				DDI_BUF_CTL_ENABLE;
308
+			vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_B)) &=
309
+				~DDI_BUF_IS_IDLE;
310
+			vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
311
+				(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
312
+				 (PORT_B << TRANS_DDI_PORT_SHIFT) |
313
+				 TRANS_DDI_FUNC_ENABLE);
314
+			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
315
+				PORTB_HOTPLUG_ENABLE;
185
316
 			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
186
317
 				BXT_DE_PORT_HP_DDIB;
187
318
 		}
188
319
 
189
320
 		if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
321
+			vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDIC_DETECTED;
322
+			vgpu_vreg_t(vgpu, BXT_P_CR_GT_DISP_PWRON) |= BIT(0);
323
+			vgpu_vreg_t(vgpu, BXT_PORT_CL1CM_DW0(DPIO_PHY0)) |=
324
+				PHY_POWER_GOOD;
325
+			vgpu_vreg_t(vgpu, BXT_PHY_CTL_FAMILY(DPIO_PHY0)) |=
326
+				BIT(30);
327
+			vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) |=
328
+				BXT_PHY_LANE_ENABLED;
329
+			vgpu_vreg_t(vgpu, BXT_PHY_CTL(PORT_C)) &=
330
+				~(BXT_PHY_CMNLANE_POWERDOWN_ACK |
331
+				  BXT_PHY_LANE_POWERDOWN_ACK);
332
+			vgpu_vreg_t(vgpu, BXT_PORT_PLL_ENABLE(PORT_C)) |=
333
+				(PORT_PLL_POWER_STATE | PORT_PLL_POWER_ENABLE |
334
+				 PORT_PLL_REF_SEL | PORT_PLL_LOCK |
335
+				 PORT_PLL_ENABLE);
336
+			vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) |=
337
+				DDI_BUF_CTL_ENABLE;
338
+			vgpu_vreg_t(vgpu, DDI_BUF_CTL(PORT_C)) &=
339
+				~DDI_BUF_IS_IDLE;
340
+			vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
341
+				(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
342
+				 (PORT_B << TRANS_DDI_PORT_SHIFT) |
343
+				 TRANS_DDI_FUNC_ENABLE);
344
+			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
345
+				PORTC_HOTPLUG_ENABLE;
190
346
 			vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
191
347
 				BXT_DE_PORT_HP_DDIC;
192
348
 		}
..
..
@@ -198,7 +354,10 @@
198
354
 			SDE_PORTC_HOTPLUG_CPT |
199
355
 			SDE_PORTD_HOTPLUG_CPT);
200
356
 
201
-	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
357
+	if (IS_SKYLAKE(dev_priv) ||
358
+	    IS_KABYLAKE(dev_priv) ||
359
+	    IS_COFFEELAKE(dev_priv) ||
360
+	    IS_COMETLAKE(dev_priv)) {
202
361
 		vgpu_vreg_t(vgpu, SDEISR) &= ~(SDE_PORTA_HOTPLUG_SPT |
203
362
 				SDE_PORTE_HOTPLUG_SPT);
204
363
 		vgpu_vreg_t(vgpu, SKL_FUSE_STATUS) |=
..
..
@@ -246,7 +405,7 @@
246
405
 			~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
247
406
 			TRANS_DDI_PORT_MASK);
248
407
 		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
249
-			(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DVI |
408
+			(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
250
409
 			(PORT_B << TRANS_DDI_PORT_SHIFT) |
251
410
 			TRANS_DDI_FUNC_ENABLE);
252
411
 		if (IS_BROADWELL(dev_priv)) {
..
..
@@ -272,7 +431,7 @@
272
431
 			~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
273
432
 			TRANS_DDI_PORT_MASK);
274
433
 		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
275
-			(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DVI |
434
+			(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
276
435
 			(PORT_C << TRANS_DDI_PORT_SHIFT) |
277
436
 			TRANS_DDI_FUNC_ENABLE);
278
437
 		if (IS_BROADWELL(dev_priv)) {
..
..
@@ -298,7 +457,7 @@
298
457
 			~(TRANS_DDI_BPC_MASK | TRANS_DDI_MODE_SELECT_MASK |
299
458
 			TRANS_DDI_PORT_MASK);
300
459
 		vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(TRANSCODER_A)) |=
301
-			(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DVI |
460
+			(TRANS_DDI_BPC_8 | TRANS_DDI_MODE_SELECT_DP_SST |
302
461
 			(PORT_D << TRANS_DDI_PORT_SHIFT) |
303
462
 			TRANS_DDI_FUNC_ENABLE);
304
463
 		if (IS_BROADWELL(dev_priv)) {
..
..
@@ -312,7 +471,10 @@
312
471
 		vgpu_vreg_t(vgpu, SFUSE_STRAP) |= SFUSE_STRAP_DDID_DETECTED;
313
472
 	}
314
473
 
315
-	if ((IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) &&
474
+	if ((IS_SKYLAKE(dev_priv) ||
475
+	     IS_KABYLAKE(dev_priv) ||
476
+	     IS_COFFEELAKE(dev_priv) ||
477
+	     IS_COMETLAKE(dev_priv)) &&
316
478
 			intel_vgpu_has_monitor_on_port(vgpu, PORT_E)) {
317
479
 		vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTE_HOTPLUG_SPT;
318
480
 	}
..
..
@@ -356,9 +518,10 @@
356
518
 static int setup_virtual_dp_monitor(struct intel_vgpu *vgpu, int port_num,
357
519
 				    int type, unsigned int resolution)
358
520
 {
521
+	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
359
522
 	struct intel_vgpu_port *port = intel_vgpu_port(vgpu, port_num);
360
523
 
361
-	if (WARN_ON(resolution >= GVT_EDID_NUM))
524
+	if (drm_WARN_ON(&i915->drm, resolution >= GVT_EDID_NUM))
362
525
 		return -EINVAL;
363
526
 
364
527
 	port->edid = kzalloc(sizeof(*(port->edid)), GFP_KERNEL);
..
..
@@ -379,6 +542,7 @@
379
542
 	port->dpcd->data_valid = true;
380
543
 	port->dpcd->data[DPCD_SINK_COUNT] = 0x1;
381
544
 	port->type = type;
545
+	port->id = resolution;
382
546
 
383
547
 	emulate_monitor_status_change(vgpu);
384
548
 
..
..
@@ -425,7 +589,7 @@
425
589
 
426
590
 static void emulate_vblank_on_pipe(struct intel_vgpu *vgpu, int pipe)
427
591
 {
428
-	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
592
+	struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
429
593
 	struct intel_vgpu_irq *irq = &vgpu->irq;
430
594
 	int vblank_event[] = {
431
595
 		[PIPE_A] = PIPE_A_VBLANK,
..
..
@@ -443,7 +607,6 @@
443
607
 		if (!pipe_is_enabled(vgpu, pipe))
444
608
 			continue;
445
609
 
446
-		vgpu_vreg_t(vgpu, PIPE_FLIPCOUNT_G4X(pipe))++;
447
610
 		intel_vgpu_trigger_virtual_event(vgpu, event);
448
611
 	}
449
612
 
..
..
@@ -458,7 +621,7 @@
458
621
 	int pipe;
459
622
 
460
623
 	mutex_lock(&vgpu->vgpu_lock);
461
-	for_each_pipe(vgpu->gvt->dev_priv, pipe)
624
+	for_each_pipe(vgpu->gvt->gt->i915, pipe)
462
625
 		emulate_vblank_on_pipe(vgpu, pipe);
463
626
 	mutex_unlock(&vgpu->vgpu_lock);
464
627
 }
..
..
@@ -482,6 +645,96 @@
482
645
 }
483
646
 
484
647
 /**
648
+ * intel_vgpu_emulate_hotplug - trigger hotplug event for vGPU
649
+ * @vgpu: a vGPU
650
+ * @connected: link state
651
+ *
652
+ * This function is used to trigger hotplug interrupt for vGPU
653
+ *
654
+ */
655
+void intel_vgpu_emulate_hotplug(struct intel_vgpu *vgpu, bool connected)
656
+{
657
+	struct drm_i915_private *i915 = vgpu->gvt->gt->i915;
658
+
659
+	/* TODO: add more platforms support */
660
+	if (IS_SKYLAKE(i915) ||
661
+	    IS_KABYLAKE(i915) ||
662
+	    IS_COFFEELAKE(i915) ||
663
+	    IS_COMETLAKE(i915)) {
664
+		if (connected) {
665
+			vgpu_vreg_t(vgpu, SFUSE_STRAP) |=
666
+				SFUSE_STRAP_DDID_DETECTED;
667
+			vgpu_vreg_t(vgpu, SDEISR) |= SDE_PORTD_HOTPLUG_CPT;
668
+		} else {
669
+			vgpu_vreg_t(vgpu, SFUSE_STRAP) &=
670
+				~SFUSE_STRAP_DDID_DETECTED;
671
+			vgpu_vreg_t(vgpu, SDEISR) &= ~SDE_PORTD_HOTPLUG_CPT;
672
+		}
673
+		vgpu_vreg_t(vgpu, SDEIIR) |= SDE_PORTD_HOTPLUG_CPT;
674
+		vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
675
+				PORTD_HOTPLUG_STATUS_MASK;
676
+		intel_vgpu_trigger_virtual_event(vgpu, DP_D_HOTPLUG);
677
+	} else if (IS_BROXTON(i915)) {
678
+		if (intel_vgpu_has_monitor_on_port(vgpu, PORT_A)) {
679
+			if (connected) {
680
+				vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
681
+					BXT_DE_PORT_HP_DDIA;
682
+			} else {
683
+				vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=
684
+					~BXT_DE_PORT_HP_DDIA;
685
+			}
686
+			vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |=
687
+				BXT_DE_PORT_HP_DDIA;
688
+			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
689
+				~PORTA_HOTPLUG_STATUS_MASK;
690
+			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
691
+				PORTA_HOTPLUG_LONG_DETECT;
692
+			intel_vgpu_trigger_virtual_event(vgpu, DP_A_HOTPLUG);
693
+		}
694
+		if (intel_vgpu_has_monitor_on_port(vgpu, PORT_B)) {
695
+			if (connected) {
696
+				vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
697
+					BXT_DE_PORT_HP_DDIB;
698
+				vgpu_vreg_t(vgpu, SFUSE_STRAP) |=
699
+					SFUSE_STRAP_DDIB_DETECTED;
700
+			} else {
701
+				vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=
702
+					~BXT_DE_PORT_HP_DDIB;
703
+				vgpu_vreg_t(vgpu, SFUSE_STRAP) &=
704
+					~SFUSE_STRAP_DDIB_DETECTED;
705
+			}
706
+			vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |=
707
+				BXT_DE_PORT_HP_DDIB;
708
+			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
709
+				~PORTB_HOTPLUG_STATUS_MASK;
710
+			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
711
+				PORTB_HOTPLUG_LONG_DETECT;
712
+			intel_vgpu_trigger_virtual_event(vgpu, DP_B_HOTPLUG);
713
+		}
714
+		if (intel_vgpu_has_monitor_on_port(vgpu, PORT_C)) {
715
+			if (connected) {
716
+				vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) |=
717
+					BXT_DE_PORT_HP_DDIC;
718
+				vgpu_vreg_t(vgpu, SFUSE_STRAP) |=
719
+					SFUSE_STRAP_DDIC_DETECTED;
720
+			} else {
721
+				vgpu_vreg_t(vgpu, GEN8_DE_PORT_ISR) &=
722
+					~BXT_DE_PORT_HP_DDIC;
723
+				vgpu_vreg_t(vgpu, SFUSE_STRAP) &=
724
+					~SFUSE_STRAP_DDIC_DETECTED;
725
+			}
726
+			vgpu_vreg_t(vgpu, GEN8_DE_PORT_IIR) |=
727
+				BXT_DE_PORT_HP_DDIC;
728
+			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) &=
729
+				~PORTC_HOTPLUG_STATUS_MASK;
730
+			vgpu_vreg_t(vgpu, PCH_PORT_HOTPLUG) |=
731
+				PORTC_HOTPLUG_LONG_DETECT;
732
+			intel_vgpu_trigger_virtual_event(vgpu, DP_C_HOTPLUG);
733
+		}
734
+	}
735
+}
736
+
737
+/**
485
738
  * intel_vgpu_clean_display - clean vGPU virtual display emulation
486
739
  * @vgpu: a vGPU
487
740
  *
..
..
@@ -490,9 +743,12 @@
490
743
  */
491
744
 void intel_vgpu_clean_display(struct intel_vgpu *vgpu)
492
745
 {
493
-	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
746
+	struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
494
747
 
495
-	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
748
+	if (IS_SKYLAKE(dev_priv) ||
749
+	    IS_KABYLAKE(dev_priv) ||
750
+	    IS_COFFEELAKE(dev_priv) ||
751
+	    IS_COMETLAKE(dev_priv))
496
752
 		clean_virtual_dp_monitor(vgpu, PORT_D);
497
753
 	else
498
754
 		clean_virtual_dp_monitor(vgpu, PORT_B);
..
..
@@ -501,6 +757,7 @@
501
757
 /**
502
758
  * intel_vgpu_init_display- initialize vGPU virtual display emulation
503
759
  * @vgpu: a vGPU
760
+ * @resolution: resolution index for intel_vgpu_edid
504
761
  *
505
762
  * This function is used to initialize vGPU virtual display emulation stuffs
506
763
  *
..
..
@@ -510,11 +767,14 @@
510
767
  */
511
768
 int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution)
512
769
 {
513
-	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
770
+	struct drm_i915_private *dev_priv = vgpu->gvt->gt->i915;
514
771
 
515
772
 	intel_vgpu_init_i2c_edid(vgpu);
516
773
 
517
-	if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
774
+	if (IS_SKYLAKE(dev_priv) ||
775
+	    IS_KABYLAKE(dev_priv) ||
776
+	    IS_COFFEELAKE(dev_priv) ||
777
+	    IS_COMETLAKE(dev_priv))
518
778
 		return setup_virtual_dp_monitor(vgpu, PORT_D, GVT_DP_D,
519
779
 						resolution);
520
780
 	else