blame | history | patch | commit | commitdiff
hc
2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf 
 kernel/arch/riscv/include/asm/csr.h
....@@ -1,77 +1,163 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
12 /*
23  * Copyright (C) 2015 Regents of the University of California
3
- *
4
- *   This program is free software; you can redistribute it and/or
5
- *   modify it under the terms of the GNU General Public License
6
- *   as published by the Free Software Foundation, version 2.
7
- *
8
- *   This program is distributed in the hope that it will be useful,
9
- *   but WITHOUT ANY WARRANTY; without even the implied warranty of
10
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11
- *   GNU General Public License for more details.
124  */
135 
146 #ifndef _ASM_RISCV_CSR_H
157 #define _ASM_RISCV_CSR_H
168 
9
+#include <asm/asm.h>
1710 #include <linux/const.h>
1811 
1912 /* Status register flags */
20
-#define SR_SIE	_AC(0x00000002, UL) /* Supervisor Interrupt Enable */
21
-#define SR_SPIE	_AC(0x00000020, UL) /* Previous Supervisor IE */
22
-#define SR_SPP	_AC(0x00000100, UL) /* Previously Supervisor */
23
-#define SR_SUM	_AC(0x00040000, UL) /* Supervisor may access User Memory */
13
+#define SR_SIE		_AC(0x00000002, UL) /* Supervisor Interrupt Enable */
14
+#define SR_MIE		_AC(0x00000008, UL) /* Machine Interrupt Enable */
15
+#define SR_SPIE		_AC(0x00000020, UL) /* Previous Supervisor IE */
16
+#define SR_MPIE		_AC(0x00000080, UL) /* Previous Machine IE */
17
+#define SR_SPP		_AC(0x00000100, UL) /* Previously Supervisor */
18
+#define SR_MPP		_AC(0x00001800, UL) /* Previously Machine */
19
+#define SR_SUM		_AC(0x00040000, UL) /* Supervisor User Memory Access */
2420 
25
-#define SR_FS           _AC(0x00006000, UL) /* Floating-point Status */
26
-#define SR_FS_OFF       _AC(0x00000000, UL)
27
-#define SR_FS_INITIAL   _AC(0x00002000, UL)
28
-#define SR_FS_CLEAN     _AC(0x00004000, UL)
29
-#define SR_FS_DIRTY     _AC(0x00006000, UL)
21
+#define SR_FS		_AC(0x00006000, UL) /* Floating-point Status */
22
+#define SR_FS_OFF	_AC(0x00000000, UL)
23
+#define SR_FS_INITIAL	_AC(0x00002000, UL)
24
+#define SR_FS_CLEAN	_AC(0x00004000, UL)
25
+#define SR_FS_DIRTY	_AC(0x00006000, UL)
3026 
31
-#define SR_XS           _AC(0x00018000, UL) /* Extension Status */
32
-#define SR_XS_OFF       _AC(0x00000000, UL)
33
-#define SR_XS_INITIAL   _AC(0x00008000, UL)
34
-#define SR_XS_CLEAN     _AC(0x00010000, UL)
35
-#define SR_XS_DIRTY     _AC(0x00018000, UL)
27
+#define SR_XS		_AC(0x00018000, UL) /* Extension Status */
28
+#define SR_XS_OFF	_AC(0x00000000, UL)
29
+#define SR_XS_INITIAL	_AC(0x00008000, UL)
30
+#define SR_XS_CLEAN	_AC(0x00010000, UL)
31
+#define SR_XS_DIRTY	_AC(0x00018000, UL)
3632 
3733 #ifndef CONFIG_64BIT
38
-#define SR_SD   _AC(0x80000000, UL) /* FS/XS dirty */
34
+#define SR_SD		_AC(0x80000000, UL) /* FS/XS dirty */
3935 #else
40
-#define SR_SD   _AC(0x8000000000000000, UL) /* FS/XS dirty */
36
+#define SR_SD		_AC(0x8000000000000000, UL) /* FS/XS dirty */
4137 #endif
4238 
4339 /* SATP flags */
44
-#if __riscv_xlen == 32
45
-#define SATP_PPN     _AC(0x003FFFFF, UL)
46
-#define SATP_MODE_32 _AC(0x80000000, UL)
47
-#define SATP_MODE    SATP_MODE_32
40
+#ifndef CONFIG_64BIT
41
+#define SATP_PPN	_AC(0x003FFFFF, UL)
42
+#define SATP_MODE_32	_AC(0x80000000, UL)
43
+#define SATP_MODE	SATP_MODE_32
4844 #else
49
-#define SATP_PPN     _AC(0x00000FFFFFFFFFFF, UL)
50
-#define SATP_MODE_39 _AC(0x8000000000000000, UL)
51
-#define SATP_MODE    SATP_MODE_39
45
+#define SATP_PPN	_AC(0x00000FFFFFFFFFFF, UL)
46
+#define SATP_MODE_39	_AC(0x8000000000000000, UL)
47
+#define SATP_MODE	SATP_MODE_39
5248 #endif
5349 
54
-/* Interrupt Enable and Interrupt Pending flags */
55
-#define SIE_SSIE _AC(0x00000002, UL) /* Software Interrupt Enable */
56
-#define SIE_STIE _AC(0x00000020, UL) /* Timer Interrupt Enable */
57
-#define SIE_SEIE _AC(0x00000200, UL) /* External Interrupt Enable */
50
+/* Exception cause high bit - is an interrupt if set */
51
+#define CAUSE_IRQ_FLAG		(_AC(1, UL) << (__riscv_xlen - 1))
5852 
59
-#define EXC_INST_MISALIGNED     0
60
-#define EXC_INST_ACCESS         1
61
-#define EXC_BREAKPOINT          3
62
-#define EXC_LOAD_ACCESS         5
63
-#define EXC_STORE_ACCESS        7
64
-#define EXC_SYSCALL             8
65
-#define EXC_INST_PAGE_FAULT     12
66
-#define EXC_LOAD_PAGE_FAULT     13
67
-#define EXC_STORE_PAGE_FAULT    15
53
+/* Interrupt causes (minus the high bit) */
54
+#define IRQ_S_SOFT		1
55
+#define IRQ_M_SOFT		3
56
+#define IRQ_S_TIMER		5
57
+#define IRQ_M_TIMER		7
58
+#define IRQ_S_EXT		9
59
+#define IRQ_M_EXT		11
60
+
61
+/* Exception causes */
62
+#define EXC_INST_MISALIGNED	0
63
+#define EXC_INST_ACCESS		1
64
+#define EXC_BREAKPOINT		3
65
+#define EXC_LOAD_ACCESS		5
66
+#define EXC_STORE_ACCESS	7
67
+#define EXC_SYSCALL		8
68
+#define EXC_INST_PAGE_FAULT	12
69
+#define EXC_LOAD_PAGE_FAULT	13
70
+#define EXC_STORE_PAGE_FAULT	15
71
+
72
+/* PMP configuration */
73
+#define PMP_R			0x01
74
+#define PMP_W			0x02
75
+#define PMP_X			0x04
76
+#define PMP_A			0x18
77
+#define PMP_A_TOR		0x08
78
+#define PMP_A_NA4		0x10
79
+#define PMP_A_NAPOT		0x18
80
+#define PMP_L			0x80
81
+
82
+/* symbolic CSR names: */
83
+#define CSR_CYCLE		0xc00
84
+#define CSR_TIME		0xc01
85
+#define CSR_INSTRET		0xc02
86
+#define CSR_CYCLEH		0xc80
87
+#define CSR_TIMEH		0xc81
88
+#define CSR_INSTRETH		0xc82
89
+
90
+#define CSR_SSTATUS		0x100
91
+#define CSR_SIE			0x104
92
+#define CSR_STVEC		0x105
93
+#define CSR_SCOUNTEREN		0x106
94
+#define CSR_SSCRATCH		0x140
95
+#define CSR_SEPC		0x141
96
+#define CSR_SCAUSE		0x142
97
+#define CSR_STVAL		0x143
98
+#define CSR_SIP			0x144
99
+#define CSR_SATP		0x180
100
+
101
+#define CSR_MSTATUS		0x300
102
+#define CSR_MISA		0x301
103
+#define CSR_MIE			0x304
104
+#define CSR_MTVEC		0x305
105
+#define CSR_MSCRATCH		0x340
106
+#define CSR_MEPC		0x341
107
+#define CSR_MCAUSE		0x342
108
+#define CSR_MTVAL		0x343
109
+#define CSR_MIP			0x344
110
+#define CSR_PMPCFG0		0x3a0
111
+#define CSR_PMPADDR0		0x3b0
112
+#define CSR_MHARTID		0xf14
113
+
114
+#ifdef CONFIG_RISCV_M_MODE
115
+# define CSR_STATUS	CSR_MSTATUS
116
+# define CSR_IE		CSR_MIE
117
+# define CSR_TVEC	CSR_MTVEC
118
+# define CSR_SCRATCH	CSR_MSCRATCH
119
+# define CSR_EPC	CSR_MEPC
120
+# define CSR_CAUSE	CSR_MCAUSE
121
+# define CSR_TVAL	CSR_MTVAL
122
+# define CSR_IP		CSR_MIP
123
+
124
+# define SR_IE		SR_MIE
125
+# define SR_PIE		SR_MPIE
126
+# define SR_PP		SR_MPP
127
+
128
+# define RV_IRQ_SOFT		IRQ_M_SOFT
129
+# define RV_IRQ_TIMER	IRQ_M_TIMER
130
+# define RV_IRQ_EXT		IRQ_M_EXT
131
+#else /* CONFIG_RISCV_M_MODE */
132
+# define CSR_STATUS	CSR_SSTATUS
133
+# define CSR_IE		CSR_SIE
134
+# define CSR_TVEC	CSR_STVEC
135
+# define CSR_SCRATCH	CSR_SSCRATCH
136
+# define CSR_EPC	CSR_SEPC
137
+# define CSR_CAUSE	CSR_SCAUSE
138
+# define CSR_TVAL	CSR_STVAL
139
+# define CSR_IP		CSR_SIP
140
+
141
+# define SR_IE		SR_SIE
142
+# define SR_PIE		SR_SPIE
143
+# define SR_PP		SR_SPP
144
+
145
+# define RV_IRQ_SOFT		IRQ_S_SOFT
146
+# define RV_IRQ_TIMER	IRQ_S_TIMER
147
+# define RV_IRQ_EXT		IRQ_S_EXT
148
+#endif /* CONFIG_RISCV_M_MODE */
149
+
150
+/* IE/IP (Supervisor/Machine Interrupt Enable/Pending) flags */
151
+#define IE_SIE		(_AC(0x1, UL) << RV_IRQ_SOFT)
152
+#define IE_TIE		(_AC(0x1, UL) << RV_IRQ_TIMER)
153
+#define IE_EIE		(_AC(0x1, UL) << RV_IRQ_EXT)
68154 
69155 #ifndef __ASSEMBLY__
70156 
71157 #define csr_swap(csr, val)					\
72158 ({								\
73159 	unsigned long __v = (unsigned long)(val);		\
74
-	__asm__ __volatile__ ("csrrw %0, " #csr ", %1"		\
160
+	__asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\
75161 			      : "=r" (__v) : "rK" (__v)		\
76162 			      : "memory");			\
77163 	__v;							\
....@@ -80,7 +166,7 @@
80166 #define csr_read(csr)						\
81167 ({								\
82168 	register unsigned long __v;				\
83
-	__asm__ __volatile__ ("csrr %0, " #csr			\
169
+	__asm__ __volatile__ ("csrr %0, " __ASM_STR(csr)	\
84170 			      : "=r" (__v) :			\
85171 			      : "memory");			\
86172 	__v;							\
....@@ -89,7 +175,7 @@
89175 #define csr_write(csr, val)					\
90176 ({								\
91177 	unsigned long __v = (unsigned long)(val);		\
92
-	__asm__ __volatile__ ("csrw " #csr ", %0"		\
178
+	__asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0"	\
93179 			      : : "rK" (__v)			\
94180 			      : "memory");			\
95181 })
....@@ -97,7 +183,7 @@
97183 #define csr_read_set(csr, val)					\
98184 ({								\
99185 	unsigned long __v = (unsigned long)(val);		\
100
-	__asm__ __volatile__ ("csrrs %0, " #csr ", %1"		\
186
+	__asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\
101187 			      : "=r" (__v) : "rK" (__v)		\
102188 			      : "memory");			\
103189 	__v;							\
....@@ -106,7 +192,7 @@
106192 #define csr_set(csr, val)					\
107193 ({								\
108194 	unsigned long __v = (unsigned long)(val);		\
109
-	__asm__ __volatile__ ("csrs " #csr ", %0"		\
195
+	__asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0"	\
110196 			      : : "rK" (__v)			\
111197 			      : "memory");			\
112198 })
....@@ -114,7 +200,7 @@
114200 #define csr_read_clear(csr, val)				\
115201 ({								\
116202 	unsigned long __v = (unsigned long)(val);		\
117
-	__asm__ __volatile__ ("csrrc %0, " #csr ", %1"		\
203
+	__asm__ __volatile__ ("csrrc %0, " __ASM_STR(csr) ", %1"\
118204 			      : "=r" (__v) : "rK" (__v)		\
119205 			      : "memory");			\
120206 	__v;							\
....@@ -123,7 +209,7 @@
123209 #define csr_clear(csr, val)					\
124210 ({								\
125211 	unsigned long __v = (unsigned long)(val);		\
126
-	__asm__ __volatile__ ("csrc " #csr ", %0"		\
212
+	__asm__ __volatile__ ("csrc " __ASM_STR(csr) ", %0"	\
127213 			      : : "rK" (__v)			\
128214 			      : "memory");			\
129215 })