blame | history | patch | commit | commitdiff
hc
2024-01-03 2f7c68cb55ecb7331f2381deb497c27155f32faf 
 kernel/arch/arm64/include/asm/esr.h
....@@ -1,18 +1,7 @@
1
+/* SPDX-License-Identifier: GPL-2.0-only */
12 /*
23  * Copyright (C) 2013 - ARM Ltd
34  * Author: Marc Zyngier <marc.zyngier@arm.com>
4
- *
5
- * This program is free software; you can redistribute it and/or modify
6
- * it under the terms of the GNU General Public License version 2 as
7
- * published by the Free Software Foundation.
8
- *
9
- * This program is distributed in the hope that it will be useful,
10
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
11
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12
- * GNU General Public License for more details.
13
- *
14
- * You should have received a copy of the GNU General Public License
15
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
165  */
176 
187 #ifndef __ASM_ESR_H
....@@ -29,23 +18,27 @@
2918 #define ESR_ELx_EC_CP14_MR	(0x05)
3019 #define ESR_ELx_EC_CP14_LS	(0x06)
3120 #define ESR_ELx_EC_FP_ASIMD	(0x07)
32
-#define ESR_ELx_EC_CP10_ID	(0x08)
33
-/* Unallocated EC: 0x09 - 0x0B */
21
+#define ESR_ELx_EC_CP10_ID	(0x08)	/* EL2 only */
22
+#define ESR_ELx_EC_PAC		(0x09)	/* EL2 and above */
23
+/* Unallocated EC: 0x0A - 0x0B */
3424 #define ESR_ELx_EC_CP14_64	(0x0C)
35
-/* Unallocated EC: 0x0d */
25
+#define ESR_ELx_EC_BTI		(0x0D)
3626 #define ESR_ELx_EC_ILL		(0x0E)
3727 /* Unallocated EC: 0x0F - 0x10 */
3828 #define ESR_ELx_EC_SVC32	(0x11)
39
-#define ESR_ELx_EC_HVC32	(0x12)
40
-#define ESR_ELx_EC_SMC32	(0x13)
29
+#define ESR_ELx_EC_HVC32	(0x12)	/* EL2 only */
30
+#define ESR_ELx_EC_SMC32	(0x13)	/* EL2 and above */
4131 /* Unallocated EC: 0x14 */
4232 #define ESR_ELx_EC_SVC64	(0x15)
43
-#define ESR_ELx_EC_HVC64	(0x16)
44
-#define ESR_ELx_EC_SMC64	(0x17)
33
+#define ESR_ELx_EC_HVC64	(0x16)	/* EL2 and above */
34
+#define ESR_ELx_EC_SMC64	(0x17)	/* EL2 and above */
4535 #define ESR_ELx_EC_SYS64	(0x18)
4636 #define ESR_ELx_EC_SVE		(0x19)
47
-/* Unallocated EC: 0x1A - 0x1E */
48
-#define ESR_ELx_EC_IMP_DEF	(0x1f)
37
+#define ESR_ELx_EC_ERET		(0x1a)	/* EL2 only */
38
+/* Unallocated EC: 0x1B */
39
+#define ESR_ELx_EC_FPAC		(0x1C)	/* EL1 and above */
40
+/* Unallocated EC: 0x1D - 0x1E */
41
+#define ESR_ELx_EC_IMP_DEF	(0x1f)	/* EL3 only */
4942 #define ESR_ELx_EC_IABT_LOW	(0x20)
5043 #define ESR_ELx_EC_IABT_CUR	(0x21)
5144 #define ESR_ELx_EC_PC_ALIGN	(0x22)
....@@ -68,13 +61,14 @@
6861 /* Unallocated EC: 0x36 - 0x37 */
6962 #define ESR_ELx_EC_BKPT32	(0x38)
7063 /* Unallocated EC: 0x39 */
71
-#define ESR_ELx_EC_VECTOR32	(0x3A)
72
-/* Unallocted EC: 0x3B */
64
+#define ESR_ELx_EC_VECTOR32	(0x3A)	/* EL2 only */
65
+/* Unallocated EC: 0x3B */
7366 #define ESR_ELx_EC_BRK64	(0x3C)
7467 /* Unallocated EC: 0x3D - 0x3F */
7568 #define ESR_ELx_EC_MAX		(0x3F)
7669 
7770 #define ESR_ELx_EC_SHIFT	(26)
71
+#define ESR_ELx_EC_WIDTH	(6)
7872 #define ESR_ELx_EC_MASK		(UL(0x3F) << ESR_ELx_EC_SHIFT)
7973 #define ESR_ELx_EC(esr)		(((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT)
8074 
....@@ -111,11 +105,14 @@
111105 /* Shared ISS fault status code(IFSC/DFSC) for Data/Instruction aborts */
112106 #define ESR_ELx_FSC		(0x3F)
113107 #define ESR_ELx_FSC_TYPE	(0x3C)
108
+#define ESR_ELx_FSC_LEVEL	(0x03)
114109 #define ESR_ELx_FSC_EXTABT	(0x10)
110
+#define ESR_ELx_FSC_MTE		(0x11)
115111 #define ESR_ELx_FSC_SERROR	(0x11)
116112 #define ESR_ELx_FSC_ACCESS	(0x08)
117113 #define ESR_ELx_FSC_FAULT	(0x04)
118114 #define ESR_ELx_FSC_PERM	(0x0C)
115
+#define ESR_ELx_FSC_TLBCONF	(0x30)
119116 
120117 /* ISS field definitions for Data Aborts */
121118 #define ESR_ELx_ISV_SHIFT	(24)
....@@ -137,6 +134,8 @@
137134 #define ESR_ELx_CV		(UL(1) << 24)
138135 #define ESR_ELx_COND_SHIFT	(20)
139136 #define ESR_ELx_COND_MASK	(UL(0xF) << ESR_ELx_COND_SHIFT)
137
+#define ESR_ELx_WFx_ISS_TI	(UL(1) << 0)
138
+#define ESR_ELx_WFx_ISS_WFI	(UL(0) << 0)
140139 #define ESR_ELx_WFx_ISS_WFE	(UL(1) << 0)
141140 #define ESR_ELx_xVC_IMM_MASK	((1UL << 16) - 1)
142141 
....@@ -148,11 +147,12 @@
148147 #define DISR_EL1_ESR_MASK	(ESR_ELx_AET | ESR_ELx_EA | ESR_ELx_FSC)
149148 
150149 /* ESR value templates for specific events */
150
+#define ESR_ELx_WFx_MASK	(ESR_ELx_EC_MASK | ESR_ELx_WFx_ISS_TI)
151
+#define ESR_ELx_WFx_WFI_VAL	((ESR_ELx_EC_WFx << ESR_ELx_EC_SHIFT) |	\
152
+				 ESR_ELx_WFx_ISS_WFI)
151153 
152154 /* BRK instruction trap from AArch64 state */
153
-#define ESR_ELx_VAL_BRK64(imm)					\
154
-	((ESR_ELx_EC_BRK64 << ESR_ELx_EC_SHIFT) | ESR_ELx_IL |	\
155
-	 ((imm) & 0xffff))
155
+#define ESR_ELx_BRK64_ISS_COMMENT_MASK	0xffff
156156 
157157 /* ISS field definitions for System instruction traps */
158158 #define ESR_ELx_SYS64_ISS_RES0_SHIFT	22
....@@ -187,12 +187,15 @@
187187 
188188 #define ESR_ELx_SYS64_ISS_SYS_OP_MASK	(ESR_ELx_SYS64_ISS_SYS_MASK | \
189189 					 ESR_ELx_SYS64_ISS_DIR_MASK)
190
+#define ESR_ELx_SYS64_ISS_RT(esr) \
191
+	(((esr) & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT)
190192 /*
191193  * User space cache operations have the following sysreg encoding
192194  * in System instructions.
193
- * op0=1, op1=3, op2=1, crn=7, crm={ 5, 10, 11, 12, 14 }, WRITE (L=0)
195
+ * op0=1, op1=3, op2=1, crn=7, crm={ 5, 10, 11, 12, 13, 14 }, WRITE (L=0)
194196  */
195197 #define ESR_ELx_SYS64_ISS_CRM_DC_CIVAC	14
198
+#define ESR_ELx_SYS64_ISS_CRM_DC_CVADP	13
196199 #define ESR_ELx_SYS64_ISS_CRM_DC_CVAP	12
197200 #define ESR_ELx_SYS64_ISS_CRM_DC_CVAU	11
198201 #define ESR_ELx_SYS64_ISS_CRM_DC_CVAC	10
....@@ -206,6 +209,18 @@
206209 #define ESR_ELx_SYS64_ISS_EL0_CACHE_OP_VAL \
207210 				(ESR_ELx_SYS64_ISS_SYS_VAL(1, 3, 1, 7, 0) | \
208211 				 ESR_ELx_SYS64_ISS_DIR_WRITE)
212
+/*
213
+ * User space MRS operations which are supported for emulation
214
+ * have the following sysreg encoding in System instructions.
215
+ * op0 = 3, op1= 0, crn = 0, {crm = 0, 4-7}, READ (L = 1)
216
+ */
217
+#define ESR_ELx_SYS64_ISS_SYS_MRS_OP_MASK	(ESR_ELx_SYS64_ISS_OP0_MASK | \
218
+						 ESR_ELx_SYS64_ISS_OP1_MASK | \
219
+						 ESR_ELx_SYS64_ISS_CRN_MASK | \
220
+						 ESR_ELx_SYS64_ISS_DIR_MASK)
221
+#define ESR_ELx_SYS64_ISS_SYS_MRS_OP_VAL \
222
+				(ESR_ELx_SYS64_ISS_SYS_VAL(3, 0, 0, 0, 0) | \
223
+				 ESR_ELx_SYS64_ISS_DIR_READ)
209224 
210225 #define ESR_ELx_SYS64_ISS_SYS_CTR	ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 1, 0, 0)
211226 #define ESR_ELx_SYS64_ISS_SYS_CTR_READ	(ESR_ELx_SYS64_ISS_SYS_CTR | \
....@@ -249,6 +264,64 @@
249264 
250265 #define ESR_ELx_FP_EXC_TFV	(UL(1) << 23)
251266 
267
+/*
268
+ * ISS field definitions for CP15 accesses
269
+ */
270
+#define ESR_ELx_CP15_32_ISS_DIR_MASK	0x1
271
+#define ESR_ELx_CP15_32_ISS_DIR_READ	0x1
272
+#define ESR_ELx_CP15_32_ISS_DIR_WRITE	0x0
273
+
274
+#define ESR_ELx_CP15_32_ISS_RT_SHIFT	5
275
+#define ESR_ELx_CP15_32_ISS_RT_MASK	(UL(0x1f) << ESR_ELx_CP15_32_ISS_RT_SHIFT)
276
+#define ESR_ELx_CP15_32_ISS_CRM_SHIFT	1
277
+#define ESR_ELx_CP15_32_ISS_CRM_MASK	(UL(0xf) << ESR_ELx_CP15_32_ISS_CRM_SHIFT)
278
+#define ESR_ELx_CP15_32_ISS_CRN_SHIFT	10
279
+#define ESR_ELx_CP15_32_ISS_CRN_MASK	(UL(0xf) << ESR_ELx_CP15_32_ISS_CRN_SHIFT)
280
+#define ESR_ELx_CP15_32_ISS_OP1_SHIFT	14
281
+#define ESR_ELx_CP15_32_ISS_OP1_MASK	(UL(0x7) << ESR_ELx_CP15_32_ISS_OP1_SHIFT)
282
+#define ESR_ELx_CP15_32_ISS_OP2_SHIFT	17
283
+#define ESR_ELx_CP15_32_ISS_OP2_MASK	(UL(0x7) << ESR_ELx_CP15_32_ISS_OP2_SHIFT)
284
+
285
+#define ESR_ELx_CP15_32_ISS_SYS_MASK	(ESR_ELx_CP15_32_ISS_OP1_MASK | \
286
+					 ESR_ELx_CP15_32_ISS_OP2_MASK | \
287
+					 ESR_ELx_CP15_32_ISS_CRN_MASK | \
288
+					 ESR_ELx_CP15_32_ISS_CRM_MASK | \
289
+					 ESR_ELx_CP15_32_ISS_DIR_MASK)
290
+#define ESR_ELx_CP15_32_ISS_SYS_VAL(op1, op2, crn, crm) \
291
+					(((op1) << ESR_ELx_CP15_32_ISS_OP1_SHIFT) | \
292
+					 ((op2) << ESR_ELx_CP15_32_ISS_OP2_SHIFT) | \
293
+					 ((crn) << ESR_ELx_CP15_32_ISS_CRN_SHIFT) | \
294
+					 ((crm) << ESR_ELx_CP15_32_ISS_CRM_SHIFT))
295
+
296
+#define ESR_ELx_CP15_64_ISS_DIR_MASK	0x1
297
+#define ESR_ELx_CP15_64_ISS_DIR_READ	0x1
298
+#define ESR_ELx_CP15_64_ISS_DIR_WRITE	0x0
299
+
300
+#define ESR_ELx_CP15_64_ISS_RT_SHIFT	5
301
+#define ESR_ELx_CP15_64_ISS_RT_MASK	(UL(0x1f) << ESR_ELx_CP15_64_ISS_RT_SHIFT)
302
+
303
+#define ESR_ELx_CP15_64_ISS_RT2_SHIFT	10
304
+#define ESR_ELx_CP15_64_ISS_RT2_MASK	(UL(0x1f) << ESR_ELx_CP15_64_ISS_RT2_SHIFT)
305
+
306
+#define ESR_ELx_CP15_64_ISS_OP1_SHIFT	16
307
+#define ESR_ELx_CP15_64_ISS_OP1_MASK	(UL(0xf) << ESR_ELx_CP15_64_ISS_OP1_SHIFT)
308
+#define ESR_ELx_CP15_64_ISS_CRM_SHIFT	1
309
+#define ESR_ELx_CP15_64_ISS_CRM_MASK	(UL(0xf) << ESR_ELx_CP15_64_ISS_CRM_SHIFT)
310
+
311
+#define ESR_ELx_CP15_64_ISS_SYS_VAL(op1, crm) \
312
+					(((op1) << ESR_ELx_CP15_64_ISS_OP1_SHIFT) | \
313
+					 ((crm) << ESR_ELx_CP15_64_ISS_CRM_SHIFT))
314
+
315
+#define ESR_ELx_CP15_64_ISS_SYS_MASK	(ESR_ELx_CP15_64_ISS_OP1_MASK |	\
316
+					 ESR_ELx_CP15_64_ISS_CRM_MASK | \
317
+					 ESR_ELx_CP15_64_ISS_DIR_MASK)
318
+
319
+#define ESR_ELx_CP15_64_ISS_SYS_CNTVCT	(ESR_ELx_CP15_64_ISS_SYS_VAL(1, 14) | \
320
+					 ESR_ELx_CP15_64_ISS_DIR_READ)
321
+
322
+#define ESR_ELx_CP15_32_ISS_SYS_CNTFRQ	(ESR_ELx_CP15_32_ISS_SYS_VAL(0, 0, 14, 0) |\
323
+					 ESR_ELx_CP15_32_ISS_DIR_READ)
324
+
252325 #ifndef __ASSEMBLY__
253326 #include <asm/types.h>
254327