.. | .. |
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5 | 5 | |
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6 | 6 | #include <dt-bindings/sound/qcom,q6afe.h> |
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7 | 7 | |
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8 | | -#define AFE_PORT_MAX 105 |
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| 8 | +#define AFE_PORT_MAX 127 |
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9 | 9 | |
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10 | 10 | #define MSM_AFE_PORT_TYPE_RX 0 |
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11 | 11 | #define MSM_AFE_PORT_TYPE_TX 1 |
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133 | 133 | /* Clock ID for INT MCLK1 */ |
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134 | 134 | #define Q6AFE_LPASS_CLK_ID_INT_MCLK_1 0x306 |
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135 | 135 | |
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| 136 | +#define Q6AFE_LPASS_CLK_ID_WSA_CORE_MCLK 0x309 |
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| 137 | +#define Q6AFE_LPASS_CLK_ID_WSA_CORE_NPL_MCLK 0x30a |
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| 138 | +#define Q6AFE_LPASS_CLK_ID_TX_CORE_MCLK 0x30c |
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| 139 | +#define Q6AFE_LPASS_CLK_ID_TX_CORE_NPL_MCLK 0x30d |
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| 140 | +#define Q6AFE_LPASS_CLK_ID_RX_CORE_MCLK 0x30e |
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| 141 | +#define Q6AFE_LPASS_CLK_ID_RX_CORE_NPL_MCLK 0x30f |
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| 142 | +#define Q6AFE_LPASS_CLK_ID_VA_CORE_MCLK 0x30b |
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| 143 | +#define Q6AFE_LPASS_CLK_ID_VA_CORE_2X_MCLK 0x310 |
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| 144 | + |
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| 145 | +#define Q6AFE_LPASS_CORE_AVTIMER_BLOCK 0x2 |
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| 146 | +#define Q6AFE_LPASS_CORE_HW_MACRO_BLOCK 0x3 |
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| 147 | +#define Q6AFE_LPASS_CORE_HW_DCODEC_BLOCK 0x4 |
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| 148 | + |
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136 | 149 | /* Clock attribute for invalid use (reserved for internal usage) */ |
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137 | 150 | #define Q6AFE_LPASS_CLK_ATTRIBUTE_INVALID 0x0 |
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138 | 151 | /* Clock attribute for no couple case */ |
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184 | 197 | u16 ch_mapping[AFE_MAX_CHAN_COUNT]; |
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185 | 198 | }; |
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186 | 199 | |
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| 200 | +struct q6afe_cdc_dma_cfg { |
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| 201 | + u16 sample_rate; |
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| 202 | + u16 bit_width; |
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| 203 | + u16 data_format; |
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| 204 | + u16 num_channels; |
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| 205 | + u16 active_channels_mask; |
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| 206 | +}; |
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| 207 | + |
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| 208 | + |
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187 | 209 | struct q6afe_port_config { |
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188 | 210 | struct q6afe_hdmi_cfg hdmi; |
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189 | 211 | struct q6afe_slim_cfg slim; |
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190 | 212 | struct q6afe_i2s_cfg i2s_cfg; |
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191 | 213 | struct q6afe_tdm_cfg tdm; |
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| 214 | + struct q6afe_cdc_dma_cfg dma_cfg; |
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192 | 215 | }; |
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193 | 216 | |
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194 | 217 | struct q6afe_port; |
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.. | .. |
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204 | 227 | struct q6afe_slim_cfg *cfg); |
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205 | 228 | int q6afe_i2s_port_prepare(struct q6afe_port *port, struct q6afe_i2s_cfg *cfg); |
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206 | 229 | void q6afe_tdm_port_prepare(struct q6afe_port *port, struct q6afe_tdm_cfg *cfg); |
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| 230 | +void q6afe_cdc_dma_port_prepare(struct q6afe_port *port, |
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| 231 | + struct q6afe_cdc_dma_cfg *cfg); |
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207 | 232 | |
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208 | 233 | int q6afe_port_set_sysclk(struct q6afe_port *port, int clk_id, |
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209 | 234 | int clk_src, int clk_root, |
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210 | 235 | unsigned int freq, int dir); |
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| 236 | +int q6afe_set_lpass_clock(struct device *dev, int clk_id, int clk_src, |
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| 237 | + int clk_root, unsigned int freq); |
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| 238 | +int q6afe_vote_lpass_core_hw(struct device *dev, uint32_t hw_block_id, |
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| 239 | + char *client_name, uint32_t *client_handle); |
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| 240 | +int q6afe_unvote_lpass_core_hw(struct device *dev, uint32_t hw_block_id, |
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| 241 | + uint32_t client_handle); |
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211 | 242 | #endif /* __Q6AFE_H__ */ |
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