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| 1 | +# SPDX-License-Identifier: GPL-2.0-only |
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1 | 2 | # |
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2 | 3 | # QCOM Soc drivers |
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3 | 4 | # |
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4 | 5 | menu "Qualcomm SoC drivers" |
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| 6 | + |
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| 7 | +config QCOM_AOSS_QMP |
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| 8 | + tristate "Qualcomm AOSS Driver" |
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| 9 | + depends on ARCH_QCOM || COMPILE_TEST |
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| 10 | + depends on MAILBOX |
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| 11 | + depends on COMMON_CLK && PM |
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| 12 | + select PM_GENERIC_DOMAINS |
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| 13 | + help |
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| 14 | + This driver provides the means of communicating with and controlling |
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| 15 | + the low-power state for resources related to the remoteproc |
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| 16 | + subsystems as well as controlling the debug clocks exposed by the Always On |
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| 17 | + Subsystem (AOSS) using Qualcomm Messaging Protocol (QMP). |
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5 | 18 | |
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6 | 19 | config QCOM_COMMAND_DB |
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7 | 20 | tristate "Qualcomm Command DB" |
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.. | .. |
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13 | 26 | resource on a RPM-hardened platform must use this database to get |
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14 | 27 | SoC specific identifier and information for the shared resources. |
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15 | 28 | |
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| 29 | +config QCOM_CPR |
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| 30 | + tristate "QCOM Core Power Reduction (CPR) support" |
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| 31 | + depends on ARCH_QCOM && HAS_IOMEM |
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| 32 | + select PM_OPP |
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| 33 | + select REGMAP |
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| 34 | + help |
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| 35 | + Say Y here to enable support for the CPR hardware found on Qualcomm |
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| 36 | + SoCs like QCS404. |
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| 37 | + |
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| 38 | + This driver populates CPU OPPs tables and makes adjustments to the |
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| 39 | + tables based on feedback from the CPR hardware. If you want to do |
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| 40 | + CPUfrequency scaling say Y here. |
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| 41 | + |
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| 42 | + To compile this driver as a module, choose M here: the module will |
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| 43 | + be called qcom-cpr |
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| 44 | + |
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16 | 45 | config QCOM_GENI_SE |
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17 | 46 | tristate "QCOM GENI Serial Engine Driver" |
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18 | 47 | depends on ARCH_QCOM || COMPILE_TEST |
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.. | .. |
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22 | 51 | driver is also used to manage the common aspects of multiple Serial |
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23 | 52 | Engines present in the QUP. |
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24 | 53 | |
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25 | | -config QCOM_GLINK_SSR |
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26 | | - tristate "Qualcomm Glink SSR driver" |
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27 | | - depends on RPMSG |
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28 | | - depends on QCOM_RPROC_COMMON |
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29 | | - help |
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30 | | - Say y here to enable GLINK SSR support. The GLINK SSR driver |
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31 | | - implements the SSR protocol for notifying the remote processor about |
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32 | | - neighboring subsystems going up or down. |
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33 | | - |
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34 | 54 | config QCOM_GSBI |
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35 | | - tristate "QCOM General Serial Bus Interface" |
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36 | | - depends on ARCH_QCOM |
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37 | | - select MFD_SYSCON |
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38 | | - help |
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39 | | - Say y here to enable GSBI support. The GSBI provides control |
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40 | | - functions for connecting the underlying serial UART, SPI, and I2C |
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41 | | - devices to the output pins. |
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| 55 | + tristate "QCOM General Serial Bus Interface" |
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| 56 | + depends on ARCH_QCOM || COMPILE_TEST |
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| 57 | + select MFD_SYSCON |
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| 58 | + help |
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| 59 | + Say y here to enable GSBI support. The GSBI provides control |
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| 60 | + functions for connecting the underlying serial UART, SPI, and I2C |
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| 61 | + devices to the output pins. |
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42 | 62 | |
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43 | 63 | config QCOM_LLCC |
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44 | 64 | tristate "Qualcomm Technologies, Inc. LLCC driver" |
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45 | | - depends on ARCH_QCOM |
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| 65 | + depends on ARCH_QCOM || COMPILE_TEST |
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46 | 66 | help |
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47 | 67 | Qualcomm Technologies, Inc. platform specific |
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48 | | - Last Level Cache Controller(LLCC) driver. This provides interfaces |
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49 | | - to clients that use the LLCC. Say yes here to enable LLCC slice |
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50 | | - driver. |
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| 68 | + Last Level Cache Controller(LLCC) driver for platforms such as, |
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| 69 | + SDM845. This provides interfaces to clients that use the LLCC. |
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| 70 | + Say yes here to enable LLCC slice driver. |
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51 | 71 | |
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52 | | -config QCOM_SDM845_LLCC |
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53 | | - tristate "Qualcomm Technologies, Inc. SDM845 LLCC driver" |
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54 | | - depends on QCOM_LLCC |
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55 | | - help |
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56 | | - Say yes here to enable the LLCC driver for SDM845. This provides |
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57 | | - data required to configure LLCC so that clients can start using the |
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58 | | - LLCC slices. |
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| 72 | +config QCOM_KRYO_L2_ACCESSORS |
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| 73 | + bool |
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| 74 | + depends on ARCH_QCOM && ARM64 || COMPILE_TEST |
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59 | 75 | |
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60 | 76 | config QCOM_MDT_LOADER |
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61 | 77 | tristate |
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62 | 78 | select QCOM_SCM |
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63 | 79 | |
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64 | | -config QCOM_PM |
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65 | | - bool "Qualcomm Power Management" |
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66 | | - depends on ARCH_QCOM && !ARM64 |
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67 | | - select ARM_CPU_SUSPEND |
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| 80 | +config QCOM_OCMEM |
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| 81 | + tristate "Qualcomm On Chip Memory (OCMEM) driver" |
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| 82 | + depends on ARCH_QCOM |
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68 | 83 | select QCOM_SCM |
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69 | 84 | help |
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70 | | - QCOM Platform specific power driver to manage cores and L2 low power |
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71 | | - modes. It interface with various system drivers to put the cores in |
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72 | | - low power modes. |
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| 85 | + The On Chip Memory (OCMEM) allocator allows various clients to |
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| 86 | + allocate memory from OCMEM based on performance, latency and power |
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| 87 | + requirements. This is typically used by the GPU, camera/video, and |
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| 88 | + audio components on some Snapdragon SoCs. |
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| 89 | + |
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| 90 | +config QCOM_PDR_HELPERS |
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| 91 | + tristate |
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| 92 | + select QCOM_QMI_HELPERS |
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73 | 93 | |
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74 | 94 | config QCOM_QMI_HELPERS |
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75 | 95 | tristate |
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76 | | - depends on ARCH_QCOM && NET |
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77 | | - help |
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78 | | - Helper library for handling QMI encoded messages. QMI encoded |
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79 | | - messages are used in communication between the majority of QRTR |
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80 | | - clients and this helpers provide the common functionality needed for |
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81 | | - doing this from a kernel driver. |
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| 96 | + depends on NET |
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82 | 97 | |
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83 | 98 | config QCOM_RMTFS_MEM |
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84 | 99 | tristate "Qualcomm Remote Filesystem memory driver" |
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.. | .. |
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94 | 109 | |
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95 | 110 | config QCOM_RPMH |
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96 | 111 | tristate "Qualcomm RPM-Hardened (RPMH) Communication" |
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97 | | - depends on ARCH_QCOM && ARM64 && OF || COMPILE_TEST |
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| 112 | + depends on ARCH_QCOM || COMPILE_TEST |
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| 113 | + depends on (QCOM_COMMAND_DB || !QCOM_COMMAND_DB) |
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98 | 114 | help |
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99 | 115 | Support for communication with the hardened-RPM blocks in |
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100 | 116 | Qualcomm Technologies Inc (QTI) SoCs. RPMH communication uses an |
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.. | .. |
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102 | 118 | of hardware components aggregate requests for these resources and |
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103 | 119 | help apply the aggregated state on the resource. |
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104 | 120 | |
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| 121 | +config QCOM_RPMHPD |
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| 122 | + tristate "Qualcomm RPMh Power domain driver" |
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| 123 | + depends on QCOM_RPMH && QCOM_COMMAND_DB |
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| 124 | + help |
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| 125 | + QCOM RPMh Power domain driver to support power-domains with |
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| 126 | + performance states. The driver communicates a performance state |
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| 127 | + value to RPMh which then translates it into corresponding voltage |
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| 128 | + for the voltage rail. |
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| 129 | + |
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| 130 | +config QCOM_RPMPD |
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| 131 | + tristate "Qualcomm RPM Power domain driver" |
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| 132 | + depends on PM |
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| 133 | + depends on QCOM_SMD_RPM |
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| 134 | + help |
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| 135 | + QCOM RPM Power domain driver to support power-domains with |
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| 136 | + performance states. The driver communicates a performance state |
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| 137 | + value to RPM which then translates it into corresponding voltage |
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| 138 | + for the voltage rail. |
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| 139 | + |
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105 | 140 | config QCOM_SMEM |
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106 | 141 | tristate "Qualcomm Shared Memory Manager (SMEM)" |
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107 | | - depends on ARCH_QCOM |
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| 142 | + depends on ARCH_QCOM || COMPILE_TEST |
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108 | 143 | depends on HWSPINLOCK |
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109 | 144 | help |
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110 | 145 | Say y here to enable support for the Qualcomm Shared Memory Manager. |
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.. | .. |
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113 | 148 | |
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114 | 149 | config QCOM_SMD_RPM |
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115 | 150 | tristate "Qualcomm Resource Power Manager (RPM) over SMD" |
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116 | | - depends on ARCH_QCOM |
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117 | | - depends on RPMSG && OF |
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| 151 | + depends on ARCH_QCOM || COMPILE_TEST |
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| 152 | + depends on RPMSG |
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118 | 153 | help |
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119 | 154 | If you say yes to this option, support will be included for the |
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120 | 155 | Resource Power Manager system found in the Qualcomm 8974 based |
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.. | .. |
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134 | 169 | depends on MAILBOX |
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135 | 170 | depends on QCOM_SMEM |
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136 | 171 | select QCOM_SMEM_STATE |
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| 172 | + select IRQ_DOMAIN |
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137 | 173 | help |
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138 | 174 | Say yes here to support the Qualcomm Shared Memory Point to Point |
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139 | 175 | protocol. |
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.. | .. |
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142 | 178 | tristate "Qualcomm Shared Memory State Machine" |
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143 | 179 | depends on QCOM_SMEM |
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144 | 180 | select QCOM_SMEM_STATE |
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| 181 | + select IRQ_DOMAIN |
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145 | 182 | help |
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146 | 183 | Say yes here to support the Qualcomm Shared Memory State Machine. |
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147 | 184 | The state machine is represented by bits in shared memory. |
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148 | 185 | |
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| 186 | +config QCOM_SOCINFO |
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| 187 | + tristate "Qualcomm socinfo driver" |
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| 188 | + depends on QCOM_SMEM |
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| 189 | + select SOC_BUS |
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| 190 | + help |
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| 191 | + Say yes here to support the Qualcomm socinfo driver, providing |
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| 192 | + information about the SoC to user space. |
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| 193 | + |
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149 | 194 | config QCOM_WCNSS_CTRL |
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150 | 195 | tristate "Qualcomm WCNSS control driver" |
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151 | | - depends on ARCH_QCOM |
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| 196 | + depends on ARCH_QCOM || COMPILE_TEST |
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152 | 197 | depends on RPMSG |
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153 | 198 | help |
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154 | 199 | Client driver for the WCNSS_CTRL SMD channel, used to download nv |
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.. | .. |
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156 | 201 | |
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157 | 202 | config QCOM_APR |
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158 | 203 | tristate "Qualcomm APR Bus (Asynchronous Packet Router)" |
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159 | | - depends on ARCH_QCOM |
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| 204 | + depends on ARCH_QCOM || COMPILE_TEST |
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160 | 205 | depends on RPMSG |
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| 206 | + depends on NET |
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| 207 | + select QCOM_PDR_HELPERS |
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161 | 208 | help |
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162 | | - Enable APR IPC protocol support between |
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163 | | - application processor and QDSP6. APR is |
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164 | | - used by audio driver to configure QDSP6 |
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165 | | - ASM, ADM and AFE modules. |
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| 209 | + Enable APR IPC protocol support between |
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| 210 | + application processor and QDSP6. APR is |
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| 211 | + used by audio driver to configure QDSP6 |
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| 212 | + ASM, ADM and AFE modules. |
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166 | 213 | endmenu |
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