add dts config

hc

2023-12-06 08f87f769b595151be1afeff53e144f543faa614

 kernel/drivers/soc/fsl/qe/qe_io.c
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@@ -1,3 +1,4 @@
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+// SPDX-License-Identifier: GPL-2.0-or-later
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 /*
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  * arch/powerpc/sysdev/qe_lib/qe_io.c
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  *
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@@ -7,11 +8,6 @@
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  *
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  * Author: Li Yang <LeoLi@freescale.com>
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  * Based on code from Shlomi Gridish <gridish@freescale.com>
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- *
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- * This program is free software; you can redistribute  it and/or modify it
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- * under  the terms of  the GNU General  Public License as published by the
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- * Free Software Foundation;  either version 2 of the  License, or (at your
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- * option) any later version.
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  */
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12
 
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 #include <linux/stddef.h>
..
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@@ -22,8 +18,6 @@
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18
 
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 #include <asm/io.h>
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 #include <soc/fsl/qe/qe.h>
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-#include <asm/prom.h>
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-#include <sysdev/fsl_soc.h>
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21
 
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 #undef DEBUG
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23
 
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@@ -34,17 +28,18 @@
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 {
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 	struct resource res;
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 	int ret;
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-	const u32 *num_ports;
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+	u32 num_ports;
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32
 
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 	/* Map Parallel I/O ports registers */
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 	ret = of_address_to_resource(np, 0, &res);
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 	if (ret)
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 		return ret;
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 	par_io = ioremap(res.start, resource_size(&res));
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+	if (!par_io)
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+		return -ENOMEM;
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40
 
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-	num_ports = of_get_property(np, "num-ports", NULL);
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-	if (num_ports)
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-		num_par_io_ports = *num_ports;
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+	if (!of_property_read_u32(np, "num-ports", &num_ports))
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+		num_par_io_ports = num_ports;
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43
 
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 	return 0;
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 }
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@@ -61,16 +56,16 @@
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 	pin_mask1bit = (u32) (1 << (QE_PIO_PINS - (pin + 1)));
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57
 
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 	/* Set open drain, if required */
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-	tmp_val = in_be32(&par_io->cpodr);
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+	tmp_val = qe_ioread32be(&par_io->cpodr);
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 	if (open_drain)
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-		out_be32(&par_io->cpodr, pin_mask1bit | tmp_val);
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+		qe_iowrite32be(pin_mask1bit | tmp_val, &par_io->cpodr);
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 	else
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-		out_be32(&par_io->cpodr, ~pin_mask1bit & tmp_val);
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+		qe_iowrite32be(~pin_mask1bit & tmp_val, &par_io->cpodr);
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64
 
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 	/* define direction */
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 	tmp_val = (pin > (QE_PIO_PINS / 2) - 1) ?
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-		in_be32(&par_io->cpdir2) :
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-		in_be32(&par_io->cpdir1);
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+		qe_ioread32be(&par_io->cpdir2) :
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+		qe_ioread32be(&par_io->cpdir1);
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 	/* get all bits mask for 2 bit per port */
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 	pin_mask2bits = (u32) (0x3 << (QE_PIO_PINS -
..
..
@@ -82,34 +77,30 @@
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 	/* clear and set 2 bits mask */
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 	if (pin > (QE_PIO_PINS / 2) - 1) {
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-		out_be32(&par_io->cpdir2,
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-			 ~pin_mask2bits & tmp_val);
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+		qe_iowrite32be(~pin_mask2bits & tmp_val, &par_io->cpdir2);
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 		tmp_val &= ~pin_mask2bits;
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-		out_be32(&par_io->cpdir2, new_mask2bits | tmp_val);
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+		qe_iowrite32be(new_mask2bits | tmp_val, &par_io->cpdir2);
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 	} else {
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-		out_be32(&par_io->cpdir1,
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-			 ~pin_mask2bits & tmp_val);
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+		qe_iowrite32be(~pin_mask2bits & tmp_val, &par_io->cpdir1);
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 		tmp_val &= ~pin_mask2bits;
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-		out_be32(&par_io->cpdir1, new_mask2bits | tmp_val);
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+		qe_iowrite32be(new_mask2bits | tmp_val, &par_io->cpdir1);
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 	}
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 	/* define pin assignment */
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 	tmp_val = (pin > (QE_PIO_PINS / 2) - 1) ?
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-		in_be32(&par_io->cppar2) :
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-		in_be32(&par_io->cppar1);
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+		qe_ioread32be(&par_io->cppar2) :
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+		qe_ioread32be(&par_io->cppar1);
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 	new_mask2bits = (u32) (assignment << (QE_PIO_PINS -
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 			(pin % (QE_PIO_PINS / 2) + 1) * 2));
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 	/* clear and set 2 bits mask */
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 	if (pin > (QE_PIO_PINS / 2) - 1) {
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-		out_be32(&par_io->cppar2,
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-			 ~pin_mask2bits & tmp_val);
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+		qe_iowrite32be(~pin_mask2bits & tmp_val, &par_io->cppar2);
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 		tmp_val &= ~pin_mask2bits;
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-		out_be32(&par_io->cppar2, new_mask2bits | tmp_val);
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+		qe_iowrite32be(new_mask2bits | tmp_val, &par_io->cppar2);
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 	} else {
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-		out_be32(&par_io->cppar1,
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-			 ~pin_mask2bits & tmp_val);
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+		qe_iowrite32be(~pin_mask2bits & tmp_val, &par_io->cppar1);
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 		tmp_val &= ~pin_mask2bits;
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-		out_be32(&par_io->cppar1, new_mask2bits | tmp_val);
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+		qe_iowrite32be(new_mask2bits | tmp_val, &par_io->cppar1);
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 	}
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105
 }
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 EXPORT_SYMBOL(__par_io_config_pin);
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@@ -137,12 +128,12 @@
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 	/* calculate pin location */
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 	pin_mask = (u32) (1 << (QE_PIO_PINS - 1 - pin));
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130
 
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-	tmp_val = in_be32(&par_io[port].cpdata);
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+	tmp_val = qe_ioread32be(&par_io[port].cpdata);
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132
 
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 	if (val == 0)		/* clear */
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-		out_be32(&par_io[port].cpdata, ~pin_mask & tmp_val);
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+		qe_iowrite32be(~pin_mask & tmp_val, &par_io[port].cpdata);
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 	else			/* set */
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-		out_be32(&par_io[port].cpdata, pin_mask | tmp_val);
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+		qe_iowrite32be(pin_mask | tmp_val, &par_io[port].cpdata);
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137
 
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 	return 0;
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139
 }
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@@ -151,22 +142,19 @@
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 int par_io_of_config(struct device_node *np)
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 {
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 	struct device_node *pio;
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-	const phandle *ph;
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 	int pio_map_len;
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-	const unsigned int *pio_map;
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+	const __be32 *pio_map;
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147
 
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 	if (par_io == NULL) {
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 		printk(KERN_ERR "par_io not initialized\n");
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 		return -1;
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 	}
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152
 
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-	ph = of_get_property(np, "pio-handle", NULL);
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-	if (ph == NULL) {
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+	pio = of_parse_phandle(np, "pio-handle", 0);
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+	if (pio == NULL) {
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 		printk(KERN_ERR "pio-handle not available\n");
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 		return -1;
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 	}
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-
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-	pio = of_find_node_by_phandle(*ph);
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158
 
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 	pio_map = of_get_property(pio, "pio-map", &pio_map_len);
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 	if (pio_map == NULL) {
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..
@@ -180,9 +168,15 @@
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168
 	}
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169
 
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 	while (pio_map_len > 0) {
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-		par_io_config_pin((u8) pio_map[0], (u8) pio_map[1],
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-				(int) pio_map[2], (int) pio_map[3],
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-				(int) pio_map[4], (int) pio_map[5]);
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+		u8 port        = be32_to_cpu(pio_map[0]);
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+		u8 pin         = be32_to_cpu(pio_map[1]);
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+		int dir        = be32_to_cpu(pio_map[2]);
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+		int open_drain = be32_to_cpu(pio_map[3]);
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+		int assignment = be32_to_cpu(pio_map[4]);
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+		int has_irq    = be32_to_cpu(pio_map[5]);
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+
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+		par_io_config_pin(port, pin, dir, open_drain,
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+				  assignment, has_irq);
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 		pio_map += 6;
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 		pio_map_len -= 6;
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 	}